The document is an examination paper for the Embedded Systems course at Thapar Institute of Engineering and Technology, detailing the structure and content of the end semester examination. It includes various questions on ARM processor architecture, assembly language programming, memory hierarchy, pipelining, AMBA, DMA controllers, and Thumb instructions. The exam is scheduled for May 11, 2023, with a total of 100 marks and a duration of 3 hours.
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UEC513 (2)
The document is an examination paper for the Embedded Systems course at Thapar Institute of Engineering and Technology, detailing the structure and content of the end semester examination. It includes various questions on ARM processor architecture, assembly language programming, memory hierarchy, pipelining, AMBA, DMA controllers, and Thumb instructions. The exam is scheduled for May 11, 2023, with a total of 100 marks and a duration of 3 hours.
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Thapar Institute of Engineering and Technology, Patiala
END SEMESTER EXAMINATION
B.E (ECE/ENC): Semester-IV (2022-23) Course Code: UEC513 Department: ECED Course Name: Embedded Systems May 11, 2023 Thursday, 09.00 - 12.00 Hrs. Time: 3 Hours, M. Marks: 100 Name of Faculty: KSS, HVR, DIN, SUK Note: Attempt all questions. Attempt all the parts of each question together. Assume missing data, if any. Q.1 (a) Draw and explain the data flow diagram of ARM processor. 8 (b) Write an ARM assembly language program to scan a series of ten 32-bit numbers to find 8 how many of them are positive. (c) Assuming the contents of R3 and R4 as: R3=0x0ff0Off0, R4=0x0ff0Off0. Find the values of 9 R1, R2, R5 and flags after execution of the following instructions: (i) SUBS R5, R3, #99 (ii) BICS R2, R3, R4 (iii) ADD RI, R3, R4, LSL #3 Q.2 (a) Given that the contents of RO is Ox01234567 which has to be stored in memory locations 6 0x00002000 to 0x00002003. What will be the contents of given memory locations when data is stored using: i. little endian format ii. big endian format 8 (b) What is memory hierarchy and how is it useful for an embedded system? Explain the memory hierarchal model of an embedded system. 5+6 (c) Compare the direct, and set associative styles of memory mapping. Consider a direct . mapped cache of size 512 KB with block size 1 KB. There are 7 bits in the tag. Find: i. Number of bits in the index and offset fields. ii. Size of main memory Q.3 (a) What are the merits of 5 stage pipelined structure over 3-stage pipelined structure. The 3+6 following sequence of instructions has to be executed in a 5-stages pipelined ARM processor: . ADD RI, R2, R3 SUB R4, RI. R5 AND R6, R2, R7 • . OR R8, R1, R9 XOR R10. RI. R11 Calculate the number of data hazards that can occur in the program w ithout and with data forwarding technique using suitable diagram. (b) How an AMBA is helpful to increase the overall speed of an embedded system? Draw and 8 explain a typical AMBA based complete embedded System. (c) What is the role of DMA controller? Draw and explain the operation of DMA controller 8 with neat diagram. Q.4 (a) Explain the following Thumb instructions with suitable example: 10 i. LDR ii. POP iii. LSL iv. BX v. MOV (b) Differentiate between Thumb and ARM states of operation? Write the various steps for 3+4 entering and exiting the Thumb mode of operation. (c) What is the need of coprocessors? Draw and explain the interfacing diagram of ARM 2+6 coprocessor.