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loc & los , clock gating

The document discusses two methods for testing digital circuits: Lunch Off Shift (LOS) and Lunch Off Capture (LOC), highlighting their advantages and limitations. It also explains clock gating as a technique to reduce power consumption in digital designs by turning off the clock when not needed, detailing two implementation techniques: intent-based and tool-generated clock gating. Additionally, it addresses potential issues with glitches in clock gating and suggests solutions to ensure stable clock outputs.

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sharath A
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14 views4 pages

loc & los , clock gating

The document discusses two methods for testing digital circuits: Lunch Off Shift (LOS) and Lunch Off Capture (LOC), highlighting their advantages and limitations. It also explains clock gating as a technique to reduce power consumption in digital designs by turning off the clock when not needed, detailing two implementation techniques: intent-based and tool-generated clock gating. Additionally, it addresses potential issues with glitches in clock gating and suggests solutions to ensure stable clock outputs.

Uploaded by

sharath A
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Lunch off shift (LOS):

This is the most simple method to adopt for scan. With this the size of generated
pattern will be low. But The shift enable goes from high to low in between
lunching and capturing pulses. See the below figure. So, if we want to run at-
speed test of a high speed circuit it will critical case for lowering shift enable for
all flops. So, in industry people mostly use LOS patterns to test stuck-at faults.

Lunch off capture (LOC):

Unlike LOS, here we do both lunching and capturing with shift enable =0. So, we
can test the circuit at high frequency with out touching shift enable. But these
type of test vector comes with higher memory size, and need better and
expensive ATE setup.

.
Clock Gating is defined as: “Clock gating is a technique/methodology to
turn off the clock to certain parts of the digital design when not needed”.

The Need for Clock Gating

With most of the SoCs heavily constrained by power budgets, it is of utmost


importance to reduce power consumption as much as possible and clock
gating is one of the simplest and most used method to reduce the dynamic
power of the design. The concept is simple. Turn off the design when not
needed – without effecting the functionality. By turning off the clock to the
design/system, essentially the switching activity of the design is reduced and
thus dynamic power. Clock gating can be applied to smallest part of digital
design (a single FF) up to complete subsystems or entire SoCs.

Clock Gating Techniques

Generally, there are two different techniques of implementing clock gating.

1. Intent based Clock gating – This type of clock gating is introduced into the design as
part of functionality through RTL.
2. Tool generated clock gating – This type of clock gating is introduced by tools during
synthesis by identifying all the Flip Flops sharing same control logic and enabling all
those FFs when needed.

We will only focus on first type of Clock gating here. Normally, complete clock
gating strategy is defined in the architecture of the system and then designers
implement that strategy. There are different techniques to implement the clock
gating.

Clock Gating Overview

In simplest form a clock gating can be achieved by using an AND gate as


shown in picture below
Figure 1: AND gate-based clock gating

The clock enable signal, generated by a combinatorial logic, controls when to


provide the clock to the downstream logic (FF in the above figure). When
enable is 1, the clock will be provided to FF and when enable is 0, the clock
will be turned off and thus FF will not be active.

However, this simplest form of clock gating technique has some problem of
generating glitches in the clock provide to the FF, which are not desirable.

Figure 2: Glitches in enable/gated clock

These glitches can be removed by introducing a negative edge triggered FF


(assuming downstream FFs are positive edge) or low-level sensitive latch at
the output of the clock enable signal.
Figure 3: Latch based clock gating

This will make sure that any glitch in the clock enable signal will not be visible
to the gated clock output. The Latch output will only be updated during the
negative clock cycle and thus input to AND gate will be stable high.

Figure 4: Glitch Free Gated Clock

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