Proceedings of the Second International Conference on Electronics and Renewable Systems (ICEARS-2023).

IEEE Xplore Part Number: CFP23AV8-ART; ISBN: 979-8-3503-4664-0

An Improved Miller Compensated Two Stage CMOS

Operational Amplifier
2023 Second International Conference on Electronics and Renewable Systems (ICEARS) | 979-8-3503-4664-0/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICEARS56392.2023.10085073

Yaram Thulasi 1, K.Lokesh Krishna 2, D.Srinivasulu Reddy 3, Veligaram Hemanthi 4, Thotli Bhargav Reddy 5 & Tata Lalithapriya 6
Electronics and Communication Engineering department
Sri Venkateswara College of Engineering.
Tirupati, Tirupati district, A.P., India
1
[email protected], 2 [email protected], [email protected], [email protected],
5
[email protected], [email protected]

Abstract— The design of a power efficient and high speed capacitances i.e. current flowing during rail-to rail operation
integrated circuits is complex and even more challenging with the of the circuit. The static power dissipation occurs due to the
current trend towards reduced supply voltages. The work flow of static and leakage currents when the input voltage is
presented in this paper is a High gain, High slew rate, wide ban d
held constant. Small currents of the order of nanoamperes or
two-stage compensated CMOS operational amplifier. An
uncompensated operational amplifier is prone various instability microamperes usually flo w under these conditions, whereas
problems. Modified Miller compensation scheme with Cascoded the short circuit power dissipation results due to the fact that
current mirrors and pole zero cancelation techniques are utilized both NMOS and PMOS transistors are conducting when the
in this design to overcome the various instability problems inputs make a transition fro m lo w to h igh state and vice-versa.
mentioned in this work. The proposed work involves assumptions The dynamic power accounts for the majority of the power
of specifications for a specific application, theoretical design consumed in any CMOS integrated circuit. The expression for
calculations, simulation and verification using Cadence tools. In total power dissipation (Ptot ) is written as
order to verify the theoretical designed values, the proposed
compensated two stage CMOS operational amplifier was
(1)
designed and simulated in 90nm CMOS technology using
Cadence Virtuoso tool at an operating voltage of VDD=1.8V. The
important parameters such as direct current gain, phase margin, Let Vn swing be the voltage swing at the nth node. It is equal to
power dissipation, CMRR, unity gain-bandwidth, slew rate was VDD , where VDD is the applied dc voltage to the circuit, Cld is
verified with the theoretical values. the load capacitance at node ‘n’ , Ish be short-circuit currents, Il
be the leakage currents due to temperature and other effects
Keywords— amplifier, compensating circuit, phase margin, and αn is the switching activity factor at node ‘n’.
stability, settling time and CMOS design.

I. INT RODUCT ION Further equation (1) is written as

Fro m the beginning of this century, the usage of portable

electronic gadgets has been ubiquitous in all the day -to-day ∑
applications. In this way, it has become more accessible. Few
frequently utilized examples include such as pocketalk
language translator, Bluetooth key finder, W i-Fi hotspot ∑
devices, hearing aids, s mart health trackers, core mini-
speakers, personal dig ital assistants, paging devices, mob iles,
laptops and tyre inflators etc. The portable gadgets dictate
Fro m the above exp ression it is evident that the total power
lesser currents for conduction to guarantee a rational battery
dissipation is proportional to the square of the applied dc
life t ime. So in the design of portable gadgets the main
voltage when the voltage swing at the nodes is approximately
specification to be considered has been ultra-lo w power
VDD . Th is means that as the applied dc voltage is scaled down,
requirement. At the circuit level, the design should be more
so does the corresponding currents flowing in the circuit. It
focused on a reduced DC supply voltage which is a high
corresponds to a reduction in power dissipation of the circuit.
requirement to assure a rational longer operating battery
The same scaling factor doesn’t hold true for frequency of the
lifetime. The reduced DC supply voltage results in a drop in
clock signal and the circuit delay. The power consumed by a
thermal dissipation of the electronic gadget. The various types
CMOS integrated circuit decreases when the applied dc
of power dissipation occurring in an integrated CMOS circuit
voltage VDD reduces, whereas the same doesn’t hold good for
design are switching (Psw ) or dynamic power dissipation (Pdy ),
increase in operating speed of the circuit . So the integrated
static power dissipation (Pst ) and short circuit power
circuit designers choose to make a trade-off between the
dissipation (Psc). The switching power dissipation occurs as a
power dissipation of a gate and the propagation delay. As
result of the t ransistors switching activity at circuit node

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 Proceedings of the Second International Conference on Electronics and Renewable Systems (ICEARS-2023).
IEEE Xplore Part Number: CFP23AV8-ART; ISBN: 979-8-3503-4664-0

technology scales down, it results in signal-to-noise ratio of configured as comparator circuit was used at the input stage of
the circuit. a four-bit flash ADC as presented in [3]. A total of fifteen
comparators were used in the design which operated with
One of the important circuits to be incorporated on the reduced kick-back noise. Yadav et al. described the design and
silicon die is the Co mplementary Metal Oxide Semiconductor analysis of a comparator circuit for use in a three-bit Flash
(CM OS) Operational A mp lifier (Op-A mp). Operational ADC. An op-amp is configure to work as a comparator circuit
Amplifier circuits are ubiquitous and are very key modules in and consumed a 431 microwatts of power. It also exhibited
the design and implementation of miniaturized integrated very low offset voltage [4]. A wideband operational amplifier
circuits used in every application. Also they are the very designed at 1GHz for use in a four bit pipelined analog to
fundamental building blocks in Analog circuits design, Digital digital converter is presented in [5]. The operational amplifier
circuit design, Co mpensating circuits and Mixed signal circuit uses miller capacitor to increase phase margin and reduce
designs. The performance of any integrated circuit is settling times. In [6], a zero offset voltage CMOS operational
susceptible to the proper design considerations considered in amplifier is simu lated and exp lained. The amplifier circuits
the CMOS operational amp lifier. Industrial systems based on exh ibited a 300 microvolt offset voltage and a gain of upto
solid-state operated analog control systems have been replaced 80d B. Parthipan et al. described the design procedure of an
with CMOS technologies. With the emergence of state of the efficient CMOS op-amp simulated in 90n m process. A trade-
art and narrow device aspect ratios, these operational amplifier off between different specifications have been in this work [7].
circuits have turn out to be the key modules in the An automated approach of model parameters extraction fro m
implementation of various ADC (analog to digital converter) the tentative data measured at low and high temperatures is
circuits, signal processing systems, DAC (digital to analog proposed in [8]. Liu et al. designed a high efficient rail to rail
converter) circuits, signal transduction, analog instrumentation class-AB operational amplifier that consists of adaptive output
design, biomedical processing of signals, threshold detectors, stage and gain boost loop to offer higher gain values, low slew
voltage buffers, mixed signal systems, analog computation and rates and less power consumption [9]. A three-stage miller op-
performing the tasks such as higher order active filtering of amp circuit using a composite stage that increases the
signals, amplification of signal voltages, and ultra-high speed transconductance and gain bandwidth product is presented in
conversion of signals. [10]. The op-amp parameters are analyzed both in strong
inversion and subthreshold regions and the designs are
CMOS Operational amplifier circuits are high-gain simulated at 130n m technology. Pourashraf et al. proposed a
amplifiers that contains dual differential input stages and call—A B Miller op-amp with increased effective drive voltage
unbalanced output stage. Ideally the single chip operational values, unity gain bandwith and high values of slew rate. The
amplifiers offer ensure infinite bandwidth, infinite output circuit uses both phase lead and miller capacitance
voltage swings, infinite voltage gain, zero output resistance, compensations [11]. Sadeqi et al. described the procedure of
infin ite slew rate, infinite PSRR(power supply rejection ratio), robust CMOS op-amp using compensation elements for
infin ite CMRR (co mmon mode rejection ratio), high gain enhanced stability [12].
bandwidth product and infinite input resistance. Since the
practical open loop gain of the op-amp is at higher levels, The outline of the proposed work is as follows. Section -II
negative feedback is incorporated so as to stabilize the gain at presents the details related to two stage CMOS operational
frequencies of interest. amplifier that contains design equation and its design. Section -
III shows the simulated results of the op-amp circuit. Finally
Single stage operational amplifier circu its exh ibit Section-IV describes the conclusions of the proposed two-stage
reasonable gain and bandwidth values. The drawback of this CMOS operational amplifier.
configuration is that the open loop non-linear effects are not
removed significantly. The designs of Multi-stage amplifiers II. DETAILS OF DESIGN
are comp lex in nature as well co mpensation techniques are
very difficult to design. Other drawbacks include h igher power
The two-stage CMOS operational amp lifier is the most widely
dissipation, large circuit area and interference effects Hence in
order to improve the closed loop accurateness and linear used amplifier configuration because it provides rail to rail
dynamic range of operation, a two stage CMOS operational output voltage swing, higher bandwidth, higher slew rate
amplifier is used. By proper design of settling time values, the values, increased input resistance and decreased output
accuracy and speed of the two-stage operational amplifier is resistance. In general negative feedback is applied to
enhanced. operational amplifiers. An uncompensated two-stage
operational amplifier exh ibits a two-pole transfer function, and
Prokopenko et al. proposed a modified a op-amp is positioned further down the unity-gain bandwidth. These
architecture to generate low offset voltage. The authors carried two-pole transfer functions severely degrade the phase margin
out simulat ion using LTSpice, with operating temperature
at crossover frequencies [13]. Also more than two poles in the
between -197°C to 27°C exh ibits an open loop gain of 60dB
[1]. A comp lete design and analysis of op-amp for digital to circuit make the circuit to beco me unstable. Without
analog converter application is described in [2]. Various compensation, a two stage operational amp lifier exh ibits a
amplifier circuits with resistive and active loads were analyzed phase marg in less than 40 degrees. To achieve good stability,
and it was found that differential amplifier consumes lower the phase margin of the amplifier needs to be at least greater
power and an operational amplifier offered highest gain of all than 55 degrees. Hence it is very much vital to include
the configurations. A high speed and high wideband op-amp frequency compensation circuitry in the operational amplifier

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 Proceedings of the Second International Conference on Electronics and Renewable Systems (ICEARS-2023).
IEEE Xplore Part Number: CFP23AV8-ART; ISBN: 979-8-3503-4664-0

to operate it in stable conditions at all the operating voltages

and currents. In this work pole splitting using miller effect is
used. The general b lock d iagram of a two-stage CMOS
operational amp lifier using miller co mpensation technique is
shown in Fig.1 [14]-[15].

Fig.1: Block diagram of Miller compensated two stage op-amp

In a closed loop negative feedback system, the expression Fig.2: Pole-Zero plot of the two stage amplifier
form phase margin at unity open-loop gain is given by

[ ] (3) III. SIMULATION RESULTS

The closed loop gain is given by

(4)

Using the small-signal model, the poles (P1 and P2 ) and zero is
given by

(5)

( ) (6)

(7)

The gain of the compensated amplifier is written as

( )

[ ] [ ]
Fig.3: Schematic of T wo-stage amplifier

Fig. 2, shows the pole-zero plot of the two-stage operational

amplifier.

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The important specifications considered in this design are as

follows: gain-80 decibels, Phase Margin greater than or equal
to 60 degrees, Slew Rate ≥ 60V/μs, Power Dissipation ≤
0.8mW, Co mmon Mode Rejection Rat io (CM RR) ≥
70decibels, Output Swing ≥ ±1.5V, Offset voltage ≤ ±10mV,
Gain Bandwidth product ≥ 800M Hz and power supply
voltage=1.8V. Fig.3 shows the schematic diagram o f designed
two-stage operational amplifier simu lated in 90n m CMOS
technology. The transistors are assumed to be operated in
saturation region. DC analysis simulation with respect to
temperature variation is plotted in Fig. 4.

Fig. 4: DC response analysis

Transient response simulat ion is performed to calcu late the

peak to peak operating voltages and currents. A pulse width of Fig. 6: Magnitude plot and Phase plot
one microsecond with a t ime-period of three microseconds is
applied at the input terminals. Fig. 5 presents the transient
analysis response.

Fig. 5: T ransient analysis responses Fig.7: Simulated power response

AC response analysis containing both magnitude and phase The output power calculations of the two-stage operational
responses are performed to calculate DC gain, Phase margin amp lifier are presented in Fig.7. Fro m the simu lated results
and unity gain bandwidth. To carry out these calculations, an power dissipated at the peak output is calculated as 12.38
input signal of 1 microvolt of opposite phase is registered at micro watts. Fig. 8 shows the response related to output noise
the input side of the two-stage op-amp. The Bode plot and input noise in microvolt/ sqrt(Hz). Tab le I, presents the
containing both magnitude plot and phase plot versus obtained simulated parameters of the proposed miller
frequency is presented in Fig. 6. A Gain of 76dB, Phase compensated two stage operational amplifier.
margin of 68°, and a Gain bandwidth product of 860MHz are
observed from the simulated graphs.

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