design

Edited by Bill Travis and Anne Watson Swager

ideas
Delay line aids in one-shot simulations
Christophe Basso, On Semiconductor, Toulouse, France

any designers use small pulse small pulse generator. The operating 2 shows the signals associated with the

M generators to delay signals, open

timing windows, drive sam-
ple/hold circuits, and other functions.
principle of the circuit lies in applying
two “1” levels to the AND-gate input be-
fore the delay line switches high. Figure
circuit in Figure 1. Listing 1 shows
netlists for Intusoft’s IsSpice4 and Ca-
dence’s PSpice.
Though the hardware implementation of
these generators does not pose any prob-
lems, the lack of dedicated circuitry
sometimes puzzles the Spice simulation INPUT SIGNAL
of the system. A common approach to
this problem is to implement a time con-
stant involving a resistor, a capacitor, and
a comparator. Unfortunately, each time DELAY-LINE OUTPUT
you need a time constant, you must re-
calculate the resistor value, the capacitor
value, or both. Despite the fact that inline
equations can do this job for you, delay INVERTER OUTPUT
lines can often offer a smarter solution.
Figure 1 shows the implementation of a

ONE-SHOT OUTPUT

X5
X6
UTD X8 AND2
TD41m INV
Out
In utd
2 3

21 mSEC 25 mSEC 29 mSEC 33 mSEC 37 mSEC

A one-shot multivibra- This plot shows timing details for Figure 1’s Spice model.
Figure 1 tor (shown with Spice Figure 2
nomenclature) makes a simple short-pulse gen-
X1 X3
erator. A1 SMALLPULSE X2 SMALLPULSE
PWMGEN VPULSE DELAY=70 nSEC INV DELAY=20 nSEC SMP

PWM
1 2 3
SMALLPULSE SMALLPULSE
VTRIGGER
Delay line aids
in one-shot simulations..............................129
X4
Sine-wave generator outputs MUL X5
PSW1
precise periods ............................................132 A
K*A*B VSAMPLED
V1 6 4
High-voltage current-feedback B
` 5 CSH RDR
amplifier is speedy ......................................136 SINE + 10 pF 1M
MODULATION
AC-power monitor SMP
uses remote sensing ..................................138
This PWM application is a sample/hold circuit in Spice-simulation nomen-
Figure 3 clature.

www.ednmag.com April 26, 2001 | edn 129

design
ideas
Figure 3 shows a typical application
circuit for the one-shot multivibrators.
You can use IsSpice4 or PSpice to simu-
late this sample/hold circuit. Figure 4
shows the waveforms associated with the 70 nSEC

circuit in Figure 3. A PWM signal (top

waveform) generates a kind of arbitrary
staircase signal. The multiplier, X4, sinu- S/H TRIGGER
soidally modulates the PWM signal. The
circuit cascades two small pulse genera-
tors (SMALLPULSE). One creates a de-
lay signal to sample at a given time (X1,
70 nsec); the other calibrates the width
MODULATED SIGNAL
(X3, 20 nsec) of the sampling signal (sec-
ond waveform). The third waveform in
Figure 4 shows the sinusoidally modu-
lated signal; the fourth waveform is the
sampled signal. You can download the Is-
Spice4 and PSpice listings for three one-
S/H OUTPUT
shot types from EDN’s Web site, www.
ednmag.com. Click on “Search Databas-
es” and then enter the Software Center to
download the file for Design Idea #2680. 100 nSEC 300 nSEC 500 nSEC 700 nSEC 900 nSEC

Is this the best Design Idea in this

Figure 4
issue? Vote at www.ednmag.com/edn These timing signals illustrate the operation of Figure 3’s circuit.
mag/vote.asp.

LISTING 1—NETLIST FOR MONOSTABLE SHORT-PULSE GENERATOR

130 edn | April 26, 2001 www.ednmag.com

 design
ideas

Sine-wave generator outputs precise periods

JM Terrade, Clermont-Ferrand, France

ectangular pulse generators, cise number of periods. The signal

R even at high frequencies,

are easy to design. How-
ever, the design becomes more diffi-
F i g u r e 1
END
COUNT
ENABLE SIGNAL
GENERATOR
SIGNAL
OUTPUT
has to start and stop exactly at 0V.
The scheme in Figure 1 can produce
one to 15 periods of a 20-MHz sinu-
cult if you need a signal that contains TRIGGER TRIGGER
INPUT DOWN INPUT SYNC
a precise number of periods with a si- COUNTER COMPARATOR A signal generator, down counter, and
nusoidal shape. Although it is easy to comparator can produce an output signal
produce a good sine wave, the diffi- N
that contains a precise number of sine-
culty is producing a signal with a pre- (NUMBER OF PULSES) wave periods.

5V

14
Figure 2 VDD 2
1 100 nF
A B
13 100 nF 3.3k
C 1 nF 10 nF 47k
IC4A VSS 1 5V
5V S
7 1 10 3 4 SIGNAL
100 nF 25V OUT
4 REF IIN A0 A1 19
3 OUT
A B 5 COSC
7 R2 5 5V
R3 C1
2 3
+ 6 10
G C
22 pF V`
17
1k IC4B 6 IC1 100 nF
2 GND
2 MAX038 9
LF356N 8 7 GND1
4 A B 9 DADJ
20 100 nF
6 C 8 V1
3.74k FADJ
IC4C
25V PDO PDI SYNC DGND DV` GND2 GND3 GND4 25V
12 13 14 15 16 2 11 18
100 nF 11 A B
100 nF 10
12 C 100 nF
100
IC4D
15V
5V

Q1 R1 10
E VP0106 10
8
IC3C 9
100 nF

C2 5V
13
11
10 nF
IC3D 12 F
100 nF
5V
330 4
6
5 IC3B
25V
100 nF
100 nF 7

2
1 3
A VCC IC3A 1 C D
5V
A 2 12 4 16
TRIGGER IC5A
B CTEN
IN 10 nF 74LS123 MIN-MAX
14 13 B 11 100 nF
C
15 Q LOAD IC2
1k R/C 74AC191 14
V+ 3 CLK
CLR
D0 D1 D2 D3 UP-DN
8 3 2 6 7 8 5 5V
S1
8 ON 1 470
1
7 2 470
2
6 3 470
3
5 4 470
4

IC1 contains the generator and comparator. The sync signal at point F drives the counter, IC2. The setting of S1 determines the end of count and thus
the number of periods, N, at the output.

132 edn | April 26, 2001 www.ednmag.com

design
ideas
soidal wave. The scheme has two main
characteristics: The positive edge
of a 5V signal triggers the input, Figure 3
and the output is one to 15 periods of a
20-MHz signal, adjustable to within
610%.
Initially, the trigger input is inactive,
the generator is disabled, and the count-
er is loaded with the number N. When
the trigger input becomes active, the
counter waits, and the end-count output
enables the generator. A sine wave ap-
pears at the output. At the end of each
period of the sine wave, the comparator
produces a sync signal that drives the
counter’s clock input. When N periods of
the output wave have occurred, the end-
count signal disables the generator.
In the actual circuit, a MAX038, IC1,
is the generator (Figure 2). This IC con-
tains the sine-wave generator and the
comparator. The sync signal is available
at Pin 14. The counter has to be fast
enough to stop the generator before the
next output period starts. The 74AC191,
IC2, is a 4-bit up/down counter with pre-
set inputs. NAND gates IC3A and IC3B dis-
able the counter after the end-count goes
active. A one-shot circuit, IC5A, ensures A timing diagram that corresponds to three periods shows the precise sine-wave output at S.
that the input trigger pulse is long
enough to allow 15 pulses. A MOS TABLE 1—WAVEFORM-SHAPE SETTINGS resistance. The switches ap-
switch, IC4, short-circuits the oscillator A0 A1 Waveform
ply the voltage at G to Pin
capacitor, C1, to stop IC1’s generator. If X 1 Sine
5 of IC1, which stops the in-
the circuit simply grounds C1 to stop the 0 0 Square
ternal oscillator. The levels
generator, the output voltage is not zero. 1 0 Triangle
at the signal output and at
To obtain a zero output voltage, the cir- the sync output, F, depend
cuit connects input Pin 5 of IC1 to a neg- on the voltage at Pin 5. The
ative 0.5V-dc voltage generator compris- continuously loading the number N that voltage at F needs to be 5V, and the volt-
ing an LF356N and associated com- you program using S1. The level at D is age at Signal Out needs to be as close to
ponents. high, and the counter can’t run. The volt- 0V as possible. You need to carefully ad-
Because the signal at Pin 5 of IC1 goes age at C is low. The circuit connects just R3 to match these conditions. The
positive and negative, IC4’s switch re- NAND gates IC3C and IC3D in parallel to output voltage is just over 0V when G is
quires a 65V supply. The level for the provide more current to drive Q1 faster close to 20.5V.
command signal also has to swing posi- during switching. C2 is also necessary to When the trigger input goes high, one-
tive and negative. MOS transistor Q1 pro- drive Q1 faster. These NAND gates invert shot IC5A starts running. The voltage at B
vides the level-shifting from 0 to 5V log- the level at D, and Q1 is on, driven with also goes high for 10 msec. This delay
ic levels to 65V, or 4016, logic levels. 0V through R1. Thus, a 5V level is pres- must be longer than 16 periods of the
NAND gates IC3C and IC3D allow a fast ent at E, and the IC4 switches are on. Po- output signal. The voltage at D now goes
drive for Q1. tentiometer R3 controls the voltage at G; low and enables the counter. As before,
The circuit’s operation consists of the LF356N acts as a voltage follower. The IC3C and IC3D invert the level at D, and the
three timing periods: load N with trig- 10V resistor, R2, prevents oscillations 5V drive turns off Q1. A 25V level is
ger input inactive, down-count with trig- during switching. C1 and the MAX038 present at E, and IC4 switches are off. The
ger input high, and disabled (Figure 3). input represent the charge impedance. internal oscillator of IC1 is now running,
When the trigger input is inactive, one- The four switches of IC4 connect in par- and a signal is present at the output, S.
shot IC5A is inactive. The level at Point B allel to present a lower resistance of Each time the output signal is positive,
in the circuit is low, and counter IC2 is 200V/4, or approximately 50V, of total the sync output at F is also positive. At the

134 edn | April 26, 2001 www.ednmag.com

design
ideas
end of each period, a positive-going edge Q1. A 5V level is present at E, and IC4 cuit for one to 15 pulses. The circuit can
appears at F. Each positive edge at F switches are on. The internal oscillator of produce other signal shapes, depending
makes counter IC2 count down by one. IC1 stops, and the output signal at F re- on how you connect A0 and A1 of IC1
When the circuit has produced N pe- turns to zero. Before returning to the (Table 1). You can also replace S1 with a
riods at S, the voltage at C goes high, original state, the signal at B should re- mC to produce any pattern of pulses.
which indicates end of count. The volt- turn to zero, which happens after the end
age at D goes high and disables the of the delay that one-shot IC5A produces. Is this the best Design Idea in this
counter. IC3C and IC3D invert the voltage All is now ready for another train of issue? Vote at www.ednmag.com/edn
at D, and the resulting 0V drive turns on pulses. Using S1, you can program the cir- mag/vote.asp.

High-voltage current-feedback amplifier is speedy

Joseph Ting, Institute of Atomic and Molecular Sciences of the Academia Sinica, Taipei, Taiwan
he circuit in Figure 1 powers a mi-

T croparticle and nanoparticle

ion trap through a 1-to-5-
turns-ratio, high-voltage transformer. It
Figure 1
R2
150 D4 C1
230V

0.01 mF
1 kV
also works successfully as a driver for a R1 20V 0.1 mF
D1 R3 1W
560 Q4
piezo-tube scanner and in a near-field LED 100
2N2907 +
47 mF
scanning optical microscope. The circuit 400V
is robust and works with supplies rang-
ing from 650 to 6230V. The measured Q1
R4
30 2.4
parameters at 6230V supply voltage are 2N2907 1 1W
IC2
gain of 26-dB from dc to 23-dB point at 2 EL 6
33
1W
7 MHz; output swing of 6200V, rise and 100k
2003CN
Q2
4 MTP
fall times of 70 nsec for an output step of 0.01 mF MTP
2N50E
2P50E
350V, slew rate of 4100V/msec, and sup-
D3
ply current of 56 mA. 1N914
The red LEDs, D1 and D2, in Figure 1 C3955 Q3 10 VOUT
15V A1381 R5
provide a 1.8V drop; the LEDs are more 1W 100k
VIN 1W 6.2V
rugged than precision IC voltage refer- 1k IC1 1
2 EL 6
ences. The current supply for IC1 comes 2003CN
R8 R6 R7
from R1 and the source comprising D1, R2, 1k 4 2.4k 2.4k
240
R3, and Q1. R3’s trimmed value is such 1W 1W
Q7
that Q2’s quiescent current is approxi- 15V A1381
10
Q6
mately 15 mA. You can determine this 1W
C3955
current by measuring the voltage drop 100k MTP
1N914
across R4. The same adjustment also con- 0.1 mF 1W 2P50E

trols the output-voltage offset. IC2 is a MTP

2N50E
unity-gain, high-current driver for Q2. D3 100k IC3
1

prevents IC2’s input from going more 2 EL 6

1W
2003CN
negative than its negative supply. Q3, D4, 33
2.4
2N2222 4
C1, and R5 provide the negative bias for 30
IC2. Q4 is an output-current limiting 0.01 mF
switch. Q4 starts to turn on at IOUT5290 D2
1 kV
100 2N2222
mA. You can replace the bipolar transis- LED
560 20V 0.1 mF
tors C3955 (npn, Q2 and Q6) and A138 150 1W
(pnp, Q3 and Q7) by equivalents as long +

as they have the following minimum 47 mF

specs: VCEOM250V; ICM100 mA, and 2230V 400V

fTM100 MHz.
You should mount all the power tran- This high-voltage, current-feedback amplifier slews at 4100V/m msec.

136 edn | April 26, 2001 www.ednmag.com

design
ideas
sistors in individual finned heat R7 may result in excessive dissi-
sinks with an overhead 3-in. fan pation. Do not change the val-
for cooling. The pc-board layout ue of R8, because it is optimized
is not critical and needs no for speed. Be cautious when
ground plane. However, you measuring and using this cir-
must use single-point ground- cuit, because it harbors lethal
ing to minimize ringing. For the voltages. The National Science
component values shown, the 50V/DIV Council of Taiwan sponsored
circuit is very stable and needs this project.
no compensation capacitors.
Figure 2 shows a large-signal re-
sponse for a 69V, 1-MHz
square-wave input. This circuit
has a fixed gain of 20. For high-
er gains, you can increase 100 nSEC/DIV
the values of R6 and R7. Figure 2
For lower values, it is better to Is this the best Design Idea in
insert an attenuator at the input, The circuit has a clean square-wave response with minimal over- this issue? Vote at www.edn
because smaller values of R6 and shoot and no ringing. mag.com/ednmag/vote.asp.

AC-power monitor uses remote sensing

Sanjay R Chendvankar, Tata Institute of Fundamental Research, Colaba, Mumbai, India
he detection circuit in the Design

T Idea “Circuit monitors ac-power

loss” (EDN, Nov 24, 1999, pg 172) re-
quires a physical connection with the
ANTENNA
9
IC1D 10
PIEZO-
BUZZER
S1
mains to sense the power loss. The circuit
9V
in Figure 1 senses the power loss through D1
the radiated power-line signal. The bat- 3 IC1A
1 2
5 IC 4
1N914
7 IC1C 6 11 12
IC1E +
tery-operated circuit has a quiescent-cur- 4049
8
1B
9V
1 BATTERY
rent drain of approximately 2 mA. The R1
antenna, which is either a telescopic an- 2.2M C1
0.1 mF
1W
tenna or simply an approximately 2-ft- 8
14
IC1F
15
long wire, intercepts the radiated
power-line signal. The CMOS in- Figure 1
verters, IC1A and IC1B, amplify this weak
signal and convert it into a digital signal. A low level at the outputs of IC1D, IC1E, and IC1F activates the piezo-buzzer and warns of ac-line
D1 and C1 generate a steady dc voltage at failure.
the input of IC1C. D1 prevents discharge
of C1 through the output of IC1B when low; hence, the levels of IC1D, IC1E, and deactivates the buzzer. You can turn S1 on
the square wave at this output periodi- IC1F are high, and the buzzer is off. When after ac power resumes.
cally goes to a low level. Inverters IC1D, the ac power fails, the output of IC1B goes
IC1E, and IC1F connected in parallel en- low; C1 discharges through R1; and IC1D,
hance the current-sink capacity for sink- IC1E, and IC1F go low. This level activates Is this the best Design Idea in this
ing the piezo-buzzer current. When the the piezo-buzzer and warns of ac-line issue? Vote at www.ednmag.com/edn
ac mains is present, the output of IC1C is failure. Switching off the battery power mag/vote.asp.

138 edn | April 26, 2001 www.ednmag.com