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8085 INTERRUPTS

The document explains the concept of interrupts in the 8085 microprocessor, which allow the processor to switch control to higher priority tasks. It categorizes interrupts into software and hardware, vectored and non-vectored, and maskable and non-maskable types, detailing examples for each. Key interrupt signals include TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR, with associated interrupt service routines (ISRs) and interrupt vector addresses (IVAs).

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13 views1 page

8085 INTERRUPTS

The document explains the concept of interrupts in the 8085 microprocessor, which allow the processor to switch control to higher priority tasks. It categorizes interrupts into software and hardware, vectored and non-vectored, and maskable and non-maskable types, detailing examples for each. Key interrupt signals include TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR, with associated interrupt service routines (ISRs) and interrupt vector addresses (IVAs).

Uploaded by

neelu kumari
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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8085 INTERRUPTS

Interrupt is the mechanism by which the processor is made to transfer control from its current
program execution to another program having higher priority. Interrupts are the signals generated
by the external devices to request the microprocessor to perform a task.
The program or the routine that is executed upon interrupt is called interrupt service routine
(ISR). After execution of ISR, the processor must return to the interrupted program.
The address of the memory where the ISR is located for a particular interrupt signal. This address
is called interrupt vector address (IVA).
There are 5 interrupt signals in 8085 microprocessor:
TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
Classification of interrupts

1. Software and Hardware Interrupts:


Software Interrupts: In this interrupt, the programmer has to add the instruction to the program
to execute the interrupt. So they are the mnemonics to the microprocessor. It is caused either by
a special instruction in the instruction set or by an external condition in the processor itself.
Example: RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, and RST 7.
Hardware Interrupts: These interrupt signals are received by the microprocessor through its
pins, so they are generated externally.
Example: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.

2. Vectored and Non-Vectored Interrupts:


Vectored Interrupts: These interrupts have fixed vector address i.e. the starting address of
subroutine and these interrupt are known to the microprocessor and after execution of these
interrupts the program control is transferred to that address.
Example: TRAP, RST 7.5, RST 6.5, and RST 5.5.
Non-Vectored Interrupts: Here, the interrupt address is not known to the microprocessor so
the interrupt address needs to be sent externally by the device to perform interrupts.
Example: INTR.

3. Maskable and Non-Maskable Interrupts


Maskable Interrupts: Maskable Interrupts are the interrupts that can be blocked. Masking can
be done by software or hardware means. These interrupts can be disable by the microprocessor
by writing some instruction into the program.
Example: RST 7.5, RST 6.5, RST 5.5 and INTR.
Non-Maskable Interrupts: Non-maskable interrupts are interrupts that are always recognized.
It is not possible to disable the interrupt by writing any instruction into the program.
Example: TRAP

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