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DigitalElectronics (Theory)
90 all ti
ying throiug
le brfor
0Unte lo truy
stage, will not trigger the next fip flop since it goC omal stotcs.
With frutjl 3fr
from 0 to 1. The flip-flops change one at a tine in nodus for CountCIS Rtatrn :ta
rapid succession, and the signal propagates A comnon ACOunter With irD
sCqueDces is ten. counter
through the counter in a ripple fashion. Ripple a dec ade
COunters ate sonnetimes called
asynchronous SCqucDCeis Called
COunters. BCDRipple Counter
scqucne of ter1 statra
decinal counter follows a Suchanntrr
Conditions korcomplementing flip-flops
A
0 after the count of 9.
Count Seguen and returns to repretnt r3rt.
have at Jeast foOur flip-flops to reprentri
must decimal digjt is
decimal digit, since a bits. If BCD ;
Complement A,
Complement A, A,will go from 1to 0 and complement A, binary code with at least four shown inn the
by a states is as
0 Complement A,
Complenment A, will oo trom 1 to0 and conprem used, the sequence of This is sirnilar to
1
7-13.
state diagram of Fig. that the state after 1G:
Awill oo from 1 to 0 and A,
o o Complement A,
0 1 Complement A, Aill Qo from 1to O and cormplement A. binary counter, except 0000 (code for decirnai
for decimal digit 9) is
1
1 1 0 Complement A., (code
1 1 Complement A, A,will go from 1 to O and complement A
1
Awill oo from 1 to 0 and complement A digit 0).
Awill go from 1 to Oand complerment A4
ß o 0 and so on
HIGH
Abinarr counter with a reverse count is called a
binary down-counter. In a down-counter, the CLK.
binary count is decremented by 1 with every input
count pulse. The count of a 4-bit down-counter
starts from binary 15 and continues to binary
cOunts 14, 13. 12. 0 and then back to 15. Fig. 7-13
And continues to binary as a binary down-counter The circuit below is an implementation of a decade
if the outputs are taken for the complement counter. Once the counter counts to ten (1010).
terminals Q, of the flip-flops. If only the normal all the flip-flops are being cleared. Notice that only
outputsto flip-flops are available, the circuit must ?, andQ, are used to decode the count of ten. This
be modified slightiy as described below. is called partial decoding, as non of the other states
A list of the count sequence of a count-down (zero to nine) have both Q, and Q, HIGH at the
binary counter shows that the lowest-order bit same time.
must be complemented with every count pulse. Any
other bit in the sequence is complemented if its
previous lower-order it goes from 0 to 1. Therefore, (o000)(o001) (po1) (0011 (O100
the diagram of a binary down-counter looks the 1 2 3 4
same as in Fig.7-12, provided all flip-flops trigger
on the positive edge of the pulse. (the small circles
in the CP inputs must be absent). If negative 6
edge-triggered flip-flops are used, then the CP (100) i000) o1
input of each flip-flop must be connected to the Q, fo110) {0101)
output of the previous flip-flop. Then when Q goes
from 0to 1, Q, willgo from 1to 0 and complement Count
the next flip-flop as required. putses

Asynchronous Decade Counters:

The binary counters earlier discussed have two to
the power n states. But counters with states less 01 1 0 0 1
than this number are also possible. They are
designed to have the number of states in their o. 0 01 1 1 0
sequences, which are called truncated sequences.
0
These sequences are achieved by forcing the 0 0 0

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Excellence for Engineors Digital Electronics (Theory) 91

state Reduction and Assignment State Table

reduction of the number of
reffered to lip-flops
dhe
sequential circuit is
in a
as the state Next State Output
rduction, Prescnt State
Statereduction algorithms use to reduce the
state in state
number of diagram. Since mflip flop
produces2m states, a
state may (or
reduction in the number of
may not) result in a reduction in the
oumber of flip-flops,
an infinite number of
There are input result in a
that mav be applied to the circuit; each sequences
unique output sequence. Consider the
According to algorithm c and d are equivalent
sequence 01110111011110 starting from the
input
Reducing the state table
initial state a,

Next State Output

0/0 Present State
0/1 /0 X =0 X 1X -0 X =1

1
1/0 0/1 0/1 1/0
X/ Y
(6) Reduced state table
Input/Output
1/0
Present State Next State Output
Fig.: State diagram X -0 X =1 X =0 X =1
Complete sequence to be as follows: a b
b b 1
Present
: a a ba a d a b d c a b d c c
State
0/0
Input : 0 1 0 1 1 0 1 1 1 0 1 1 1 1 0 0/1
Output : 0 0 1 0 0 1 0 0 0 1 0 0 00 1
Next
: a b ab d a hb dc a b d cc a
State 0/1

An algorithm for the state reduction of a complete Reduced state diagram

specified state table Reduced state table with binary assignment
1WO state are said to be equivalent if, for each Put a = 0 and b =1
nember of the set of input, they give exactly the
ane output and sendthe circuit either tothe same
ate or to a equivalent state". Present State
Next State Output
X =0 X =1 X =0

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