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Assignment #1

The document outlines a series of engineering problems related to analog integrated circuit design, focusing on process variations, resistor mismatch, and amplifier characteristics. Each problem requires calculations for cut-off frequencies, resistor values, voltage variations, and gain specifications under varying conditions. The problems involve using given parameters and formulas to determine the impact of variations on circuit performance.

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2 views

Assignment #1

The document outlines a series of engineering problems related to analog integrated circuit design, focusing on process variations, resistor mismatch, and amplifier characteristics. Each problem requires calculations for cut-off frequencies, resistor values, voltage variations, and gain specifications under varying conditions. The problems involve using given parameters and formulas to determine the impact of variations on circuit performance.

Uploaded by

itzabhay
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment: #1

Due Date: May 26, 2022

PROBLEM 1. Process Variations

(a) In the low pass filter shown above, due to process variations, the resistor R has ±25%
variation and capacitor C has ±20% variation across corners. Taking three process corners
(MAX, MIN and TYP where TYP is 0%) each for R and C, find the cut-off frequencies of
the low pass filter for all possible corners. What is the percentage variation of the cut-off
frequency w.r.t its typical value. Identify the critical corners.
(b) If the temperature coefficient(k) of R is -1000ppm/◦ C, find the percentage variation of the
cut-off frequency across temperature (-40◦ C to 125◦ C) w.r.t to its value at 27◦ C assuming
ideal capacitor. Given: R(T) = R(T0 ) [1 + k (T-T0 )], where T0 = 27◦ C.

PROBLEM 2. Resistor Mismatch

(a) Assuming the above Opamp to be ideal, find R1 and R2 such that voltage gain, Av = Vo /Vi
= 2 and R1 +R2 = 20kΩ.
(b) The resistor value is calculated as R = Rsh (L/W), where L, W and Rsh are the length,
width and sheet resistance of the resistor, respectively. If R1 and R2 are of the same type
and the resistor mismatch is modelled using Gaussian distribution with σ value given,
choose W and L of R1 and R2 such that 3σ variation in Av is ≤1%. Given: Rsh =200 Ω/.
Minimum L and W that can be used are √Lmin =Wmin =500nm. Sigma variation of R w.r.t.
its mean is given by σ(∆R/R) = 0.03/ (WL), where W and L are in µm.

EE5320: Analog Integrated Circuit Design 1 May - Aug. 2022


PROBLEM 3. Given: Vref = 400mV; V1 =Vref /4; V2 =Vref /2; V3 =3Vref /4; R1 +R2 +R3 +R4 =40kΩ;
Minimum L and W of resistors, Lmin =Wmin =500nm; Sigma variation of R w.r.t. its mean is
√
given by σ(∆R/R) = 0.03/ (WL)

(a) For the resistive divider shown above, find the 3σ variation in the output voltages V1 , V2
and V3 due to resistor mismatch in terms of σ(∆R/R). Which voltage has the highest
variation? Choose W and L of the resistors such that for 3σ(Vi )≤1mV for all values of i.

(b) If the resistive divider is extended to say eight equal resistors, which voltage is expected
to have the highest variation?

PROBLEM 4. Consider a pseudo-differential amplifier as shown in the circuit below. Here,


RL = 50 Ω, CL = 50 fF, for MOSFETs in saturation gm/Id=10 /V and bias current IDS = 5 mA.
In layout, MOSFETs Mn1 and Mn2 are connected to load resistor RL using metal M3 and
outputs (Vop /Von ) are tapped using M4. Metal length and tapping locations are shown in the
figure. Using metal resistance as 10Ω/µm for M3 and metal capacitance as 10fF/µm for M4,
find the following: (Ignore resistance for M4 and capacitance for M3).
1.8V

RL RL
0.3µm

CL
M4 Von
1.3µm
0.7µm

1.5µm
M3

M3

0.5µm
M4 Vop
CL
Vcm + Vid/2 Mn1 Mn2

Vcm - Vid/2

(a) Output voltage Vop − Von for Vid =0.

(b) Differential voltage transfer function for the amplifier, H(s) = (Vop (s) − Von (s)) /Vid (s).

(c) DC gain, poles, and zeros in H(s).


PROBLEM 5. Consider a pseudo-differential amplifier as shown in the circuit below. MOS-
FETs Mn1 and Mn2 are biased in saturation with gm/Id=10 /V and bias current IDS = 5 mA.
Two different resistors with sheet resistance Rsh1 = 25 Ω/ and Rsh2 = 100 Ω/ are available in
a given process with linear temperature coefficient (TC1 ) +1000 ppm/◦C and -1000 ppm/◦C, re-
spectively. Minimum dimensions for resistors are Wmin = 400 nm and Lmin = 400 nm with vari-
ation limited to 20%. Sheet resistance variation is given by σ(∆Rsh1/Rsh1) = σ(∆Rsh2/Rsh2) = 0.25.
Neglect quadratic temperature coefficients for resistors and any temperature dependence for
MOSFETs.
1.8V

R1 R2

Von
Vop

Vcm + Vid/2 Mn1 Mn2

Vcm - Vid/2

(a) Find dimensions for resistors RL1 and RL2 such that differential DC gain of the amplifier
(Vop − Von ) /Vid is 10 V/V and gain is independent of temperature.

(b) Find standard deviation of variation in DC gain σ(∆ADC /ADC ) due to mismatch between
resistors.

PROBLEM 6. Consider block diagram of a comparator as shown in the figure below. Output
of the comparator, Q, is HIGH for Vin √ > Vref and LOW for Vin < Vref . Let R1 = 3R2 with
width W = 4 µm and σ(∆R/R) = 0.03/ W L for both resistors. Find the length of two resistors
such that ±3σ variation in reference voltage is limited to ±0.225 V.

1.8V

R1

Vin
Q
Vref
R2

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