Electrical Characteristics

8.8 Power Management Timing Diagrams

Figure 8-1. G3 w/RTC Loss to S4/S5 (With Deep S4/S5 Support) Timing Diagram

S o u rc e D e s tin a tio n S ig n a l N a m e
G3 D e e p S 4 /S 5 S 5 /S 4

B o a rd PCH V ccR TC t2 2 5
t2 0 0
B o a rd PCH RTCRST#
t2 0 0 a
B o a rd PCH V ccD S W 3_3
t2 0 0 b
B o a rd PCH DPW ROK
t2 0 0 c

PCH B o a rd SLP_SUS# t2 0 2

B o a rd PCH V ccS us
t2 0 1
B o a rd PCH RSMRST# t2 2 6

PCH B o a rd SUSCLK v a lid

t2 0 2 a
PCH B o a rd SLP_S5# O n ly fo r S 4 a fte r G 3 o r D e e p S x

Figure 8-2. G3 w/RTC Loss to S4/S5 (Without Deep S4/S5 Support) Timing Diagram

S o u rc e D e s tin a tio n S ig n a l N a m e
G3 S 5 /S 4

B o a rd PCH VccR TC t2 2 5
t2 0 0
B o a rd PCH RTCRST#
t2 0 0 a

B o a rd PCH V ccD S W 3_3

t2 0 0 b
B o a rd PCH DPW ROK
t2 0 0 c

PCH B o a rd S LP_S U S# t2 0 2

B o a rd PCH VccSus
t2 0 1

B o a rd PCH RSMRST# t2 2 6

PCH B o a rd S U SC LK v a lid
t2 0 2 a
PCH B o a rd S LP_S 5# O n ly fo r S 4 a fte r G 3

350 Datasheet
Electrical Characteristics

Figure 8-3. S5 to S0 Timing Diagram

Source Dest Signal Name

PCH Board SLP_S5#

PCH Board SLP_S4# t203

PCH Board SLP_S3# t204

Could already be high before this sequence begins (to support M3),
PCH Board SLP_A# but will never go high later than SLP_S3#

PCH Board SLP_LAN# Could already be high before this sequence begins (to support WOL),
but will never go high later than SLP_S3# or SLP_A#

Board PCH VccASW

t229

Board PCH Vcc

PROCPWRGD

Serial VID
CPU CPU VRM CPU SVID Load

V_vid
Board CPU VccCore_CPU

CPU VRM PCH SYS_PWROK

t205
Board PCH PWROK t206
t207
Board PCH APWROK APWROK may come up earlier
than PWROK, but no later

PCH CPU DRAMPWROK t230

25 MHz
Board PCH stable
Crystal Osc
PCH
PCH Board stable
Output Clocks
PCH CPU PROCPWRGD t208
t209

PCH Board SUS_STAT# t210

Assumes soft strap programmed to start at

PROCPWRGD - expected setting for SNB
CPU PCH THRMTRIP# ignored honored

PCH CPU/Board PLTRST# t211

_A s
E
NE ite
CK
SE DM N
DO wr
RE V DO
_
CP SK ET
T
SE

T_
ex ES
U_ U
P_
ST ing

Fl _R
RA
ain

U
CP
Tr
PCH CPU DMI

Datasheet 351
 Electrical Characteristics

Figure 8-4. S3/M3 to S0 Timing Diagram

Source Dest Signal Name

PCH Board SLP_S5#

PCH Board SLP_S4#

PCH Board SLP_S3#

PCH Board SLP_A#

PCH Board SLP_LAN#

Board PCH VccASW

Board PCH Vcc

PROCPWRGD

Serial VID
CPU CPU VRM CPU SVID Load
Note: V_PROC_IO may go to Vboot at
this time, but can also stay at 0V V_vid
(default)
Board CPU VccCore_CPU

CPU VRM PCH SYS_PWROK

t205
Board PCH PWROK t206

Board PCH APWROK

PCH CPU DRAMPWROK

25 MHz
Board PCH stable
Crystal Osc

PCH
PCH Board stable
Output Clocks
t208
PCH CPU PROCPWRGD t209

PCH Board SUS_STAT# t210

Assumes soft strap programmed to start at
CPUPWRGD - expected setting for SNB

CPU PCH THRMTRIP# ignored honored

PCH CPU/Board PLTRST# t211

s
ET M NE

N ite

K
C
ES VD O

r
_A
_D w
D

E
T_

O
T

S E
E

S
_S

U
ex E
S ing

PU K
Fl _R
AP

_R
n

U
TR
ai

P
Tr

C
PCH CPU DMI

Figure 8-5. S5/Moff - S5/M3 Timing Diagram

S o u rc e D est S ig n a l N a m e

PCH B o a rd S L P _S 5#

PCH B o a rd S L P _S 4#

PCH B o a rd S L P _S 3#

PCH B o a rd SLP_A#

PCH B o a rd SLP_LAN# C o uld a lre a d y be hig h be fo re th is se q ue n ce be g in s (to

sup p o rt W O L), b u t w ill n e ver g o h ig h la ter th a n S L P_A #

B o a rd PCH V ccA S W
t20 7
B o a rd PCH APW ROK
t2 12

PCH S P I F la sh SPI

C L_ R S T 1# t21 3
PCH C o n tro lle r L in k
(M o b ile O n ly)

352 Datasheet
Electrical Characteristics

Figure 8-6. S0 to S5 Timing Diagram

Source Dest Signal Name

DMI DMI Message L2/L3

PCIe* normal
PCH PCIe Ports operation
L2/L3
Devices

PCH Board SUS_STAT# t214

t215

PCH Board PLTRST# t217

PCH Board PROCPWRGD

CPU PCH THRMTRIP# honored ignored

t218
PCH
PCH Board valid
Output Clocks

PCH Board SLP_S3#

t219

PCH Board SLP_S4#

t220

PCH Board SLP_S5#

t221
t222
Board PCH PWROK
May drop before or after
SLP_S4/5# and DRAMPWRGD

Board PCH SYS_PWROK

PCH CPU DRAMPW ROK

PCH Controller Link CL_RST# ME-Related Signals

Going to M 3: stay high
Going to MOFF: go low
Only switch if going to MOFF
Source of Live value from Value from MAC
PCH GbE PHY LANPHYPC value GbE MAC latched in SUS well

If appropriate, save MAC

PCH Board SLP_A# PMCSR context here

Board PCH APWROK

PCH Board SLP_LAN# SLP_LAN# could stay

high for M 3 or WOL

Datasheet 353
 Electrical Characteristics

Figure 8-7. S4/S5 to Deep S4/S5 to G3 w/ RTC Loss Timing Diagram

S o u rce D e s tin a t io n S ig n a l N a m e

S 4 /S 5 D e e p S 4 /S 5 G3

PCH B o a rd (E C ) SUSW ARN# u n d r iv e n

B o a rd (E C ) PCH SUSACK# u n d r iv e n

PCH B o a rd SLP_SU S #
SLP_S3# /
PCH B o a rd SLP_S4# / u n d r iv e n
SLP_A#

PCH B o a rd SLP_S5# u n d r iv e n
S L P _ S 5 # d r o p s h e r e if
n o t a lr e a d y a s s e r te d

B o a rd PCH RSMRST#
t2 3 5
B o a rd PCH V ccS us

B o a rd PCH DPW ROK

t2 3 4
B o a rd PCH VccD SW

B o a rd PCH RTCRST#
t2 3 6
B o a rd PCH V ccR TC

Figure 8-8. DRAMPWROK Timing Diagram

S o u rc e D e s tin a tio n S ig n a l N a m e

PCH B o a rd S LP_S4#

B o a rd PCH PW ROK

PCH CPU DRAM PW ROK t22 3 t2 24

354 Datasheet