TECHNICAL FEATURE

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REVIEWED

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PASSIVE MINIATURIZATION:
SI INTEGRATED PASSIVE
DEVICES FOR RF AND
MICROWAVE APPLICATIONS
With well-developed, low cost RF passive manufacturing technology (thick oxide
Si substrate and copper/benzocyclobutene (Cu/BCB) multi-layer passive process
technologies), various kinds of high performance RF integrated passive devices
(IPD) have been fabricated on a 6" Si wafer for RF and microwave applications,
and have achieved dramatic cost and size reductions. The fabricated devices are a
low pass/high pass antenna diplexer, a low pass filter with harmonic resonance, a
bandpass type diplexer for a VCO loop and a 2.4 GHz wireless LAN balun. To
the authors’ knowledge, they offer the smallest size and highest performance for
devices of this type built on silicon. The size of the wafer-level, packaged, RF IPD
is 1 to 1.5 mm2. This RF passive integration technique will permit the 40 percent
functional size reduction for handheld phones and wireless terminals that has
been pursued until now.

W
hen considering mobile electronic tion of mobile terminals. There has been con-
products, smaller is usually better. siderable research focused on low tempera-
Most portable devices often have ture and low cost co-fired ceramic (LTCC)
particularly stringent miniaturization require- technology, 2 but the research on thin film
ments in order to meet market place expecta- multi-chip module with deposited substrate
tions. The average passive device count in cel- (MCM-D) technology is not active. It is main-
lular phones has not dramatically dropped in ly focused on glass carrier substrates,3 not on
recent years1 and current handset designs are Si substrates because of many limiting factors
far from eliminating passive components. The such as substrate conduction.
size improvements, to date, have come from A thick oxide technology has been devel-
both smaller passive components and more ef- oped to transform the Si wafer in a new RF
ficient packaging of the components on the
boards. The market demands, such as ultra- DONG-WOOK KIM, IN-HO JEONG
miniaturization and pricing pressure, make AND JONG-SOO LEE
the integration of passive components on Telephus Inc.
wafer to be the solution for the next genera- Taejeon, South Korea
 TECHNICAL FEATURE
substrate and synergistically combine can be the optimal choice for low cost mA for 168 hours. RF components for
it with a high quality passive Cu/BCB and high performance RF passive in- wireless applications are typically re-
process.4,5 Device examples and mea- tegration. For small-size passive de- quired to have an RF CW power han-
sured results for various RF IPDs are vices, the area occupied by an induc- dling capability of 3 W. The input and
provided to demonstrate their superi- tor should be reduced, while main- output matching circuits fabricated us-
or performance and attractive size re- taining satisfactory RF performance. ing the Cu process endured 5 W of RF
duction. To reduce the size of the To achieve this goal, a line width of power for 168 hours without change,
passive component to the maximum, 10 µm and a line spacing of 10 µm are
PbSn eutectic solder balls are used to mostly used for functional passive de- GLASS SiO2
attach them directly on the board. vices on Si. Figure 2 shows the in- 0

INSERTION LOSS (dB/mm)

ductance value as a function of the −0.025
PASSIVE INTEGRATION number of turns and inductor size.
−0.050
ON SI SUBSTRATE Most of the planar spiral inductors
Silicon is the most stable and reli- occupy less than 0.5 × 0.5 mm area −0.075
able semiconductor and has been and are mostly concentrated in the −0.100
used in many electronic applications. 0.09 to 0.16 mm2 region. They are −0.125
Unlike other semi-insulating sub- much smaller than any other induc-
−0.150
strates, silicon has had to rely on the tors implemented on PCB, LTCC or 1 2 3 4 5 6 7
properties of silicon dioxide for isola- glass substrates. FREQUENCY (GHz)
tion. But a thin silicon dioxide layer ▲ Fig. 1 Insertion loss of coplanar
cannot effectively isolate passive de- SMALL-SIZE transmission lines on 25 µm thick oxide Si
vices on Si substrates because of ca- AND HIGH POWER RF substrate and high quality glass substrate.
pacitive effects. The signal loss is also INTEGRATED PASSIVE DEVICES
40
high because of the finite conductivi- The on-chip inductor, a major tech- 8.5 TURNS
ty of the silicon substrate. These ef- nological challenge, is fabricated on a 35
fects make it difficult to use Si tech- thick oxide Si substrate using a Cu
30
nology for RF and microwave appli- metal system with 11 µm plated metal 7.5
cations. In addition to the substrate thickness and BCB interlayer material. 25

L (nH)
loss, the conductor loss in the metals, The fabricated inductors have a spac- 20
6.5
due to the low conductivity of materi- ing of 10 µm between turns and sever- 5.5
als such as aluminum, limits the ap- al different metal widths (10, 20, 30, 15
plication of silicon to less than a few 40, 50 µm) and show the maximum 10
4.5
hundreds of megahertz. quality factor Q for the range of 40 to 3.5
A thick silicon dioxide layer of 25 60 µm, depending on the geometrical 5
2.5
µ m on Si reduces the transmission parameters and for inductances from 0
1.5
0 4 16 32 64
losses by confining most of the elec- 0.3 to 35.0 nH. Figure 3 shows a
SIZE (×104 µm2)
tromagnetic field in the low loss di- cross-sectional view of the bonding pad
electric layer beneath the conductors structure composed of Ti/Cu – Ni/Au ▲ Fig. 2 Inductance as a function of size
and not in the conducting silicon re- and BCB passivation. The Ni (6 µm) and number of turns.
gion. Also, the use of an 11 µm thick and Au (0.5 µm) layers are electroplat-
Cu metal layer and low dielectric ed and used for the bonding of Au
constant BCB material makes it pos- wire. They are not needed when the
sible to implement low loss transmis- chip is bonded with solder balls during
sion lines over a broad frequency packaging. The spiral inductor with
range. For example, a 50 Ω coplanar thick Cu metal has much more DC
transmission line of 50 µm width and current and RF power capabilities
15 µm gap on Si showed a total inser- than conventional Al- or Au-based in-
tion loss of only 0.04 to 0.07 dB/mm ductors, even though the underlying
at 5 GHz. This RF loss is very compa- interconnection between inner and ▲ Fig. 3 Cross-sectional view
rable to that of a high quality glass outer sides of the inductor is relatively of a bonding pad.
substrate in the low GHz region, thin. The DC current test results for a
2.0
though the latter shows slightly high- spiral inductor with a 10 µm line width 1.8
VOLTAGE (V)

er performance in the frequency re- and line spacing is shown in Figure 4. 1.6
1.4
gion above 10 GHz. However, the Every current step was sustained for 1.2
glass substrate is very fragile and can 15 minutes and the current was in- 1.0
SLOPE
0.8
break easily during the process. Fig- creased to 640 mA. According to the 0.6 DEVIATION
ure 1 shows a comparison of the in- data, some deviation was observed 0.4 START
0.2
sertion losses of coplanar waveguide around 550 mA and the underlying 0
(CPW) lines built on a thick oxide Si metal started to burn at more than 600 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
substrate and a high quality glass sub- mA. No physical or performance CURRENT (A)
strate. The results show that the spe- change was noticed after the inductor ▲ Fig. 4 DC current rating test
cialized Si substrate and Cu process was submitted to a DC current of 500 of the spiral inductor.
 TECHNICAL FEATURE
which means the developed small-size While achieving low insertion losses, any excessive loss. Figure 6 shows a
Si RF IPD can be considered to have enough harmonic attenuation was ob- fabricated GSM/DCS diplexer and its
greater power handling capability than tained by modifying the Chebyshev measured performance. To achieve
required by commercial specifications filter and the elliptic filter topologies the high band-rejection level and har-
for handheld terminals. to resonate at harmonic frequencies. monic attenuation level, four induc-
In the following paragraphs, high Figure 5 shows a 900 MHz low pass tors are used to obtain series and par-
quality Si integrated passive devices filter for GSM applications and its allel resonances. The insertion losses
with high volumetric efficiency will measured results. As shown, the in- of the wafer-level packaged diplexer
be introduced and their measured sertion loss is typically 0.45 dB and, are 0.45 dB at 900 MHz and 0.6 dB
performance provided. All the pas- in the case of a wafer-level packaged at 1800 MHz. The band-rejection
sive devices are wafer-level bonded to device, the second- and third-har- levels are greater than 25 dBc at 900
the boards, using eutectic solder balls monic attenuation levels are greater MHz and 30 dBc at 1800 MHz. The
for direct attachment, or are finished than 25 dBc. The size of the filter is third-harmonic attenuation is also
with Ni/Au plated pads for wire bond 1.0 mm 2 and it can be directly at- more than 25 dBc. The size of the
attachment on multi-chip modules. tached on the PC board by a conven- wafer diplexer is 1.5 mm 2 , corre-
Typically, wire bondable passive de- tional solder-reflow process. This ul- sponding to a 60 percent reduction
vices are 20 to 30 percent smaller tra-miniaturization is sure to be an over a conventional device size.
than solder ball bonded devices. important step for a 40 percent size
reduction in the functional integra- BANDPASS TYPE LUMPED
LUMPED L-C TYPE tion of mobile phones. L-C DIPLEXER FOR VCO LOOP
LOW PASS FILTER FOR PAM APPLICATIONS
OR FEM APPLICATIONS LOW PASS/HIGH PASS LUMPED This bandpass type diplexer, pro-
In modern communications sys- L-C DIPLEXER FOR ASM viding bandpass filtering and imped-
tems, low pass filters are used to pass OR FEM APPLICATIONS ance matching, is designed to operate
the wanted signal and eliminate or at- The diplexer handles two different as an EGSM/PCS/DCS transmitter
tenuate harmonics, mainly at the out- carrier frequencies on the same sig- VCO sampling diplexer. It can be used
put stage of the power amplifier. nal path. It consists of a combination for a two-port, low power transmitter
With conventional low pass filter cir- of low pass and high pass filters or VCO feedback to the synthesizer in
cuits, it is not easy to meet the inser- two bandpass filters. The bandpass GSM handsets. The device circuit
tion loss in the pass-band and the at- diplexer shows good attenuation consists of bandpass filter channels
tenuation levels at the second- and characteristics but is very lossy, so it where suppression of second- and
third-harmonic frequencies required cannot be used in the front end of a third-harmonic signals is required.
by strict commercial specifications. mobile phone that does not allow for Two parallel resonators are used in se-
ries connection and shunt connection
in each channel. Figure 7 shows the
fabricated chip and its test results. The
nominal values of the pass-band inser-
tion loss are 1.2 dB at 880 to 915 MHz

(a)

0
(a) GSM DCS (a)
−5
 S31 (dB)  S21 (dB)

0 −10
0
−5 −15 −5
 S31 (dB)  S21 (dB)

GSM DCS
 S11 (dB)  S21 (dB)

−20 −10
−10
−15
−15 −25
−20
−20 −30 −25
−35 −30
−25
−40 −35
−30 0 1 2 3 4 −40
−35 FREQUENCY (GHz) −45
(b) −50
−40
0 1 2 3 4 5 6 7 0 1 2 3 4
FREQUENCY (GHz) FREQUENCY (GHz)
(b) (b)

▲ Fig. 5 Wafer-level packaged low pass ▲ Fig. 6 GSM/DCS diplexer (a) and its ▲ Fig. 7 Bandpass type EGSM/PCS/DCS
filter (a) and its measured results (b). measured results (b). diplexer (a) and its measured results (b).
 TECHNICAL FEATURE
gy (SMT) techniques and a solder-re- bump bonding, while maintaining their
flow process. Solder balls with a diam- high power handling capability and RF
eter of 130 or 300 µm can be used, de- performance. This RF passive integra-
pending on the requirements. The for- tion on Si will provide a step forward
mer is obtained during the plating for the next generation of mobile tech-
process and the latter is typically nology and will be cost-effective. It is
achieved with the ball placement an optimal solution for handheld wire-
process. The fabricated passive de- less applications that require stringent
(a)
vices can be RF-tested using a mem- cost and size reductions. ■
brane probe card. According to the ex-
AMPLITUDE_IMBALANCE (dB) periments performed, the solder balls References
PHASE_IMBALANCE (°)
INSERTION LOSS (dB)

4 1. D. Carey, “Miniaturization in Electronics:

0.8 are not damaged too much and the
The Passive-aggressive View,” Passive
0.4 2 RF measurement results are accurate Component Industry, September/October
0
and reproducible if the probe contact 2001, pp. 28–30.
0
is kept to less than 20 times for the 2. J. Muller, “High Quality RF Inductors in
−0.4 −2 same device. When less than 20 con- LTCC,” Proceedings of the ISHN Interna-
−4 tacts have been made, the measure- tional Symposium on Microelectronics,
−0.8
Minneapolis, MN 1996.
2.0 2.2 2.4 2.6 2.8 3.0 ment error is less than 0.05 dB and 3. W. de Raedt, E. Beyne and R. Mertens,
FREQUENCY (GHz) the standard deviation is 0.016 dB. “Thin Film Embedded Passives for Mi-
(b) crowave and Millimeter-wave Applica-
CONCLUSION tions,” 7th Pan Pacific Microelectronic
▲ Fig. 8 Balun for 2.4 GHz wireless LAN
Small-size RF integrated passive Symposium, Hawaii, 2002, pp. 343–349.
applications (a) and its measured results (b). 4. D.W. Kim, I.H. Jeong, C.M. Nam, T.O.
devices are fabricated on 25 µm thick Kong, H.S. Sung, K.J. Kim, I.D. Yoon, J.S.
and 2.2 dB at 1710 to 1910 MHz. The oxide Si substrates, using a thick Cu Lee and Y.S. Kwon, “Ultra High Q Induc-
attenuation levels of the stop-band are and low dielectric constant BCB inter- tor and RF Integrated Passive Devices on
more than 30 dBc at 1800 MHz and layer processes. The devices show high Thick Oxide Si Substrate,” 7th Pan Pacific
Microelectronics Symposium, Hawaii,
20 dBc at 3600 MHz. The return loss RF power handling capability (more 2002, pp. 350–355.
is greater than 15 dB. The packaged than 3 W) and low loss. Solder bumps 5. D.W. Kim, I.H. Jeong, H.S. Sung, J.S. Lee,
device size is 1.5 mm2. for passive device bonding are used C.M. Nam and Y.S. Kwon, “High Perfor-
and to the authors’ knowledge, the fab- mance RF Passive Integration on Si Smart
LUMPED L-C BALUN FOR Substrate,” IEEE International Microwave
ricated wafer-level packaging circuits Symposium, Seattle, WA 2002.
WIRELESS LAN APPLICATIONS shown here are the smallest ever re-
A balun converts a balanced signal ported, compared to conventional ce- Dong-Wook Kim
to an unbalanced one or vice-versa. received his BS degree
ramic passive devices. The low pass fil- in electronics
The photograph and the measured ter shows an insertion loss of 0.45 dB engineering from
performance of a fabricated 2.4 GHz and the harmonic attenuation level is HanYang University,
balun are shown in Figure 8. The in- greater than 25 dBc. The packaged de- Seoul, South Korea, in
sertion loss of 0.5 dB is obtained from vice size is 1.0 mm 2 . The antenna 1990, and his MS and
PhD degrees in
back-to-back measurement of the diplexer for GSM/DCS applications electrical engineering
baluns. The phase imbalance is mea- shows insertion losses of 0.45 and 0.60 from the Korea
sured to be less than 3.5° and the am- dB at 900 MHz and 1800 MHz, re- Advanced Institute of
plitude imbalance is less than 0.5 dB. spectively. The band-rejection levels Science and
These results are superior to those Technology (KAIST), Taejeon, South Korea, in
are more than 25 dBc at 900 MHz and 1992 and 1996, respectively. From 1991 to
from their ceramic counterparts, 30 dBc at 1800 MHz. The insertion 2000, he worked as a member of the technical
which show typical phase imbalance losses of the diplexer for VCO applica- staff at the LG Electronics Institute of
of 10° and amplitude imbalance of tions are 1.2 dB at 900 MHz and 2.2 Technology, Seoul, South Korea, where he was
2.0 dB maximum. The smaller size, dB at 1800 MHz, in spite of the band- involved in developing microwave and
millimeter-wave circuits and modules. Since
1.5 mm2, corresponding to a reduc- pass topology. A balun is also fabricat- 2000, he has been a principal engineer and
tion of 60 percent over the conven- ed for 2.4 GHz wireless LAN applica- general manager of Telephus Inc., where he is
tional device, is another advantage. tions and has a loss of 0.5 dB, a phase currently leading the product development
imbalance less than 3.5° and an ampli- division to develop Si integrated passive
DISCUSSION devices and multi-chip modules for microwave
tude imbalance less than 0.5 dB. The and millimeter-wave applications. His areas of
To make RF integrated passive de- size of the above three passive device interest are low cost passive integration
vices small and inexpensive, no pack- circuits is 1.5 mm2 and shows a dra- techonology, RF and millimeter-wave
aging was used, except eutectic solder matic reduction compared to conven- integrated circuit design, multi-chip module
balls for wafer-level bonding. The de- tional approaches. The “cheap and based on low cost passive integration process
and system-in-package. Dr. Kim is a member of
vice with eutectic solder balls can be small” passive devices are achieved by both IEEE and IMAPS (International
directly attached to the board, using using passive integration technology on Microelectronics and Packaging Society).
conventional surface-mount technolo- Si substrates and wafer-level solder
 TECHNICAL FEATURE
In-Ho Jeong received Jong-Soo Lee received
his MSEE and PhD his BSEE, MSEE and
degrees from the Korea PhD degrees in
Advanced Institute of electrical engineering
Science and from the Korea
Technology (KAIST), Advanced Institute of
Taejeon, South Korea, Science and
in 1997 and 2001, Technology (KAIST) in
respectively. He 1994, 1996 and 2001,
currently works for respectively. In 2000,
Telephus Inc. as a he was a research
senior R&D engineer. engineer at the
His research interests include RF MEMS DaimlerChrysler Research Center, Ulm,
technology and integrated passive devices for Germany, working with GaN power
wireless communications. amplifiers. He joined Telephus Inc. that same
year. His work includes passive device
modeling for MCM-D technology, design of
passive circuits, and the design of RF modules
integrated with passive circuits, SAW-based
filters and RFICs. His major interests are in
active devices such as Si BJT or BiCMOS and
GaAs (InP) MESFET, HEMT or HBT to design
RF subsystems or modules such as transceiver
modules including diplexers, LNAs, filters and
mixers.