MODULE 3

5 What are the issues associated with NP domino logic (3) [June 2022]
Scheme: Drawbacks of NP domino logic 3 marks
• Charge sharing problem.
• Charge leakage problem.
• P-tree blocks are slower than the n-tree modules, due to lower current drive of the pMOS
transistors in the logic network
6 Compare DRAM and SRAM cells (3) [June 2022][Jan 2024]
Scheme: Any 3 points (3marks)

5 What is memory? Distinguish between volatile and non-volatile memory (3) [ May 2023]
Scheme: Memory definition (1 mark) Types with example (2 marks)
Memory stores information that the CPU uses for processing and completing instructions. A
memory unit stores binary information in group of bits called words.
5 Draw the circuit of a 3 input NOR gate using Dynamic CMOS logic. (3) [June 2023]
Scheme: Diagram-3 marks

Substitute the PDN block in the above figure with the following diagram

6 Explain the working of a one transistor DRAM memory cell. (3) [June 2023]
Scheme: Diagram-2 marks, Explain-1 mark
Or
6 Draw the circuit of one transistor DRAM cell (3) [ May 2023]
Scheme: Circuit diagram (3 marks)
Write:
• Data to be written placed at BL.
• WL is asserted high to turn transistor ON.
• Depending on data, storage capacitor either charges or discharges.
Read:
• BL must be pre-charged to VDD/2.
• Assert WL high to turn access transistor ON.
• During read operation, there is a flow of charges between the storage capacitor Cs and the
column capacitor CBL.
• As a result the column capacitor voltage either increases (read ‘1’) or decreases (read’0’)
slightly. This difference can then be amplified by the sense amplifier.
• Read operation destroys the charge stored on the storage capacitor Cs (“destructive read out”).
• Therefore, the data must be restored (refreshed) each time the read operation is performed.
Essays:
15 a) Design three transistor and one transistor DRAM cells and explain the working of each
type (10) [June 2022]
Scheme: Design of Three Transistor DRAM with working (5 marks) Design of One Transistor
DRAM with working (5 marks)

one transistor DRAM cell – Refer above answer

Three transistor DRAM cell:

The storage transistor M2 is turned OFF or ON depending on the charge stored in storage
capacitor C1 and the pass transistors M1 and M3 act as access switches for data WRITE and
READ operations.
Write “1” operation:
• Pre-charge C2 and C3. (Charged to logic ”1” level).
• For the write “1” operation, the inverse data input (DATA’) is at logic “0”. Thus the data write
transistor DATA’ is turned OFF.
• Set WS = 1. Then M1 turns ON, i.e., the charge on C2 is shared with C1.
• Since the capacitance C2 is very large compared to C1, the storage node capacitance C1
attains approximately same logic-high level as C2.
• After write operation (WS = 0), M1 turns OFF. Since C1 is charged up to logic “1”, M2 turns
ON.

Read “1” operation:

• Pre-charge C2 and C3. (Charged to logic ”1” level).
• Set RS = 1. Then M3 turns ON.
• As C1 is having logic “1”, M2 is also ON.
• Thus C3 discharges through M2 and M3 and the falling column voltage is interpreted by the
“data read” circuitry as a stored logic “1”.
• Here the charge stored in C1 is not disturbed.
Write “0” operation:
• Pre-charge C2 and C3. (Charged to logic ”1” level).
• For the write “0” operation, the inverse data input (DATA’) is at logic “1”. Thus the data write
transistor DATA’ is turned ON.
• Set WS = 1. Then M1 turns ON and voltage level on C1 and C2 are pulled to logic “0”,
through M1 and DATA’ transistor.
• After write operation (WS = 0), M1 turns OFF. Since C1 is discharged up to logic “0”, M2
turns OFF.

Read “0” operation:

• Pre-charge C2 and C3. (Charged to logic ”1” level).
• Set RS = 1. Then M3 turns ON.
• As C1 is having logic “0”, M2 is OFF.
• Thus C3 will not discharge through M2 and M3 as there is no conducting path and the logic-
high level on the column voltage is interpreted by the “data read” circuitry as a stored logic “0”
bit.
• Here the charge stored in C1 is not disturbed.

b) Explain the basic principle of operation of dynamic logic (4) [June 2022]
Scheme: Explanation(2marks) Figure (2marks)
Or
b) Describe the principle of operation of Dynamic logic with neat diagram (6) [ May 2023]
Scheme: Explanation (4 marks) Figure (2marks)
Or
Explain in detail the precharge and evaluate logic in dynamic logic design (7) [Jan 2024]

In dynamic logic, a clock signal is used to evaluate combinational logic.

With the addition of clock input, it uses a sequence of pre-charge and conditional evaluation
phases. When CLK = 0, the output node “Out” is precharged to VDD by the PMOS transistor
Mp. During that time, the evaluate NMOS transistor Me is off, so that the pull-down path is
disabled. For CLK = 1, the precharge transistor Mp is off, and the evaluation transistor Me is
turned on. The output is conditionally discharged based on the input values and the pull-down
topology. If the inputs are such that the PDN conducts, then a low resistance path exists
between “Out” and GND and the output is discharged to GND. The final discharged output
level depends on the time span of the evaluation phase. Otherwise, VOUT remains at VDD.
If the PDN is turned off, the pre-charge value remains stored on the output capacitance CL,
which is a combination of junction capacitances, the wiring capacitance, and the input
capacitance of the fan-out gates. During evaluation phase, the only possible path between the
output node and a supply rail is to GND. Once Out is discharged, it cannot be charged again
until the next pre-charge operation. The inputs of the gate can thus make at most one
transition during evaluation. The output can be in the high impedance state during the
evaluation period if the pull-down network is turned off.
16a) Design a 4x4 NAND based MOS ROM Cell Array and explain its operation (10) [June
2022]
Scheme: Design (6 marks) Explanation (4 marks)

Each bit line consists of a depletion-load NAND gate, driven by some of the row
signals, i.e., the word lines. It uses depletion load NMOS as pull up transistor (always ON).
In normal operation, all word lines are held at the logic HIGH voltage (ON, WL=1) level except
for the selected line, which is pulled down to logic LOW level (OFF, WL=0).
• If a transistor exists at the cross point of a column and the selected row, that transistor is
turned off and column voltage is pulled HIGH by the load device.
• On the other hand, if no transistor exists (shorted) at that particular cross point, the column
voltage is pulled LOW by the other NMOS transistor in the multi-NAND structure.
• Thus, a logic “1”-bit is stored by the presence of a transistor that can be deactivated, while a
logic “0”-bit is stored by a shorted or normally ON transistor at the cross-point.
b) Compare the performance of dynamic and domino logic(4) [June 2022]
Scheme: Comparison any 4 points (4 marks)

15 a) Design a six transistor SRAM cell. Explain its operation (8) [ May 2023]
Scheme: Six Transistor SRAM circuit (4 marks) explanation (4 marks)
Or
16 a) With circuit diagram explain the read operation in a 6 transistor static RAM memory. (10)
[June 2023]
Scheme: Figures-5 marks, Explain- 5 marks
Or
Draw circuit diagram and explain the operation of 6 transistor SRAM cell. Explain READ and
WRITE operation.

A low power SRAM cell maybe designed by using cross coupled CMOS inverters. The
memory cell consists of simple CMOS inverters(M1,M2 & M3,M4) connected back to back,
and two access transistors (M5 and M6). The access transistors are turned ON whenever a
word line is activated for read or write operation, connecting the cell to the complementary bit
line columns.
READ operation: Assume that Q= logic ‘1’ ; Q’ = ‘0’.
• Both bit lines are pre-charged to VDD.
• The transistors M2 and M3 are turned OFF, while the transistors M1 and M4 operate in linear
mode.
• Read cycle is started by asserting WL enabling access transistor M5 and M6.
• During READ operation, value stored in Q and Q’ are transferred to the bit line by leaving
BL in its pre-charged value and by discharging BL’ through M5 and M1.

WRITE operation:

Assume that Q =logic’1’ ; Q’ = logic ’0’

• A ‘0’ is written in the cell by setting BL = 0 or BL’ = 1.
• The transistors M2 and M3 are turned OFF, while the transistors M1 and M4 operate in linear
mode.
• Write cycle is started by asserting WL (WL=1) enabling access transistor M5 and M6.
• During WRITE operation, value stored in BL is transferred to Q by discharging it through
M4 and M6.
Then Q’ = 1.
• Q = 0 and Q’ = 1
b) Explain the basic principle of operation of Domino logic. What are its advantages (6) [ May
2023]
Scheme: Explanation(2marks) Figure (2marks) advantages (2marks)
Or
Explain Domino Logic(3) [Jan 2024]

A Domino logic module consists of an n-type dynamic logic block followed by a static inverter.
The addition of the inverter allows us to operate a number of such structures in cascade.
During pre-charge, the output of the n type dynamic gate is charged up to VDD, and the output
of the inverter is set to 0.
During evaluation, the dynamic gate conditionally discharges, and the output of the inverter
makes a conditional transition from 0 to 1.
Advantages:
• Reduced number of transistors required compared to static CMOS logic.
• Lower power consumption.
• Reduced chip area.
• Higher speed of operation (only rising edge delay)
• No short-circuit power dissipation.
• No glitching power dissipation
• The introduction of static inverter has the additional advantage that the fan-out of the gate is
driven by a static inverter with low impedance output, which increases noise immunity.
• The buffer reduces the capacitance of the dynamic output node by separating internal and
load capacitances.

16 a) Design a 4x4 NOR based MOS ROM Cell array and explain its operation (8) [ May
2023][JAN 2024]
Scheme: Design (4 marks) Explanation (4 marks)

Each column consists of pseudo-NMOS NOR gate driven by word lines (row signals).
The gates of all PMOS are grounded to keep it ON. Only one word line is activated (selected)
at a time by raising its voltage to VDD, while all other rows are held at a low voltage level. If
an active transistor exists at the cross point of a column and the selected row, the column
voltage is pulled down to the logic low level by that transistor. If no active transistor exists at
the cross point, the column voltage is pulled high by the PMOS load device. Thus, a logic “1”
–bit is stored as the absence of an active transistor, while a logic “0”-bit is stored as the presence
of an active transistor at the cross-point.
Disadvantage: Large part of cell is devoted to BL and ground connection
b) Explain the implementation of 4x4 NOR based ROM array to store the following data in
word lines - 1 0 0 0, 0 1 1 0, 0 1 0 0, 0 0 1 0. (7) [June 2023]
Scheme: Figure-4 marks, Explain-3 marks
NOTE: For this question you have to modify the diagram accordingly. Explanation is same.
15a) Discuss the signal degradation issue that occurs while we cascade dynamic logic gates.
How can we overcome it in domino logic? (7) [June 2023]
Scheme: Problem in cascading-4 marks
How to overcome in domino logic-3 marks

For practical multi-stage applications, however, the dynamic CMOS gate presents a significant
problem. The output of the first dynamic CMOS stage drives one of the inputs of the second
dynamic CMOS stage, which is assumed to be a two-input NAND gate for simplicity. – During
pre-charge, both Vout1 and Vout2 are pre-charged to Vdd. When clk goes high to begin
evaluate, all inputs at stage 1 require some finite time to resolve, but during this time charge
may erroneously be discharged from Vout2. e.g. assume that eventually the 1st stage NMOS
logic tree conducts and fully discharges Vout1, but since all the inputs to the N-tree all not
immediately resolved, it takes some time for the N-tree to finally discharge Vout1 to GND. If,
during this time delay, the 2nd stage has the input condition shown with bottom NMOS
transistor gate at a logic 1, then Vout2 will start to fall and discharge its load capacitance until
Vout1 finally evaluates and turns off the top series NMOS transistor in stage. This example
illustrates that dynamic CMOS logic stages driven by the same clock signal cannot be cascaded
directly.
If we build a system by cascading domino CMOS logic gates as shown in Fig. all input
transistors in subsequent logic blocks will be turned off during the precharge phase, since all
buffer outputs are equal to 0. During the evaluation phase, each buffer output can make at most
one transition (from 0 to 1), and thus each input of all subsequent logic stages can also make
at most one (0 to 1) transition. Thus this overcomes the cascading problem in the dynamic
logic.

b) Write a note on NP domino logic.(4) [June 2023]

Scheme: Explain -4 marks
In NP Domino logic -Cascaded NMOS & PMOS Dynamic logic circuits are used. The
precharge-and-evaluate timing of nMOS logic stages is accomplished by the clock signal ɸ,
whereas the pMOS logic stages are controlled by the inverted clock signal.
The operation of the NORA CMOS circuit is as follows:
● When the clock signal is low (ɸ=0 ), the output nodes of nMOS logic blocks are precharged
to VDD through the pMOS precharge transistors, whereas the output nodes of pMOS logic
blocks are predischarged to 0 V through the nMOS discharge transistors.
• When the clock signal makes a low-to-high transition(ɸ =1), all cascaded nMOS and pMOS
logic stages evaluate one after the other. All Nlogic tree logically evaluates to ground while P-
logic tree logically evaluates to Vdd.
• Inverter outputs can be used to feed other N-blocks from N-blocks, or to feed other P blocks
from P-blocks.
16a) Design a 4x4 OR based ROM Array and explain its operation (7) [Jan 2024]

WL is used to enable rows and output is read from BL

Default values of BL and WL = 0 (low)
NMOS is used to design the cell and is connected to VDD .
Cell with transistor –data will be one, else data is zero
Whenever there is a connection between BL and WL , the logic stored will be high.
According to OR logic, whenever any logic is high, output will be high.
The supply voltage is shared between the word lines. This reduces the number of supply lines
and thereby area. This requires mirroring of transistors of alternate word lines. Transistor drain
will be connected to supply voltage and source to BL. Pull down loads use NMOS transistors
which will be always ON. So BL is low.ie. Pulling down BL to Gnd. Let only WL(0) =1, So
transistor in that row will turn on. So that BL is connected to Vdd and becomes high. Transistor
presence indicates stored 1 and absence means stored 0.