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Week 3

Latch-up is a short circuit phenomenon in ICs caused by parasitic transistors, leading to high current and potential damage. Prevention techniques include adding high resistance to limit current and using insulating oxide layers to disrupt the parasitic structure. The document also outlines the IC design flow and scaling factors for MOS circuits, emphasizing the importance of maintaining electric field consistency during scaling.

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ahmed shafeey
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6 views

Week 3

Latch-up is a short circuit phenomenon in ICs caused by parasitic transistors, leading to high current and potential damage. Prevention techniques include adding high resistance to limit current and using insulating oxide layers to disrupt the parasitic structure. The document also outlines the IC design flow and scaling factors for MOS circuits, emphasizing the importance of maintaining electric field consistency during scaling.

Uploaded by

ahmed shafeey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Advanced Electronics

Week 3

DR. Ahmed EL-Shafeey


Latch-Up and its Prevention
What is Latchup:
• Latchup refers to short circuit formed between power and ground rails in an IC
leading to high current and damage to the IC.
• Speaking about CMOS transistors, latch up is the phenomenon of low impedance
path between power rail and ground rail due to interaction between parasitic pnp
and npn transistors.
• These form a +ve feedback loop, short circuit the power rail and ground rail, which
eventually causes excessive current, and can even permanently damage the device.
Latch-Up and its Prevention
Latchup formation:

• Shown alongside is a CMOS transistor consisting of an NMOS and a PMOS device.


• Q1 and Q2 are parasitic transistor elements residing inside it.
• Q1 is double emitter pnp transistor whose base is formed by n well substrate of
PMOS, two emitters are formed by source and drain terminal of PMOS and
collector is formed by substrate(p type) of NMOS.
• The reverse is true for Q2.
• The two parasitic transistors form a positive feedback loop.
Analysis of latchup formation:

If collector current of one of BJT is temporarily increased by disturbance, resulting


positive feedback loop causes current perturbation to be multiplied by β1β2 as explained
below.
The disturbance may be a spike of input voltage on an input or output pin, leading to
junction breakdown, or ionizing radiations.
Because collector current of one transistor Q1 is fed as input base current to another
transistor Q2, collector current of Q2, Ic2 = β2 * Ib2 and this collector current Ic2 is fed
as input base current Ib1 to another transistor Q1.
In this way both transistors feedback each other and the collector current of each goes on
multiplying.
Net gain of Silicon Controlled Rectifier (SCR) device = β1 *β2

Total current in one loop = current perturbation * Gain

If β1 *β2 >=1, both transistors will conduct a high saturation current even
after the triggering perturbation is no longer available. This current will
eventually becomes so large that it may damage the device.
Latch-up prevention techniques:

Simply put, latchup prevention/protection includes putting a high resistance in


the path so as to limit the current through supply and make β1 *β2 < 1. This can
be done with the help of following techniques:

Surrounding PMOS and NMOS transistors with an insulating oxide layer


(trench). This breaks parasitic SCR structure.

Latchup Protection Technology circuitry which shuts off the device when
latchup is detected.
IC Design Flow
IC design cycle involves several steps:

1. System Specification
a) Feasibility study and die size estimate
b) Function analysis

2. Architectural or System Level Design

3. Logic Design
a) Analogue Design, Simulation & Layout
b) Digital Design & Simulation
c) System Simulation & Verification

4. Circuit Design
a) Digital design synthesis
b) Design For Test and Automatic test pattern generation
c) Design for manufacturability (IC)

5. Physical Design
a) Floor planning
b) Place and Route
6. Physical Verification & Signoff
a) Static timing
b) Simulation
c) Tape-in
d) Mask data preparation
e) Tape-out

7. Wafer fabrication
8. Packaging

9. Chip test
a) Post silicon validation and integration
b) Device characterization

10. Chip Deployment


a) Datasheet generation
b) Production
c) Yield Analysis
d) Failure analysis
e) Plan for next generation chip
Scaling of MOS Circuits
Scaling Factors

• In our discussions we will consider 2 scaling factors, α and β

• 1/ β is the scaling factor for VDD and gate oxide thickness D

• 1/ α is scaling factor for all other linear dimensions (horizontal + vertical)

• We will assume electric field is kept constant


Scale
Scaling Factors for Device Parameters
Where:
𝑳
𝑹𝒐𝒏 =
𝝈∗𝑨

𝑸𝒐𝒏 ∗ 𝝁
𝝈=
𝒕
𝟏 𝜶𝟐
𝒇𝒐 = 𝒇𝒐 𝒊𝒔 𝒔𝒄𝒂𝒍𝒆𝒅 𝒃𝒚
𝜷
𝑻𝒅
1
𝐼𝑑𝑠𝑠 𝑖𝑠 𝑠𝑐𝑎𝑙𝑒𝑑 𝑏𝑦 ( )
𝛽

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