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MATLAB Experiments No. (4)

Digital Controller Design Using Root Locus

 Objectives:
The objectives of this experiment are to:
1. Design Phase Lag compensator using Root Locus, and see its effect on
the steady state error.
2. Design Phase Lead compensator using Root Locus, and see its effect on
the transient response.
 Digital Controller Design Using Root Locus:
The performance of a control system can be described in terms of the time
domain performance measures or the frequency domain performance
measures. The performance of a system can be specified by requiring a
certain peak time 𝑇𝑃 , maximum overshoot, and settling time for a step
input. Furthermore, it is usually necessary to specify the maximum
allowable steady state error for several test signal inputs and disturbance
inputs. These performance specifications can be defined in terms of the
desirable location of the poles and zeros of the closed loop transfer
function, the locus of the roots of the closed loop system can be readily
obtained for the variation of the system parameter. However, when the
locus of roots does not result in a suitable root configuration, we must add
a compensating network to alter the locus of the roots as the parameter is
varied. Therefore, we can use the Root Locus method and determine a
suitable compensator network transfer function - Lead or Lag- so that the
resultant Root Locus yields the desired closed loop root configuration.

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A different design technique is presented in this experiment: The Root

Locus procedure. Recall that the Root Locus for a system is a plot of the
roots of the system’s characteristic equation as gain is varied. Hence, the
character of the transient response of a system is evident from the Root
Locus. The design procedure is to add poles and zeros via a digital
controller so as to shift the roots of the characterstic equation to more
appropriate locations in the z-plane.
The transfer function of first order digital controller is:
𝑧 − 𝑧0
𝐷(𝑧) = 𝐾𝑑
𝑧 − 𝑧𝑃
Two basic types of compensators in this experiment will be designed:
1. Phase Lag Compensator.
2. Phase Lead Compensator.
Phase Lag Compensation:
The idea of the Lag compensater design is to place a pole and a zero close
to 𝑧 = 1, where 𝑧0 < 𝑧𝑃 . The Phase Lag compensator is an integration type
and can be used to increase the static error constants of a feedback control
system. Hence, the steady state error can be reduced.
 Design Procedure:
The design Phase Lag compensator using Root Locus by Emulation
method, consists of the following steps:
1. Design a Phase Lag compensator in the s-plane to meet all specifications.
2. Use Tustin transformation to specify and implement a digital
compensator 𝐺𝑐 (𝑠) with 𝐷(𝑧).
3. Choose an appropriate sampling interval.
4. Using simulation to verify the design.

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Example 5.1: Consider the unity feedback digital control system as shown
in Figure 5.1.

Figure 5.1: Digital control system of Example 5.1.

Do the following:
1. Design a Phase Lag compensator to reduce the steady state error by a
factor of approximately 4, if the system operating with 10 % overshoot
2. Compare the system characteristics with and without compensator.

Solution:
The first step is to find the proper 𝐺𝑐 (𝑠) for this system. We find the
specifications can be met by the compensation:
𝑠 + 0.3
𝐺𝑐 (𝑠) = 2.5
𝑠 + 0.075
The closed loop bandwidth of the system 𝜔𝐵𝑊 = 1.86 rad/sec, and an
appropriate sampling frequency would be faster than 𝜔𝐵𝑊 by a factor of
20. Thus:
𝜔𝑠 = 1.86 × 20 = 37.2 rad/sec.
Then, the sampling interval 𝑇 should be:

2𝜋 2𝜋
𝑇= = = 0.168 sec.
𝜔𝑠 37.2

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Let us choose the appropriate sampling interval 𝑇 = 0.15 sec. We have

𝑧−𝐴
𝐷(𝑧) = 𝐾𝑑
𝑧−𝐵
𝐴 = 𝑒 −0.3 𝑇 = 0.9559, and 𝐵 = 𝑒 −0.075𝑇 = 0.9888.
We now have:
𝑎1−𝐴
𝐾𝑑 = 𝐾 = 2.54.
𝑏1−𝐵
The digital Phase Lag compensator is:
𝑧 − 0.9559
𝐷(𝑧) = 2.54
𝑧 − 0.9888
% To obtain the ramp response of the system with and without digital compensator %
s=tf('s');
Gs=1/(s*(s+2));
Ds=2.5*(s+0.3)/(s+0.075);
Gz=c2d(Gs,0.15,’zoh’ ) ;
Dz= c2d(Ds,0.15,’tustin’ );
sys=feedback(2.86*Gs,1);
sysLagC=feedback(Gs*Ds,1);
sysLagD=feedback(Gz*Dz,1);
t=0:0.15:45;
r=t;
lsim(sys,sysLagC,sysLagD,r,t)

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Linear Simulation Results

45

40

35

30

25
Amplitude

20

15

10

0
0 5 10 15 20 25 30 35 40 45
Time (sec)

Figure 5.2: Ramp response of the system with and without Phase Lag compensator.

% To obtain the step response of the system with and without compensator %
step(sys,sysLagC,sysLagD)
gtext(‘Uncompensated System’)
gtext(‘Continuous Controlled System’)
gtext(‘Digital Controlled System’)

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Step Response
1.4
Digital Controlled System

1.2
Continuous Controlled System

Uncompensated System
0.8
Amplitude

0.6

0.4

0.2

0
0 2 4 6 8 10 12 14 16 18
Time (sec)

Figure 5.3: Compare the system with and without compensator

- continuous and digital- (Step Response).
Performance comparison between the uncompensated system and the
system with continuous and digital Phase Lag compensator:
Performance System Without System With System With
Specifications Compensator Continuous Compensator Digital Compensator

Rise Time (𝑇𝑅 ) 1.09 sec 1.04 sec 0.985 sec

Overshoot(𝑂𝑆%) 9.99 % 24.5 % 29.5 %

Peak Time(𝑇𝑃 ) 2.31 sec 2.59 sec 2.4 sec

Bandwidth(rad/sec) 1.959 1.86 1.958

Settling Time(𝑇𝑠 ) 3.5 sec 7.44 sec 7.77 sec

Error(Ramp) 0.7 0.18 0.18

What is the effect of adding Phase Lag compensator on the system? and
discuss the differences between continuous and digital compensator.

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Phase Lead Compensation:

The idea of the Lead compensater design is to place the compensator zero
equal with the plant pole 𝑧 = 𝑧2 as shown in Figure 5.4: The controller
pole is placed to the left of the zero 𝑧0 > 𝑧𝑃 , which yields the phase lead
compensator. Thus the Root Locus is shifted to the left. The resulting root
at 𝑧𝑏 has a smaller time constant than that at 𝑧𝑎 , thus the system responds
faster.

Figure 5.4: Phase Lead design.

 Design Procedure:
The design Phase Lead compensator using Root Locus, consists of the
following steps:
1. Choose 𝑧0 is one of the plant poles to cancel a pole of 𝐺(𝑧).
2. Determine the location of compensator pole 𝑧𝑃 < 𝑧0 such that the
compensator is Phase Lead.
3. Determine 𝐾𝑑 from 𝐾𝑑 = (1 − 𝑧𝑃 )/(1 − 𝑧0 ).
4. For a given root location 𝑧𝑎 (or you choose), find 𝐾𝑐 such that
𝐾𝑐 𝐷(𝑧𝑏 )𝐺(𝑧𝑏 ) = −1, that means you are on root locus.

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5. Have only set one root, so need to check complete system (all roots
behavior).
6. Simulate the compensated system, and redesign if the required
specifications are not met.
The Phase Lead compensator can be designed by Emulation method.
Example 5.2: Consider the digital control system as shown in Figure 5.5.

Figure 5.5: Digital control system of Example 5.2.

Do the following:
1. Design a Phase Lead compensator to increase the speed response of
the system. Assume that the sampling period is 0.1 sec.
2. Compare the system characteristics with and without compensator.
Solution:
% To draw Root Locus of the uncompensated system %
s=tf('s');
Gs=1/(s*(s+1));
Gz=zpk(c2d(Gs,0.1,’zoh’));
rlocus(Gz)

0.0048374(𝑧 + 0.9672)
𝐺(𝑧) =
(𝑧 − 1)(𝑧 − 0.9048)

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Root Locus
2.5

1.5
System: Gz
Gain: 0.244
1 Pole: 0.952 + 2.29e-009i
Damping: 1
0.5 Overshoot (%): 0
Imaginary Axis

Frequency (rad/sec): 0.494

0

-0.5

-1

-1.5

-2

-2.5
-6 -5 -4 -3 -2 -1 0 1 2
Real Axis

Figure 5.6: Root Locus of uncompensated system.

The Root Locus for 𝐺(𝑧) is shown in Figure 5.6. Note that 𝐾 is equal 0.244
for critical damping, with the two roots coincident at 𝑧 = 0.952. We will
choose a Phase Lead compensator with the zero at 0.9048, in order to cancel
one of the plant poles. We will place the compensator pole at 𝑧 = 0.7, which
should increase the system speed of response.
Determine the value of 𝐾𝑑 where:
1 − 𝑧𝑃 1 − 0.7
𝐾𝑑 = = = 3.15.
1 − 𝑧0 1 − 0.9048
Then:
𝑧 − 0.9048
𝐷(𝑧) = 3.15
𝑧 − 0.7
Note that 𝐾𝑑 = 3.15 such that 𝐷(1) = 1.

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% To draw Root Locus of the compensated system %

z=tf('z',0.1);
Dz=3.15*(z-0.9048)/(z-0.7);
rlocus(Gz*Dz)

Root Locus
2

1.5

System: untitled1
1
Gain: 0.814
Pole: 0.844
0.5 Damping: 1
Overshoot (%): 0
Imaginary Axis

Frequency (rad/sec): 1.7

0

-0.5

-1

-1.5

-2
-6 -5 -4 -3 -2 -1 0 1 2
Real Axis

Figure 5.7: Root Locus of the compensated system.

The Root Locus of the compensated system is also shown in Figure 5.7. We
choose critical damping as our design criterion; a value of 𝐾 = 0.814
results in a critically damped system, with roots at 𝑧 = 0.844; these values
were found by calculating the breakaway points.
% To obtain step response of the system with and without compensator %
sys=feedback(0.244*Gz,1);
sysLead=feedback(0.814*Gz*Dz,1);
step(sys,sysLead)
gtext(‘Uncompensated System’)
gtext(‘Compensated System’)

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Step Response
1.2

Compensated System
1

Uncompensated System
0.8
Amplitude

0.6

0.4

0.2

0
0 2 4 6 8 10 12 14 16 18
Time (sec)

Figure 5.8: Compare the system with and without Phase Lead compensator
(Step Response).

System performance comparison between the compensated and

uncompensated system:
System Without Phase System with Phase
System Performance
Lead Compensator Lead Compensator
Rise Time(𝑇𝑅 ) 6.8 sec 1.98 sec
Bandwidth(rad/sec) 0.317 1.09
Settling Time 11.8 sec 3.43 sec
Error (Ramp) 4 1

Discuss the effect of adding Phase Lead compensator on the system

performance.

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Example 5.3: Consider the digital control unity feedback system as shown
in Figure 5.9.

Figure 5.9: Digital control system of Example 5.3.

Do the following:
1. Design a digital compensator that yields a peak time is less than 1
second and overshoot no more than 15%.
2. Compare the results with the continuous compensator.
Solution:
The first step is to find the proper 𝐺𝑐 (𝑠) for the system defined in Figure
5.9. After trial and error using SISO Design Tool, we find the specifications
can be met by the lead compensation:
𝑠+𝑎 𝑠 + 1.37
𝐺𝑐 (𝑠) = 𝐾 = 16.5
𝑠+𝑏 𝑠 + 2.1
To digitize this 𝐺𝑐 (𝑠), we first need to select a sample rate. For a system
with closed loop bandwidth 𝜔𝐵𝑊 = 5.38 rad/sec, and a very safe sample
rate would be faster than 𝜔𝐵𝑊 by a factor of 20. Thus:
𝜔𝑠 = 5.38 × 20 = 107.6 rad/sec.
A sample rate of 107.6 rad/sec is about 17.12 Hz. Therefore, the sample
period should be 𝑇 = 0.05 sec. We have
𝑧−𝐴
𝐷(𝑧) = 𝐾𝑑
𝑧−𝐵

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𝐴 = 𝑒 −1.37 𝑇 = 0.9337, and 𝐵 = 𝑒 −2.1 𝑇 = 0.9003.

We now have:
𝑎1−𝐴 1.37 1 − 0.9003
𝐾𝑑 = 𝐾 = 16.5 = 16.18.
𝑏1−𝐵 2.1 1 − 0.9337
The digital Phase Lead compensator is:
𝑧 − 0.9337
𝐷(𝑧) = 16.18
𝑧 − 0.9003
% To obtain the step response of the system with and without digital compensator %
s=tf('s');
Gs=1/(s*(s+3));
Ds=16.5*(s+1.37)/(s+2.1);
Gz=c2d(Gs, 0.05,’zoh’ ) ;
Dz= c2d(Ds,0.05,’tustin’ );
sys=feedback(8.34*Gs,1);
sysLeadC=feedback(Gs*Ds,1);
sysLeadD=feedback(Gz*Dz,1);
step(sysLeadC,sysLeadD)
gtext(‘Uncompensated System’)
gtext(‘Continuous Controlled System’)
gtext(‘Digitally Controlled System’)

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Step Response
1.4

Digitally Controlled System

1.2

Uncompensated System
1

Continuous Controlled System

0.8
Amplitude

0.6

0.4

0.2

0
0 0.5 1 1.5 2 2.5 3 3.5 4
Time (sec)

Figure 5.10: Step response of compensated system(continuous and digital) and

uncompensated system.

Performance comparison between the uncompensated system and the

system with continuous and digital Phase Lead compensator:
Performance System Without System With System With
Specifications Compensator Continuous Compensator Digital Compensator

Rise Time (𝑇𝑅 ) 0.581 sec 0.396 sec 0.372 sec

Overshoot(𝑂𝑆%) 14.8 % 14.8 % 19.3 %

Peak Time(𝑇𝑃 ) 1.26 sec 0.847 sec 0.8 sec

Bandwidth(rad/sec) 3.60 5.38 5.57

Settling Time(𝑇𝑠 ) 2.7 sec 2.04 sec 2.02 sec

Error(Ramp) 0.36 0.28 0.28

Discuss the effect of adding Phase Lead compensator on the system

performance, and difference between continuous and digital compensator.

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Assignment 5.1: An important positioning system in manufacturing system

is a worktable motion control system. The system controls the motion of a
worktable at a certain location. We assume that the table is activated in
each axis by a motor and lead screw, as shown in Figure 5.11(a). We
consider the x-axis and examine the motion control for a feedback system,
as shown in Figure 5.11(b).

Figure 5.11: A table motion control system: (a) actuator and table, (b) block diagram.
Do the following:
1. Design 𝐷(𝑧) to such that the closed loop system response to a unit step
input has a percent overshoot no more than 5% and a settling time less
than 0.7 sec.
2. Determine the steady state errors for both the compensated and
uncompensated system to a unit ramp input.
3. Discuss the effects of the compensator designed in part (1) on the
transient response and steady state error.

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Assignment 5.1: Consider the control system shown in Figure 5.12.

Figure 5.12: Digital control system of Assignment 5.2.

Do the following:
1. Design a Phase Lag compensator 𝐺𝑐 (𝑠) in s-plane utilizing Root Locus
method to meet the design specifications:
a) Steady state error less than 10% for a step input.
b) Phase margin greater than 45°.
c) Settling time (with a 2% criterion) less than 5 seconds for a unit step
input.
2. Determine a suitable 𝐷(𝑧) to satisfy the requirements of part (1) using
𝐺𝑐 (𝑠) to 𝐷(𝑧) conversion method with a sampling period 𝑇 = 0.01 sec.
3. Plot the step response of the system with the continuous time
compensator 𝐺𝑐 (𝑠) of part (1) and of the digital system with the 𝐷(𝑧)
of part (2). Compare the results.
4. Repeat part (2) for 𝑇 = 0.001 sec and then repeat part (3).

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