PIC32

PIC32 Flash Programming Specification

1.0 DEVICE OVERVIEW 2.0 PROGRAMMING OVERVIEW
This document defines the Flash programming When in development of a programming tool, it is
specification for the PIC32 family of 32-bit necessary to understand the internal Flash program
microcontrollers. operations of the target device and the Special
This programming specification is designed to guide Function Registers (SFRs) used to control Flash
developers of external programmer tools. Customers programming, as these same operations and registers
who are developing applications for PIC32 devices are used by an external programming tool and its
should use development tools that already provide software. These operations and control registers are
support for device programming. described in the “Flash Program Memory” chapter in
the specific device data sheet, and the related “PIC32
The major topics of discussion include: Family Reference Manual” section. It is highly
• Section 1.0 “Device Overview” recommended that these documents be used in
• Section 2.0 “Programming Overview” conjunction with this programming specification.
• Section 3.0 “Programming Steps” An external tool programming setup consists of an
• Section 4.0 “Connecting to the Device” external programmer tool and a target PIC32 device.
Figure 2-1 illustrates a typical programming setup. The
• Section 5.0 “EJTAG vs. ICSP”
programmer tool is responsible for executing
• Section 6.0 “Pseudo Operations” necessary programming steps and completing the
• Section 7.0 “Entering 2-Wire Enhanced ICSP programming operation.
Mode”
• Section 8.0 “Check Device Status” FIGURE 2-1: PROGRAMMING SYSTEM
• Section 9.0 “Erasing the Device” SETUP
• Section 10.0 “Entering Serial Execution Mode”
• Section 11.0 “Downloading the Programming Target PIC32 Device
Executive (PE)”
• Section 12.0 “Downloading a Data Block” External CPU
• Section 13.0 “Initiating a Page Erase” Programmer
• Section 14.0 “Initiating a Flash Row Write”
• Section “”
• Section 16.0 “Exiting Programming Mode”
On-Chip Memory
• Section 17.0 “The Programming Executive”
• Section 18.0 “Checksum”
• Section 19.0 “Configuration Memory and Device
ID”
• Section 20.0 “TAP Controllers”
• Section 21.0 “AC/DC Characteristics and Timing
Requirements”
• Appendix A: “PIC32 Flash Memory Map”
• Appendix B: “Hex File Format”
• Appendix C: “Device IDs”
• Appendix D: “Revision History”

 2007-2021 Microchip Technology Inc. DS60001145AA-page 1

PIC32
2.1 Devices with Dual Flash Panel and 2.2 Programming Interfaces
Dual Boot Regions All PIC32 devices provide two physical interfaces to the
The PIC32MKXXXXXXD/E/F/K/L/M and PIC32MZ external programmer tool:
families of devices incorporate several features useful • 2-wire In-Circuit Serial Programming™ (ICSP™)
for field (self) programming of the device. These • 4-wire Joint Test Action Group (JTAG)
features include dual Flash panels with dual boot
regions, an aliasing scheme for the boot regions See Section 4.0 “Connecting to the Device” for
allowing automatic selection of boot code at start-up more information.
and a panel swap feature for Program Flash. The two Either of these methods may use a downloadable
Flash panels and their associated boot regions can be Programming Executive (PE). The PE executes from
erased and programmed separately. Refer to the the target device RAM and hides device programming
Section 48. “Memory Organization and details from the programmer. It also removes overhead
Permissions” (DS60001214) of the “PIC32 Family associated with data transfer and improves overall data
Reference Manual” for a detailed explanation of these throughput. Microchip has developed a PE that is
features. available for use with any external programmer, see
A development tool used for production programming Section 17.0 “The Programming Executive” for
will not be concerned about most of these features with more information.
the following exceptions: Section 3.0 “Programming Steps” describes high-
• Ensuring the SWAP bit (NVMCON[7]) is in the level programming steps, followed by a brief
proper setting. The default setting is ‘0’ for no swap explanation of each step. Detailed explanations are
of panels. The development tool should assume the available in corresponding sections of this document.
default setting when generating source files for the More information on programming commands, EJTAG,
programming tool. and DC specifications are available in the following
• Proper handling of the aliasing of the boot memory sections:
in the checksum calculation. The aliased sections • Section 19.0 “Configuration Memory and
will be duplicates of the fixed sections. See Device ID”
Section 18.0 “Checksum” for more information on
• Section 20.0 “TAP Controllers”
checksum calculations with aliased regions
• Section 21.0 “AC/DC Characteristics and
• For PIC32MK devices, using the Erase/Retry
Timing Requirements”
feature when an attempt to erase a Flash page fails
and needs to be retried. See Section 13.0
“Initiating a Page Erase” for more information. 2.3 Enhanced JTAG (EJTAG)
The 2-wire and 4-wire interfaces use the EJTAG
protocol to exchange data with the programmer. While
this document provides a working description of this
protocol as needed, advanced users are advised to
refer to the Imagination Technologies Limited web site
(www.imgtec.com) for more information.

2.4 Data Sizes

Data sizes are defined as follows:
• One word: 32 bits
• One-half word: 16 bits
• One-quarter word: 8 bits
• One Byte: 8 bits

DS60001145AA-page 2  2007-2021 Microchip Technology Inc.

 PIC32
3.0 PROGRAMMING STEPS The following sequence lists the programming steps
with a brief explanation of each step. More detailed
All tool programmers must perform a common set of information about these steps is available in the
steps, regardless of the actual method being used. subsequent sections.
Figure 3-1 shows the set of steps to program PIC32 1. Connect to the target device.
devices.
To ensure successful programming, all required
pins must be connected to appropriate signals.
FIGURE 3-1: PROGRAMMING FLOW
See Section 4.0 “Connecting to the Device”
for more information.
Start 2. Place the target device in programming mode.
For 2-wire programming methods, the target
device must be placed in a special programming
mode (Enhanced ICSP™) before executing any
Enter Enhanced ICSP™
other steps.
(Only required for 2-wire)
Note: For the 4-wire programming methods,
Step 2 is not applicable.
See Section 7.0 “Entering 2-Wire Enhanced
Check Device Status
ICSP Mode” for more information.
3. Check the status of the device.
Checks the status of the device to ensure it is
Erase Device ready to receive information from the
programmer.
See Section 8.0 “Check Device Status” for
more information.
Enter Serial Exec Mode
4. Erase the target device.
If the target memory block in the device is not
blank, or if the device is code-protected, an
Download the PE erase step must be performed before
(Optional) programming any new data.
See Section 9.0 “Erasing the Device” for
more information.
Download a Data Block 5. Enter programming mode.
Verifies that the device is not code-protected
and boots the TAP controller to start sending
and receiving data to and from the PIC32 CPU.
Initiate Flash Write
See Section 10.0 “Entering Serial Execution
Mode” for more information.

No
Done

Yes

Verify Device

Exit Programming Mode

Done

 2007-2021 Microchip Technology Inc. DS60001145AA-page 3

PIC32
6. Download the Programming Executive (PE).
The PE is a small block of executable code that
is downloaded into the RAM of the target device.
It will receive and program the actual data.
Note: If the programming method being used
does not require the PE, Step 6 is not
applicable.
See Section 11.0 “Downloading the
Programming Executive (PE)” for more
information.
7. Download the block of data to program.
All methods, with or without the PE, must
download the desired programming data into a
block of memory in RAM.
See Section 12.0 “Downloading a Data
Block” for more information.
8. Initiate Flash Write.
After downloading each block of data into RAM,
the programming sequence must be started to
program it into the target device’s Flash
memory.
See Section 14.0 “Initiating a Flash Row
Write” for more information.
9. Repeat Step 7 and Step 8 until all data blocks
are downloaded and programmed.
10. Verify the program memory.
After all programming data and Configuration
bits are programmed, the target device memory
should be read back and verified for the
matching content.
See Section “” for more information.
11. Exit the programming mode.
The newly programmed data is not effective until
either power is removed and reapplied to the
target device or an exit programming sequence
is performed.
See Section 16.0 “Exiting Programming
Mode” for more information.

DS60001145AA-page 4  2007-2021 Microchip Technology Inc.

 PIC32
4.0 CONNECTING TO THE DEVICE 4.1 4-wire Interface
The PIC32 family provides two possible physical One possible interface is the 4-wire JTAG (IEEE
interfaces for connecting and programming the 1149.1) port. Table 4-1 lists the required pin
memory contents, see Figure 4-1. For all programming connections. This interface uses the following four
interfaces, the target device must be powered and all communication lines to transfer data to and from the
required signals must be connected. In addition, the PIC32 device being programmed:
interface must be enabled, either through its • Test Clock Input (TCK)
Configuration bit, as in the case of the JTAG 4-wire
• Test Mode Select Input (TMS)
interface, or though a special initialization sequence, as
is the case for the 2-wire ICSP interface. • Test Data Input (TDI)
• Test Data Output (TDO)
The JTAG interface is enabled by default in blank
devices shipped from the factory. Refer to the specific device data sheet for the
connection of the signals to the device pins.
Enabling ICSP is described in Section 7.0 “Entering
2-Wire Enhanced ICSP Mode”. 4.1.1 TEST CLOCK INPUT (TCK)
TCK is the clock that controls the updating of the TAP
FIGURE 4-1: PROGRAMMING
controller and the shifting of data through the Instruc-
INTERFACES
tion or selected Data registers. TCK is independent of
the processor clock with respect to both frequency and
2-wire phase.
ICSP™
OR PIC32 4.1.2 TEST MODE SELECT INPUT (TMS)
Programmer 4-wire TMS is the control signal for the TAP controller. This
JTAG signal is sampled on the rising edge of TCK.
+ MCLR, VDDCORE(1), VDDR1V8(1),
VDDIO, VSS, VSS1V8(1) 4.1.3 TEST DATA INPUT (TDI)
TDI is the test data input to the Instruction or selected
Note 1: This pin is not available on all devices. Data register. This signal is sampled on the rising edge
Refer to the “Pin Diagrams” or “Pin of TCK for some TAP controller states.
Tables” section in the specific device data
sheet to determine availability. 4.1.4 TEST DATA OUTPUT (TDO)
TDO is the test data output from the Instruction or Data
registers. This signal changes on the falling edge of
TCK. TDO is only driven when data is shifted out,
otherwise the TDO is tri-stated.

TABLE 4-1: 4-WIRE INTERFACE PINS

Pin
Device Pin Name Pin Description
Type

MCLR I Programming Enable

(2)
ENVREG I Enable for On-Chip Voltage Regulator
VDD, VDDIO, VDDCORE(2), VDDR1V8(2), VBAT(2), P Power Supply
and AVDD(1)
VSS, VSS1V8(2), and AVSS(1) P Ground
VCAP(2) P CPU logic filter capacitor connection
TDI I Test Data In
TDO O Test Data Out
TCK I Test Clock
TMS I Test Mode State
Legend: I = Input O = Output P = Power
Note 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground (AVSS).
2: This pin is not available on all devices. Refer to the “Pin Diagrams” or “Pin Tables” section in the specific
device data sheet to determine availability.

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PIC32
4.2 2-wire Interface 4.2.1 SERIAL PROGRAM CLOCK
(PGECX)
Another possible interface is the 2-wire ICSP port.
Table 4-2 lists the required pin connections. This PGECx is the clock that controls the updating of the
interface uses the following two communication lines to TAP controller and the shifting of data through the
transfer data to and from the PIC32 device being Instruction or selected Data registers. PGECx is
programmed: independent of the processor clock, with respect to
both frequency and phase.
• Serial Program Clock (PGECx)
• Serial Program Data (PGEDx) 4.2.2 SERIAL PROGRAM DATA (PGEDX)
These signals are described in the following two PGEDx is the data input/output to the Instruction or
sections. Refer to the specific device data sheet for the selected Data Registers, it is also the control signal for
connection of the signals to the chip pins. the TAP controller. This signal is sampled on the falling
edge of PGECx for some TAP controller states.

TABLE 4-2: 2-WIRE INTERFACE PINS

Device Programmer
Pin Type Pin Description
Pin Name Pin Name

MCLR MCLR P Programming Enable

(2)
ENVREG N/A I Enable for On-Chip Voltage Regulator
VDD, VDDIO, VBAT(2), and AVDD(1) VDD P Power Supply
VDDCORE(2) and VDDR1V8(2) N/A P Power Supply for DDR Interface
VSS, VSS1V8(2), and AVSS(1) VSS P Ground
VCAP(2) N/A P CPU Logic Filter Capacitor Connection
PGECx PGEC I Primary Programming Pin Pair: Serial Clock
PGEDx PGED I/O Primary Programming Pin Pair: Serial Data
Legend: I = Input O = Output P = Power
Note 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground (AVSS).
2: This pin is not available on all devices. Refer to either the “Pin Diagrams” or “Pin Tables” section in the
specific device data sheet to determine availability.

DS60001145AA-page 6  2007-2021 Microchip Technology Inc.

 PIC32
4.3 PIC32MX Power Requirements 4.4 PIC32MX With VBAT Pin Power
Devices in the PIC32MX family are dual voltage
Requirements
supply designs. There is one supply for the core and Some devices in the PIC32MX family provide a VBAT
another for peripherals and I/O pins. All devices pin which can be connected to the VDD power supply
contain an on-chip regulator for the lower voltage during programming. See Figure 4-3.
core supply to eliminate the need for an additional
external regulator. There are three implementations FIGURE 4-3: PIC32MX WITH VBAT PIN
of the on board regulator:
POWER CONNECTIONS
• The first version has an internal regulator that can
be disabled using the ENVREG pin. When disabled, 3.3V(1)
an external power supply must be used to power the PIC32MX XLP

core. If enabled, a low-ESR filter capacitor must be VDD

connected to the VCAP pin, see Figure 4-2. VBAT
• The second version has an internal regulator that
VCAP
cannot be disabled. A low-ESR filter capacitor must
always be connected to the VCAP pin. VSS
• The third version has an internal regulator that
cannot be disabled and does not require a filter
capacitor Note 1: This is typical operating voltage. Refer to
Section 21.0 “AC/DC Characteristics and Timing
Refer to Section 21.0 “AC/DC Characteristics and Requirements” for the full operating range of VDD.
Timing Requirements” and the “Electrical
Characteristics” chapter in the specific device data
sheet for the power requirements for your device. 4.5 PIC32MZ EC and PIC32MZ EF
Power Requirements
FIGURE 4-2: INTERNAL REGULATOR Devices in the PIC32MZ EC and PIC32MZ EF families
ENABLE/DISABLE are also dual voltage supply designs like PIC32MX
OPTIONS devices. However, the internal regulator does not
Regulator Enabled(2) require the external filter capacitor, and there is no cor-
(ENVREG tied to VDD) responding VCAP or ENVREG pins. See Figure 4-4.
3.3V Refer to Section 21.0 “AC/DC Characteristics and
PIC32MX Timing Requirements” and the “Electrical
VDD Characteristics” chapter in the specific device data
ENVREG
sheet for the power requirements for your device.

VCAP FIGURE 4-4: PIC32MZ EC/EF POWER

CEFC CONNECTIONS
VSS
(10 F typical)
3.3V(1)
Regulator Disabled(2) PIC32MZ EC/EF
(ENVREG tied to ground)
VDD
1.8V(1) 3.3V(1)
PIC32MX VSS
VDD
ENVREG

VCAP Note 1: This is typical operating voltage. Refer to

Section 21.0 “AC/DC Characteristics and Timing
VSS Requirements” for the full operating range of VDD.

Note 1: These are typical operating voltages. Refer to

Section 21.0 “AC/DC Characteristics and Timing
Requirements” for the full operating ranges of VDD
and VCAP.
2: Regulator Enabled and Regulator Disabled mode
are not available on all devices. Refer to the specific
device data sheet to determine availability.

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PIC32
4.6 PIC32MZ DA Power Requirements 4.8 PIC32MZ W1 Power Requirements
Devices in the PIC32MZ DA family are quadruple Devices in the PIC32MZ W1 family are triple voltage
voltage supply designs. Two of the voltage supplies are supply designs. Two of the voltage supplies are identi-
identical to the PIC32MZ EC and PIC32MZ EF voltage cal to the PIC32MZ EC and PIC32MZ EF voltage sup-
supplies. The third voltage supply is for the DDR plies. Connect the voltage supplies of the PIC32MZ W1
memory interface, and requires a 1.8 volt supply. The family of devices as shown in the following figure.
fourth voltage supply is for the VBAT pin, but it can be
connected to the VDD power supply. See Figure 4-5. FIGURE 4-7: PIC32MZ W1 POWER
Refer to Section 21.0 “AC/DC Characteristics and CONNECTIONS
Timing Requirements” and the “Electrical
Characteristics” chapter in the specific device data 3.3V(1)
sheet for the power requirements for your device. PIC32MZ W1
VDD
FIGURE 4-5: PIC32MZ DA POWER VBAT
CONNECTIONS

1.8V(1) 3.3V(1)
VSS
PIC32MZ DA
VDDIO
VBAT Note 1: These are typical operating voltages. Refer to
Section 21.0 “AC/DC Characteristics and Timing
VDDCORE and VDDR1V8 Requirements” for the full operating ranges of VDD
VSS1V8 and VBAT.
VSS

Note 1: These are typical operating voltages. Refer to

Section 21.0 “AC/DC Characteristics and Timing
Requirements” for the full operating ranges of
VDDIO, VBAT, VDDCORE and VDDR1V8.

4.7 PIC32MK Power Requirements

Devices in the PIC32MK family are triple voltage supply
designs. Two of the voltage supplies are identical to the
PIC32MZ EC and PIC32MZ EF voltage supplies. The
third voltage supply is for the VBAT pin, but it can be
connected to the VDD power supply. See Figure 4-6.

FIGURE 4-6: PIC32MK POWER

CONNECTIONS

3.3V(1)
PIC32MK
VDD
VBAT

VSS

Note 1: These are typical operating voltages. Refer to

Section 21.0 “AC/DC Characteristics and Timing
Requirements” for the full operating ranges of VDD
and VBAT.

DS60001145AA-page 8  2007-2021 Microchip Technology Inc.

 PIC32
5.0 EJTAG vs. ICSP FIGURE 5-1: TAP CONTROLLER
Programming is accomplished through the EJTAG Tap Controller
module in the CPU core. EJTAG is connected to either
TMS
the full set of JTAG pins or a reduced 2-wire to 4-wire
EJTAG interface for ICSP mode. In both modes,
programming of the PIC32 Flash memory is
accomplished through the ETAP controller. The TAP
TCK
Controller uses the TMS pin to determine if Instruction
or Data registers should be accessed in the shift path
TDO
between TDI and TDO, see Figure 5-1.
The basic concept of EJTAG that is used for TDI
programming is the use of a special memory area
Instruction, Data,
called DMSEG (0xFF200000 to 0xFF2FFFFF), which and Control Registers
is only available when the processor is running in
Debug mode. All instructions are serially shifted into an
internal buffer, and then loaded into the Instruction
register and executed by the CPU. Instructions are fed
through the ETAP state machine in 32-bit groups. 5.1 Programming Interface
Figure 5-2 shows the basic programming interface in
PIC32 devices. Descriptions of each interface block are
provided in subsequent sections.

FIGURE 5-2: BASIC PIC32 PROGRAMMING INTERFACE BLOCK DIAGRAM

TMS Common

TCK VDD/VDDIO/VDD1V8CORE
ETAP CPU VBAT/VDDR1V8
TDI VSS/VSS1V8

TDO Flash
MTAP
Controller MCLR
or

PGECx 2-wire Flash

to Memory
PGEDx 4-wire

5.1.1 ETAP Instructions. The MTAP_COMMAND instruction provides

a mechanism for a JTAG probe to send commands to
This block serially feeds instructions and data into the
the device through its Data register.
CPU.
The programmer sends commands by shifting in the
5.1.2 MTAP MTAP_COMMAND instruction through the SendCommand
In addition to the EJTAG TAP (ETAP) controller, the pseudo operation, and then sending the MTAP_COM-
PIC32 device uses a second proprietary TAP controller MAND DR commands through the XferData pseudo
for additional operations. The Microchip TAP (MTAP) operation, see Table 20-2 for specific commands.
controller supports two instructions relevant to The probe does not need to issue a MTAP_COMMAND
programming: MTAP_COMMAND and TAP switch instruction for every command shifted into the Data
Instructions. See Table 20-1 for a complete list of register.

 2007-2021 Microchip Technology Inc. DS60001145AA-page 9

PIC32
5.1.3 2-WIRE TO 4-WIRE words (4096 bytes) or 4096 words (16,384 bytes). Row
size indicates the number of words that are
This block converts the 2-wire ICSP interface to the
programmed with the row program command. There
4-wire JTAG interface.
are always 8 rows within a page; therefore, devices
5.1.4 CPU with 256, 1024, and 4096 word page sizes have 32,
128, and 512 word row sizes, respectively. Table 5-1
The CPU executes instructions at 8 MHz through the shows the PFM, BFM, row, and page size of each
internal oscillator. device family.
5.1.5 FLASH CONTROLLER For a PIC32MZ W1 device, the BFM begins at address
0x1FC00000, and the PFM begins at address
The Flash controller controls erasing and programming 0x10000000. The Flash is divided into pages of 1024
of the Flash memory on the device. words or 4 kbytes, which represents the smallest block
of memory that can be erased. Row size indicates the
5.1.6 FLASH MEMORY
number of words that are programmed with row
The PIC32 device Flash memory is divided into two program commands. The Flash contains 4 rows within
logical Flash partitions consisting of the Boot Flash a page with a total row size of 256 words or 1024 bytes.
Memory (BFM) and Program Flash Memory (PFM).
Memory locations of the BFM are reserved for the
The BFM begins at address 0x1FC00000, and the PFM
device Configuration registers, see Section 19.0
begins at address 0x1D000000. Each Flash partition is
“Configuration Memory and Device ID” for more
divided into pages, which represent the smallest block
information.
of memory that can be erased. Depending on the
device, page sizes are 256 words (1024 bytes), 1024

TABLE 5-1: CODE MEMORY SIZE

Row Size Page Size Boot Flash Memory Address Programming Executive
PIC32 Device
(Words) (Words) (Bytes) (See Note 1) (See Notes 2 and 3)
PIC32MX
110/120/130/150/170
210/220/230/350/270
(28/36/44-pin devices Only)
0x1FC00000-0x1FC00BFF (3 KB)
PIC32MX
120/130/150/170/230/250/ 32 256 RIPE_11_aabbcc.hex
270/530/550/570
(64/100-pin devices Only)
PIC32MX
15X/17X/25X/27X 0x1FC00000-0x1FC02FFF (12 KB)
(28/44-pin devices Only)
PIC32MZ W1 256 1024 0x1FC00000-0x1FC0FFFF (64 KB) —
Note 1: Program Flash Memory address ranges are based on Program Flash size are as given below:
• 0x1D000000-0x1D003FFF (16 KB)
• 0x1D000000-0x1D007FFF (32 KB)
• 0x1D000000-0x1D00FFFF (64 KB)
• 0x1D000000-0x1D01FFFF (128 KB)
• 0x1D000000-0x1D03FFFF (256 KB)
• 0x1D000000-0x1D07FFFF (512 KB)
• 0x1D000000-0x1D0FFFFF (1024 KB)
• 0x1D000000-0x1D1FFFFF (2048 KB)
All Program Flash memory sizes are not supported by each family.
Program Flash Memory address ranges for PIC32MZ W1: 0x10000000-0x100FFFFF (1024 KB).
2: The Programming Executive can be obtained from the related product page on the Microchip website or it can be
located in the following MPLAB® X IDE installation folders:
…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\REALICE.jar
…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\ICD3.jar
…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\PICKIT3.jar
3: The last characters of the file name, aabbcc, vary based on the revision of the file.

DS60001145AA-page 10  2007-2021 Microchip Technology Inc.

 PIC32
TABLE 5-1: CODE MEMORY SIZE (CONTINUED)
Row Size Page Size Boot Flash Memory Address Programming Executive
PIC32 Device
(Words) (Words) (Bytes) (See Note 1) (See Notes 2 and 3)
PIC32MX
330/350/370/430/450/470
PIC32MX
320/340/360/420/440/460
128 1024 0x1FC00000-0x1FC02FFF (12 KB) RIPE_06_aabbcc.hex
PIC32MX
534/564/664/764
PIC32MX
575/675/695/795
PIC32MK 0x1FC00000-0x1FC04FFF (20 KB)
128 1024 RIPE_15a_aabbcc.hex
0512/1024XXD/E/F/K/L/M 0x1FC20000-0x1FC24FFF (20 KB)
PIC32MK
128 1024 0x1FC00000-0x1FC04FFF (20 KB) RIPE_15a_aabbcc.hex
0256/0512XXG/H
PIC32MZ 0x1FC00000-0x1FC13FFF (80 KB)
512 4096 RIPE_15_aabbcc.hex
05XX/10XX/20XX 0x1FC20000-0x1FC33FFF (80 KB)
PIC32MZ W1 256 1024 0x1FC00000-0x1FC0FFFF (64 KB) RIPE_25_aabbcc.hex
Note 1: Program Flash Memory address ranges are based on Program Flash size are as given below:
• 0x1D000000-0x1D003FFF (16 KB)
• 0x1D000000-0x1D007FFF (32 KB)
• 0x1D000000-0x1D00FFFF (64 KB)
• 0x1D000000-0x1D01FFFF (128 KB)
• 0x1D000000-0x1D03FFFF (256 KB)
• 0x1D000000-0x1D07FFFF (512 KB)
• 0x1D000000-0x1D0FFFFF (1024 KB)
• 0x1D000000-0x1D1FFFFF (2048 KB)
All Program Flash memory sizes are not supported by each family.
Program Flash Memory address ranges for PIC32MZ W1: 0x10000000-0x100FFFFF (1024 KB).
2: The Programming Executive can be obtained from the related product page on the Microchip website or it can be
located in the following MPLAB® X IDE installation folders:
…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\REALICE.jar
…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\ICD3.jar
…\Microchip\MPLABX\<version>\mplab_ide\mplablibs\modules\ext\PICKIT3.jar
3: The last characters of the file name, aabbcc, vary based on the revision of the file.

 2007-2021 Microchip Technology Inc. DS60001145AA-page 11

PIC32
5.2 4-wire JTAG Details
The 4-wire interface uses standard JTAG (IEEE
1149.1-2001) interface signals.
• TCK: Test Clock – drives data in/out
• TMS: Test Mode Select – selects operational mode
• TDI: Test Data Input – data into the device
• TDO: Test Data Output – data out of the device
Since only one data line is available, the protocol is
necessarily serial (like SPI). The clock input is at the
TCK pin. Configuration is performed by manipulating a
state machine bit by bit through the TMS pin. One bit of
data is transferred in and out per TCK clock pulse at the
TDI and TDO pins. Different instruction modes can be
loaded to read the chip ID or manipulate chip functions.
Data presented to TDI must be valid for a chip-specific
setup time before, and hold time, after the rising edge
of TCK. TDO data is valid for a chip-specific time after
the falling edge of TCK, refer to Figure 5-3.

FIGURE 5-3: 4-WIRE JTAG INTERFACE

TCK

‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’

TMS ‘1’

TDI iLSb iMSb

TDO oLSb oMSb

DS60001145AA-page 12  2007-2021 Microchip Technology Inc.

 PIC32
5.3 2-wire ICSP Details 5.3.2 2-PHASE ICSP
In ICSP mode, the 2-wire ICSP signals are time In 2-phase ICSP mode, the TMS and TDI device pins
multiplexed into the 2-wire to 4-wire block. The 2-wire are multiplexed into PGEDx in two clocks, see
to 4-wire block then converts the signals to look like a Figure 5-5. The LSb is shifted first; and TDI and TMS
4-wire JTAG port to the TAP controller. The following are sampled on the falling edge of PGECx. There is no
are two possible modes of operation: TDO output provided in this mode. The 2-phase ICSP
• 4-phase ICSP mode was designed to accelerate 2-wire, write-only
• 2-phase ICSP transactions.
Note: The packet is not actually executed until
5.3.1 4-PHASE ICSP the first clock of the next packet. To enter
In 4-phase ICSP mode, the TDI, TDO and TMS device 2-wire, 2-phase ICSP mode, the TDOEN
pins are multiplexed onto PGEDx in four clocks, see bit (DDPCON[0] or CFGCON[0]) must be
Figure 5-4. The Least Significant bit (LSb) is shifted set to ‘0’.
first; and TDI and TMS are sampled on the falling edge
of PGECx, while TDO is driven on the falling edge of
PGECx. The 4-phase ICSP mode is used for both read
and write data transfers.

FIGURE 5-4: 2-WIRE, 4-PHASE

TCK

‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’

TMS ‘1’

TDI IR0 IR4

TDO 1 X

PGECx

PGEDx pTDO = 1 TDI = IR0 TMS = 0 nTDO = 0

 2007-2021 Microchip Technology Inc. DS60001145AA-page 13

PIC32
FIGURE 5-5: 2-WIRE, 2-PHASE

TCK

‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’

TMS ‘1’

TDI IR0 IR4

TDO 1 X

PGECx

PGEDx TDI = IR0 TMS = 0

5.3.3 SYNCHRONIZATION When asserting the PGEDx pin high, there may be
contention on the pin as the device may attempt to
Some PIC32 devices can Reset the internal EJTAG
drive TDO out onto the pin while the in-circuit emulator
state machine if the attached programmer loses syn-
is driving in. This will only occur for a maximum of one
chronization with it. This can occur when noise is pres-
cycle as TMS high will advance the EJTAG state
ent on the PGCx signal.
machine out of a Shift-IR or Shift-DR state.
To achieve resynchronization, the PGEDx pin is held
Synchronization in 2-wire, 2-phase mode is not
high for 24 PGECx clock cycles. This forces five TMS
supported.
events into the EJTAG controller and will place the
EJTAG state machine into a Test Idle Reset. See
Figure 5-6 for an example of how to achieve
resynchronization.

FIGURE 5-6: ACHIEVING RESYNCHRONIZATION

PGECx 1 4 5 21 22 23 24
§

2 3
§

PGEDx
TDO Contention Synchronization achieved

DS60001145AA-page 14  2007-2021 Microchip Technology Inc.

 PIC32
6.0 PSEUDO OPERATIONS 6.1 SetMode Pseudo Operation
To simplify the description of programming details, all Format:
operations will be described using pseudo operations. SetMode (mode)
There are several functions used in the pseudo-code Purpose:
descriptions. These are used either to make the To set the EJTAG state machine to a specific state.
pseudo-code more readable, to abstract
implementation-specific behavior or both. When Description:
passing parameters with pseudo operation, the The value of mode is clocked into the device on
following syntax will be used: signal TMS. TDI is set to a ‘0’ and TDO is ignored.

• 5’h0x03 – send 5-bit hexadecimal value of 3 Restrictions:

None.
• 6’b011111 – send 6-bit binary value of 31
Example:
These functions are defined in this section, and include
SetMode (6’b011111)
the following operations:
• SetMode (mode)
• SendCommand (command)
• oData = XferData (iData)
• oData = XferFastData (iData)
• oData = XferInstruction (instruction)

FIGURE 6-1: SetMode 4-WIRE

Mode = 6’b011111

TCK

‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’

TMS

TDI

TDO

FIGURE 6-2: SetMode 2-WIRE

Mode = 6’b011111

PGECx

PGEDx TDI = 0 TMS = 1 TDO = 1 TDI = 0 TMS = 0 TDO = x

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PIC32
6.2 SendCommand Pseudo Operation
Format:
SendCommand (command)
Purpose:
To send a command to select a specific TAP register.
Description (in sequence):
1. The TMS Header is clocked into the device to
select the Shift IR state
2. The command is clocked into the device on
TDI while holding signal TMS low.
3. The last Most Significant bit (MSb) of the
command is clocked in while setting TMS
high.
4. The TMS Footer is clocked in on TMS to return
the TAP controller to the Run/Test Idle state.
Restrictions:
None.
Example:
SendCommand (5’h0x07)

FIGURE 6-3: SendCommand 4-WIRE

Command (MSb)
TMS Header = 1100 Command = 5’h0x07 + TMS = 1 TMS Footer = 10

TCK

‘1’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’

TMS

TDI iLSb iMSb

TDO 1 x

FIGURE 6-4: SendCommand 2-WIRE (4-PHASE)

TMS Header = 1100 Command (5’h0x07) + TMS = 0 Command (MSb) + TMS = 1 TMS Footer = 10

PGECx

PGEDx
TDI = 0 TMS = 1 TDO = x TDI = iLSb TMS = 0 TDO = x TDI = iMSb TMS = 1 TDO = x TDI = 0 TMS = 1 TDO = x

DS60001145AA-page 16  2007-2021 Microchip Technology Inc.

 PIC32
6.3 XferData Pseudo Operation
Format:
oData = XferData (iData)
Purpose:
To clock data to and from the register selected by the
command.
Description (in sequence):
1. The TMS Header is clocked into the device to
select the Shift DR state.
2. The data is clocked in/out of the device on
TDI/TDO while holding signal TMS low.
3. The last MSb of the data is clocked in/out
while setting TMS high.
4. The TMS Footer is clocked in on TMS to return
the TAP controller to the Run/Test Idle state.
Restrictions:
None.
Example:
oData = XferData (32’h0x12)

FIGURE 6-5: XferData 4-WIRE

TMS Header = 100 Data (32’h0x12) Data (MSb) + TMS =1 TMS Footer = 10

TCK

‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’

TMS

TDI iLSb iMSb

TDO oLSb oMSb

FIGURE 6-6: XferData 2-WIRE (4-PHASE)

TMS Header = 100

PGEC

PGED TDI = 0 TMS = 1 TDO = X TDI = 0 TMS = 0 TDO = X TDI = 0 TMS = 0 TDO = oLSb

Data (31’h0x12) + TMS = 0 Data (MSb) + TMS Footer = 1

TDI = iLSb TMS = 0 TDO =...

oLSb+1 TDI = iMSb TMS = 1 TDO = X

TMS Footer = 10

TDI = 0 TMS = 1 TDO = X TDI = 0 TMS = 0 TDO = X

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PIC32
6.4 XferFastData Pseudo Operation Restrictions:
The SendCommand (ETAP_FASTDATA) must be sent
Format: first to select the Fastdata register, as shown in
oData = XferFastData (iData) Example 6-1. See Table 20-4 for a detailed descriptions
Purpose: of commands.
To quickly send 32 bits of data in/out of the device.
Note: The 2-phase XferData is only used when
Description (in sequence): talking to the PE. See Section 17.0 “The
1. The TMS Header is clocked into the device to Programming Executive” for more
select the Shift DR state. information.
Note: For 2-wire (4-phase) – on the last clock,
the oPrAcc bit is shifted out on TDO while EXAMPLE 6-1: SendCommand
clocking in the TMS Header. If the value of // Select the Fastdata Register
oPrAcc is not ‘1’, the whole operation SendCommand(ETAP_FASTDATA)
must be repeated. // Send/Receive 32-bit Data
oData = XferFastData(32’h0x12)
2. The input value of the PrAcc bit, which is ‘0’, is
clocked in.
Note: For 2-wire (4-phase) – the TDO during this
operation will be the LSb of output data.
The rest of the 31 bits of the input data are
clocked in and the 31 bits of output data
are clocked out. For the last bit of the input
data, the TMS Footer = 1 is set.

3. TMS Footer = 10 is clocked in to return the TAP

controller to the Run/Test Idle state.

FIGURE 6-7: XferFastData 4-WIRE

TMS Header = 100 PrAcc Data (32’h0x12) Data (MSb) + TMS = 1 TMS Footer = 10

TCK

‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’

TMS

TDI ‘0’ iLSb iMSb

TDO ‘1’ oLSb oMSb

FIGURE 6-8: XferFastData 2-WIRE (2-phase)

TMS Header = 100 PrAcc Data (32’h0x12) Data (MSb) TMS = 1 TMS Footer = 10

PGECx

PGEDx TDI = X TMS = 1 TDI = 0 TMS = 0 TDI = TMS = 0 TDI = TMS = 1 TDI = X TMS = 1
iLSb MSb

DS60001145AA-page 18  2007-2021 Microchip Technology Inc.

 PIC32
FIGURE 6-9: XferFastData 2-WIRE (4-PHASE)
TMS Header = 100

PGECx

PGEDx TDI = 0 TMS = 1 TDO = X TDI = 0 TMS = 0 TDO = X TDI = 0 TMS = 0 TDO = oPrAcc

PrAcc Data (31’h12) + TMS = 0 Data (MSb) + TMS Footer = 1

TDI = 0 TMS = 0 TDO = oLSb TDI = iLSb TMS = 0 TDO = oLSb+1 TDI = iMSb TMS = 1 TDO = X

TMS Footer = 10

TDI = 0 TMS = 1 TDO = X TDI = 0 TMS = 0 TDO = X

 2007-2021 Microchip Technology Inc. DS60001145AA-page 19

PIC32
6.5 XferInstruction Pseudo
Operation
Format:
XferInstruction (instruction)
Purpose:
To send 32 bits of data for the device to execute.
Description:
The instruction is clocked into the device and then
executed by CPU.
Restrictions:
The device must be in Debug mode.

EXAMPLE 6-2: XferInstruction

XferInstruction (instruction)
{
// Select Control Register
SendCommand(ETAP_CONTROL);
// Wait until CPU is ready
// Check if Processor Access bit (bit 18) is set
do {
controlVal = XferData(32’h0x0004C000);
} while( PrAcc(contorlVal[18]) is not ‘1’ );

// Select Data Register

SendCommand(ETAP_DATA);

// Send the instruction

XferData(instruction);

// Tell CPU to execute instruction

SendCommand(ETAP_CONTROL);
XferData(32’h0x0000C000);
}

DS60001145AA-page 20  2007-2021 Microchip Technology Inc.

 PIC32
6.6 ReadFromAddress Pseudo
Operation
Format:
oData = ReadFromAddress (address)
Purpose:
To send 32 bits of data to the device memory.
Description:
The 32-bit data is read from the memory at the
address specified in the “address” parameter.
Restrictions:
The device must be in Debug mode.

EXAMPLE 6-3: ReadFromAddress FOR PIC32MX, PIC32MZ AND PIC32MK DEVICES

ReadFromAddress (address)
{

// Load Fast Data register address to s3

instruction = 0x3c130000;
instruction |= (0xff200000>>16)&0x0000ffff;
XferInstruction(instruction); // lui s3, <FAST_DATA_REG_ADDRESS(31:16)> - set address of fast
data register

// Load memory address to be read into t0

instruction = 0x3c080000;
instruction |= (address>>16)&0x0000ffff;
XferInstruction(instruction); // lui t0, <DATA_ADDRESS(31:16)> - set address of data
instruction = 0x35080000;
instruction |= (address&0x0000ffff);
XferInstruction(instruction); // ori t0, <DATA_ADDRESS(15:0)> - set address of data

// Read data
XferInstruction(0x8d090000); // lw t1, 0(t0)

// Store data into Fast Data register

XferInstruction(0xae690000); // sw t1, 0(s3) - store data to fast data register
XferInstruction(0); // nop

// Shift out the data

SendCommand(ETAP_FASTDATA);
oData = XferFastData(32'h0x00000000);

return oData;

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PIC32
6.7 Synchronize Pseudo Operation
Format:
Synchronize ()
Purpose:
To reset the EJTAG state machine into Test Idle
Reset.
Description:
The PGEDx signal is held high for 24 PGECx clock
cycles. All other signals are ignored.
Restrictions:
None.

FIGURE 6-10: ACHIEVING RESYNCHRONIZATION

PGECx 1 4 5 21 22 23 24

§
2 3

§
PGEDx
TDO Contention Synchronization achieved

DS60001145AA-page 22  2007-2021 Microchip Technology Inc.

 PIC32
7.0 ENTERING 2-WIRE ENHANCED The key sequence is a specific 32-bit pattern: ‘0100
1101 0100 0011 0100 1000 0101 0000’ (the
ICSP MODE
acronym ‘MCHP’, in ASCII). The device will enter
To use the 2-wire PGEDx and PGECx pins for pro- Program/Verify mode only if the key sequence is valid.
gramming, they must be enabled. Note that any pair of The MSb of the Most Significant nibble must be shifted
programming pins available on a particular device may in first.
be used, however, they must be used as a pair. PGED1 Once the key sequence is complete, VIH must be
must be used with PGEC1, and so on. applied to the MCLR pin and held at that level for as
Note: If using the 4-wire JTAG interface, the long as the 2-wire Enhanced ICSP interface is to be
following procedure is not necessary. maintained. An interval of at least time P19 and P7
must elapse before presenting data on PGEDx. Signals
The following steps are required to enter 2-wire appearing on PGEDx before P7 has elapsed will not be
Enhanced ICSP mode: interpreted as valid.
1. The MCLR pin is briefly driven high, then low. Upon successful entry, the programming operations
2. A 32-bit key sequence is clocked into PGEDx. documented in subsequent sections can be performed.
3. The MCLR pin is then driven high within a While in 2-wire Enhanced ICSP mode, all unused I/Os
specified period of time and held. are placed in the high-impedance state.
Refer to Section 21.0 “AC/DC Characteristics and Note: Entry into ICSP mode places the device in
Timing Requirements” for timing requirements. Reset to prevent instructions from
The programming voltage applied to the MCLR pin is executing. To release the Reset, the
VIH, which is essentially VDD, in PIC32 devices. There MCHP_DE_ASSERT_RST command must
is no minimum time requirement for holding at VIH. be issued.
After VIH is removed, an interval of at least P18 must
elapse before presenting the key sequence on PGEDx.

FIGURE 7-1: ENTERING ENHANCED ICSP™ MODE

P20
P6
P19 P7
P14
VIH VIH
MCLR

VDD
Program/Verify Entry Code = 0x4D434850
PGEDx 0 1 0 0 1 ... 0 0 0 0
b31 b30 b29 b28 b27 b3 b2 b1 b0

PGECx
P18 P1A
P1B

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PIC32
8.0 CHECK DEVICE STATUS 8.1 4-wire Interface
Before a device can be programmed, the programmer The setup sequence to enter 4-wire JTAG program-
must check the status of the device to ensure that it is ming should be done while asserting the MCLR pin.
ready to receive information. Once the programming mode is entered, the MCLR pin
can be released to allow the processor to execute
FIGURE 8-1: CHECK DEVICE STATUS instructions or drive ports.
The following steps are required to check the device
status using the 4-wire interface:
Set MCLR low 4-wire 1. Set the MCLR pin low.
2. SetMode (6’b011111) to force the Chip TAP
controller into Run Test/Idle state.
3. SendCommand (MTAP_SW_MTAP).
4. SetMode (6’b011111) to force the Chip TAP
SetMode (6’b011111)
controller into Run Test/Idle state.
5. SendCommand (MTAP_COMMAND).
6. statusVal = XferData (MCHP_STATUS).
SendCommand (MTAP_SW_MTAP) 7. If CFGRDY (statusVal[3]) is not ‘1’ and FCBUSY
(statusVal[2]) is not ‘0’ GOTO step 5.
Note: If using the 4-wire interface, the oscillator
source, as selected by the Configuration
SetMode (6’b011111) Words, must be present to access the
Flash memory. In an unprogrammed
device, the oscillator source is the internal
FRC allowing for Flash memory access. If
SendCommand (MTAP_COMMAND) the Configuration Words have been
reprogrammed selecting an external
oscillator source then it must be present
for Flash memory access. See the
statusVal = XferData (MCHP_STATUS) “Special Features” chapter in the
specific device data sheet for details
regarding oscillator selection using the
Configuration Word settings.

8.2 2-wire Interface

No FCBUSY = 0
CFGRDY = 1 The following steps are required to check the device
status using the 2-wire interface:
1. SetMode (6’b011111) to force the Chip TAP
Yes controller into Run Test/Idle state.
2. SendCommand (MTAP_SW_MTAP).
Done
3. SetMode (6’b011111) to force the Chip TAP
controller into Run Test/Idle state.
4. SendCommand (MTAP_COMMAND).
5. statusVal = XferData (MCHP_STATUS).
6. If CFGRDY (statusVal[3]) is not ‘1’ and FCBUSY
(statusVal[2]) is not ‘0’, GOTO step 4.
Note: If the CFGRDY and FCBUSY bits do not
come to the proper state within 10 ms, the
sequence may have been executed
incorrectly or the device is damaged.

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 PIC32
9.0 ERASING THE DEVICE FIGURE 9-1: ERASE DEVICE
Before a device can be programmed, it must be
erased. The erase operation writes all ‘1s’ to the Flash Select MTAP
memory and prepares it to program a new set of data. SendCommand (MTAP_SW_MTAP)
Once a device is erased, it can be verified by
performing a “Blank Check” operation. See
Section 9.1 “Blank Check” for more information. SetMode (6’b011111)
The procedure for erasing program memory (Program,
boot, and Configuration memory) consists of selecting
the MTAP and sending the MCHP_ERASE command.
Put MTAP in Command Mode
The programmer must wait for the erase operation to
SendCommand (MTAP_COMMAND)
complete by reading and verifying bits in the
MCHP_STATUS value. Figure 9-1 illustrates the process
for performing a Chip Erase.
Issue Chip Erase Command
Note: The Device ID memory locations are read- XferData (MCHP_ERASE)
only and cannot be erased. Therefore,
Chip Erase has no effect on these memory
locations. XferData (MCHP_DE_ASSERT_RST)
Not required for PIC32MX Devices
The following steps are required to erase a target
device:
1. SendCommand (MTAP_SW_MTAP).
10 milliseconds Delay
2. SetMode (6’b011111).
3. SendCommand (MTAP_COMMAND).
4. XferData (MCHP_ERASE).
5. XferData (MCHP_DE_ASSERT_RST). This step is Read Erase Status
not required for PIC32MX devices. statusVal = XferData (MCHP_STATUS)
6. Delay 10 ms.
7. statusVal = XferData (MCHP_STATUS).
8. If CFGRDY (statusVal[3]) is not ‘1’ and FCBUSY No FCBUSY = 0
(statusVal[2]) is not ‘0’, GOTO to step 5. CFGRDY = 1
Note: The Chip Erase operation is a self-timed
operation. If the FCBUSY and CFGRDY Yes
bits do not set properly within the specified
Chip Erase time, the sequence may have Done
been executed incorrectly or the device is
damaged.

9.1 Blank Check

The term “Blank Check” implies verifying that the
device has been successfully erased and has no
programmed memory locations. A blank or erased
memory location always reads as ‘1’.
The device Configuration registers are ignored by the
Blank Check. Additionally, all unimplemented memory
space should be ignored from the Blank Check.

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PIC32
10.0 ENTERING SERIAL FIGURE 10-1: ENTERING SERIAL
EXECUTION MODE EXECUTION MODE

Before programming a device, it must be placed in Select MTAP

Serial Execution mode. The procedure for entering SendCommand (MTAP_SW_MTAP)
Serial Execution mode consists of verifying that the
device is not code-protected. If the device is code-
protected, a Chip Erase must be performed. See SetMode (6’b011111)
Section 9.0 “Erasing the Device” for details.

Put MTAP in Command Mode

SendCommand (MTAP_COMMAND)

Read Code-Protect Status

statusVal = XferData (MCHP_STATUS)

No Cannot Enter
CPS = 1
Must Erase First
Yes

Assert Reset
2-wire
XferData (MCHP_ASSERT_RST)

Select ETAP
SendCommand (MTAP_SW_ETAP)

SetMode (6’b011111)

Put CPU in Serial Exec Mode

SendCommand (ETAP_EJTAGBOOT)

Select MTAP Set MCLR High

SendCommand (MTAP_SW_MTAP)
4-wire

SetMode (6’b011111)

Put MTAP in Command Mode

SendCommand (MTAP_COMMAND)

Release Reset
XferData (MCHP_DE_ASSERT_RST)

Enable Flash
XferData (MCHP_FLASH_EN)
Required for PIC32MX devices

Select ETAP
SendCommand (MCHP_SW_ETAP)

SetMode (6’b011111)
2-wire

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 PIC32
10.1 4-wire Interface 10.2 2-wire Interface
The following steps are required to enter Serial The following steps are required to enter Serial
Execution mode: Execution mode:
Note: It is assumed that the MCLR pin has been 1. SendCommand (MTAP_SW_MTAP).
driven low from the previous Check 2. SetMode (6’b011111).
Device Status step (see Figure 8-1). 3. SendCommand (MTAP_COMMAND).
1. SendCommand (MTAP_SW_MTAP). 4. statusVal = XferData (MCHP_STATUS).
2. SetMode (6’b011111). 5. If CPS (statusVal[7]) is not ‘1’, the device must
3. SendCommand (MTAP_COMMAND). be erased first.
4. statusVal = XferData (MCHP_STATUS). 6. XferData (MCHP_ASSERT_RST).
5. If CPS (statusVal[7]) is not ‘1’, the device must 7. SendCommand (MTAP_SW_ETAP).
be erased first. 8. SetMode (6’b011111).
6. SendCommand (MTAP_SW_ETAP). 9. SendCommand (ETAP_EJTAGBOOT).
7. SetMode (6’b011111). 10. SendCommand (MTAP_SW_MTAP).
8. SendCommand (ETAP_EJTAGBOOT). 11. SetMode (6’b011111).
9. Set the MCLR pin high. 12. SendCommand (MTAP_COMMAND).
13. XferData (MCHP_DE_ASSERT_RST).
14. XferData (MCHP_FLASH_ENABLE). This step is
required for PIC32MX family devices.
15. SendCommand (MTAP_SW_ETAP).
16. SetMode (6’b011111).

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PIC32
11.0 DOWNLOADING THE Table 11-1 lists the steps that are required to download
the PE.
PROGRAMMING EXECUTIVE
(PE) TABLE 11-1: DOWNLOAD THE PE
OP CODES
The PE resides in RAM memory and is executed by the
CPU to program the device. The PE provides the Operation Operand
mechanism for the programmer to program and verify Step 1: PIC32MX devices only: Initialize BMXCON to
PIC32 devices using a simple command set and 0x1F0040. The instruction sequence executed by
communication protocol. There are several basic the PIC32 core is:
functions provided by the PE: lui a0,0xbf88
ori a0,a0,0x2000 /* address of BMXCON */
• Read memory lui a1,0x1f
• Erase memory ori a1,a1,0x40 /* a1 has 0x1f0040 */
• Program memory sw a1,0(a0) /* BMXCON initialized */
XferInstruction 0x3c04bf88
• Blank check
XferInstruction 0x34842000
• Read executive firmware revision
XferInstruction 0x3c05001f
• Get the Cyclic Redundancy Check (CRC) of Flash
XferInstruction 0x34a50040
memory locations
XferInstruction 0xac850000
The PE performs the low-level tasks required for Step 2: PIC32MX devices only: Initialize BMXDKPBA to
programming and verifying a device. This allows the 0x800. The instruction sequence executed by the
programmer to program the device by issuing the PIC32 core is:
appropriate commands and data. A detailed li a1,0x800
description for each command is provided in sw a1,16(a0)
Section 17.2 “The PE Command Set”. XferInstruction 0x34050800
The PE uses the device’s data RAM for variable XferInstruction 0xac850010
storage and program execution. After the PE has run, Step 3: PIC32MX devices only: Initialize BMXDUDBA
no assumptions should be made about the contents of and BMXDUPBA to the value of BMXDRMSZ.
data RAM. The instruction sequence executed by the PIC32
core is:
After the PE is loaded into the data RAM, the PIC32 lw a1,64(a0) /* load BMXDMSZ */
family can be programmed using the command set sw a1,32(a0)
shown in Table 17-1. sw a1,48(a0)
XferInstruction 0x8C850040
FIGURE 11-1: DOWNLOADING THE PE XferInstruction 0xac850020
XferInstruction 0xac850030
Step 4: Set up PIC32 RAM address for PE. The instruc-
tion sequence executed by the PIC32 core is:
Write the PE Loader to RAM
lui a0,0xa000
ori a0,a0,0x800
XferInstruction 0x3c04a000
XferInstruction 0x34840800
Load the PE Step 5: Load the PE_Loader. Repeat this step (Step 5)
until the entire PE_Loader is loaded in the PIC32
memory. In the operands field, “<PE_loader
hi++>” represents the MSbs 31 through 16 of the
PE loader op codes shown in Table 11-2. Like-
Loading the PE in the memory is a two step process: wise, “<PE_loader lo++>” represents the LSbs
1. Load the PE loader in the data RAM. (The PE 15 through 0 of the PE loader op codes shown in
loader loads the PE binary file in the proper Table 11-2. The “++” sign indicates that when
location of the data RAM, and when done, these operations are performed in succession,
the new word is to be transferred from the list of
jumps to the programming exec and starts
op codes of the LPE Loader shown in Table 11-2.
executing it.)
The instruction sequence executed by the PIC32
2. Feed the PE binary to the PE loader. core is:
lui a2, <PE_loader hi++>
ori a2,a2, <PE_loader lo++>
sw a2,0(a0)
addiu a0,a0,4
XferInstruction (0x3c06 <PE_loader hi++> )

DS60001145AA-page 28  2007-2021 Microchip Technology Inc.

 PIC32
TABLE 11-1: DOWNLOAD THE PE TABLE 11-2: PE LOADER OP CODES
OP CODES (CONTINUED) Op code Instruction
Operation Operand 0x24840004 addiu a0, a0, 4
XferInstruction (0x34c6 <PE_loader lo++> ) 0x1460fffb bnez v1, <here2>
XferInstruction 0xac860000 0x00000000 nop
XferInstruction 0x24840004 0x1000fff3 b <here1>
Step 6: Jump to the PE_Loader. The instruction 0x00000000 nop
sequence executed by the PIC32 core is:
here3:
lui t9,0xa000
ori t9,t9,0x800 0x3c02a000 lui v0, 0xa000
jr t9 0x34420900 ori v0, v0, 0x900
nop 0x00400008 jr v0
XferInstruction 0x3c19a000 0x00000000 nop
XferInstruction 0x37390800
XferInstruction 0x03200008
XferInstruction 0x00000000
Step 7: Load the PE using the PE_Loader. Repeat the
last instruction of this step (Step 7) until the entire
PE is loaded into the PIC32 memory. In this step,
you are given an Intel® Hex format file of the PE
that you will parse and transfer a number of 32-bit
words at a time to the PIC32 memory (refer to
Appendix B: “Hex File Format”). The instruction
sequence executed by the PIC32 is shown in
Table 11-2.
SendCommand ETAP_FASTDATA
XferFastData PE_ADDRESS (Address of PE
program block from PE Hex
file)
XferFastData PE_SIZE (Number of 32-bit
words of the program block
from PE Hex file)
XferFastData PE software op code from PE
Hex file (PE Instructions)
Step 8: Jump to the PE. Magic number (0xDEAD0000)
instructs the PE_Loader that the PE is completely
loaded into the memory. When the PE_Loader
sees the magic number, it jumps to the PE.
XferFastData 0x00000000
XferFastData 0xDEAD0000
TABLE 11-2: PE LOADER OP CODES
Op code Instruction
0x3c07dead lui a3, 0xdead
0x3c06ff20 lui a2, 0xff20
0x3c05ff20 lui al, 0xff20
herel:
0x8cc40000 lw a0, 0 (a2)
0x8cc30000 lw v1, 0 (a2)
0x1067000b beq v1, a3, <here3>
0x00000000 nop
0x1060fffb beqz v1, <here1>
0x00000000 nop
here2:
0x8ca20000 lw v0, 0 (a1)
0x2463ffff addiu v1, v1, -1
0xac820000 sw v0, 0 (a0)

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PIC32
12.0 DOWNLOADING A DATA 12.2 With the PE
BLOCK When using the PE, the steps in Section 12.0 “Down-
To program a block of data to the PIC32 device, it must loading a Data Block” and Section 14.0 “Initiating a
be loaded into SRAM. Flash Row Write” are handled in two single commands:
ROW_PROGRAM and PROGRAM.
12.1 Without the PE The ROW_PROGRAM command programs a single row of
Flash data, while the PROGRAM command programs
To program a block of memory without using the PE, multiple rows of Flash data. Both of these commands
the block of data must first be written to RAM. This are documented in Section 17.0 “The Programming
method requires the programmer to transfer the actual Executive”.
machine instructions with embedded (immediate) data
for writing the block of data to the devices internal RAM
memory.

FIGURE 12-1: DOWNLOADING DATA

WITHOUT THE PE

bufAddr = RAM Buffer Address

Write 32-bit Immediate

Data to bufAddr

Increment bufAddr

No
Done

The following steps are required to download a block of

data:
1. XferInstruction (op code).
2. Repeat Step 1 until the last instruction is
transferred to CPU.

TABLE 12-1: DOWNLOAD DATA OP

CODES
Op code Instruction
Step 1: Initialize SRAM Base Address to 0xA0000000.
3c10a000 lui s0, 0xA000;
Step 2: Write the entire row of data to be programmed
into system SRAM.
3c08<DATA> lui t0, <DATA(31:16)>;
3508<DATA> ori t0, t0, <DATA(15:0)>;
ae08<OFFSET> sw t0, <OFFSET>(s0);
// OFFSET increments by 4
Step 3: Repeat Step 2 until one row of data is loaded.

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 PIC32
13.0 INITIATING A PAGE ERASE PIC32MK family devices can perform an erase retry on
a page by increasing the internal voltage used to per-
An individual page may be erased rather than erasing form the erase.
all of Flash memory. The PE is not used in this case.

TABLE 13-1: PAGE ERASE

OP CODES
Op Code Instruction
Step 1: All PIC32 devices: Initialize constants. Registers a1, a2, and a3 are set for WREN = 1 or NVMOP[3:0] = 0100, WR = 1
and WREN = 1, respectively. Registers s1 and s2 are set for the unlock data values and s0 is initialized to ‘0’.
34054004 ori a1, $0,0x4004
34068000 ori a2,$0,0x8000
34074000 ori a3,$0,0x4000
3c11aa99 lui s1,0xaa99
36316655 ori s1,s1,0x6655
3c125566 lui s2,0x5566
365299aa ori s2,s2,0x99aa
3c100000 lui s0,0x0000
Step 2: PIC32MX family devices only: Set register a0 to the base address of the NVM register (0xBF80_F400).
3c04bf80 lui a0,0xbf80
3484f400 ori a0,a0,0xf400
Step 3: PIC32MK and PIC32MZ family devices only: Set register a0 to the base address of the NVM register (0xBF80_0600).
Register s3 is set for the value used to disable write protection in NVMBPB.
3c04b480 lui a0,0xbf80
34840600 ori a0,a0,0x0600
34138080 ori s3,$0,0x8080
Step 4: PIC32MK and PIC32MZ family devices only: Unlock and disable Boot Flash write protection.
ac910010 sw s1,16(a0)
ac920010 sw s2,16(a0)
ac930090 sw s3,144(a0)
00000000 nop
Step 5: PIC32MK family devices only: Save the contents of NVMCON2.
8c9400a0 lw s4,160(a0)
Step 6: PIC32MK family devices only: Set the initial programming voltage level and enable page testing (unlock required).
36953000 ori s5,s4,0x3000
32b5fcff andi s5,s5,0xFCFF
here3:
ac910010 sw s1,16(a0)
ac920010 sw s2,16(a0)
ac860008 sw a2,8(a0)
ac9500a0 sw s5,160(a0)

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PIC32
TABLE 13-1: PAGE ERASE
OP CODES (CONTINUED)
Op Code Instruction
Step 7: All PIC32 devices: Set the NVMADDR register with the address of the Flash page to be erased.
3c08<ADDR> lui t0,<FLASH_PAGE_ADDR(31:16)>
3508<ADDR> ori t0,t0,<FLASH_PAGE_ADDR(15:0)>
ac880020 sw t0,32(a0)
Step 8: All PIC32 devices: Set up the NVMCON register for write operation.
ac850000 sw a1,0(a0)
delay (6 us)
Step 9: PIC32MX devices only: Poll the LVDSTAT register.
here1:
8c880000 lw t0,0(a0)
31080800 andi t0,t0,0x0800
1500fffd bne t0,$0,here1
00000000 nop
Step 10: All PIC32 devices: Unlock the NVMCON register and start the write operation.
ac910010 sw s1,16(a0)
ac920010 sw s2,16(a0)
ac860008 sw a2,8(a0)
Step 11: All PIC32 devices: Loop until the WR bit (NVMCON[15]) is clear.
here2:
8c880000 lw t0,0(a0)
01064024 and t0,t0,a2
1500fffd bne t0,$0,here2
00000000 nop
Step 12: All PIC32 devices: Wait at least 500 ns after the WR bit (NVMCON[15]) clears before writing to any of the NVM registers.
This requires inserting a delay in the execution. The programming tools and program executive utilizes the FRC 8 MHz
clock. Therefore four NOP instructions equate to 500 ns (see Note 1).
00000000 nop
00000000 nop
00000000 nop
00000000 nop
Step 13: All PIC32 devices: Clear the WREN bit (NVMCON[14]).
ac870004 sw a3,4(a0)

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 PIC32
TABLE 13-1: PAGE ERASE
OP CODES (CONTINUED)
Op Code Instruction
Step 14: PIC32MK family devices only: Check that all data in the page has been erased. If not, adjust the voltage and try again. If
all voltages levels have been tried, fail, and go to error procedure.
ac870004 sw a3, 4(a0)
20171000 addi s7, $0, 4096
00005020 add t2, $0, $0
8c880020 lw t0, 32(a0)
01194020 add t0, t0, t9
here5:
8d090000 lw t1, 0(t0)
15200005 bne t1, $0, here6
214a0010 addi t2, t2, 16
11570009 beq t2, s7, here7
00000000 nop
1000fffa beq $0, $0, here5
21080010 addi t0, t0, 16
here6:
22b50100 addi s5, s5, 256
32b60300 andi s6, s5, 768
16c0ffde bne s6, $0, here3
00000000 nop
10000005 beq $0, $0, err_proc
00000000 nop
Step 15: PIC32MK family devices only: Restore the NVMCON2 register.
here7:
ac9400a0 sw s4,160(a0)
Step 16: All PIC32 devices: Check the WRERR bit (NVMCON[13]) to ensure that the program sequence has completed success-
fully. If an error occurs, jump to the error processing routine.
8c880000 lw t0,0(a0)
30082000 andi t0,t0,0x2000
1500<ERR_PROC> bne t0,$0,<err_proc_offset>
00000000 nop

Note 1: For programming the Flash at runtime in the users application, the following code is recommended:

while(NVMCON.WR) // waitfor WR bit(NVMCON[15]) to clear

{};
{
unsigned int start_count = _CP0_GET_COUNT();
unsigned int total_count = (.00000025 * SYSCLK); //count for 500 ns and CPU
frequency in MHz
while ((_CP0_GET_COUNT()- start_count) < total_count);
}

 2007-2021 Microchip Technology Inc. DS60001145AA-page 33

PIC32
14.0 INITIATING A FLASH ROW 14.2 Without the PE
WRITE Flash memory write operations are controlled by the
NVMCON register. Programming is performed by
Note: Certain PIC32 devices have available setting the NVMCON register to select the type of write
ECC memory. When the ECC feature is operation and initiating the programming sequence by
used, the Flash memory must be setting the WR control bit (NVMCON[15]).
programmed in groups of four 32-bit
words using four, 32-bit word alignment. If FIGURE 14-1: INITIATING FLASH WRITE
ECC is dynamically used, the WITHOUT THE PE
programming method determines when
the feature is used. ECC is not enabled
for words programmed with the single Unprotect Control Registers
word programming command. ECC is
enabled for words programmed in groups
of four, either with the quad word or row Select Write Operation
programming commands. Failure to
adhere to these methods can result in
ECC DED errors during run-time. Refer to
Load Addresses in NVM Registers
the specific device data sheet for details
regarding ECC use and configuration.

Once a row of data has been downloaded into the Unlock Flash Controller
device’s SRAM, the programming sequence must be
initiated to write the block of data to the Flash memory.
Start Operation
See Table 14-1 for the op code and instructions for
initiating a Flash row write.
Done
14.1 With the PE
When using the PE, the data is immediately written to
the Flash memory from the SRAM. No further action is In the Flash write procedure (see Table 14-1), the Row
required. Programming method is used to program the Flash
memory, as it is typically the most expedient. word and
Quad Word programming methods are also available,
depending on the device, and may be used or required
depending on your application. Refer to the “Flash
Program Memory” chapter in the specific device data
sheet and the related section of the “PIC32 Family
Reference Manual” for more information.
The following steps are required to initiate a Flash
write:
1. XferInstruction (op code).
2. Repeat Step 1 until the last instruction is
transferred to the CPU.

DS60001145AA-page 34  2007-2021 Microchip Technology Inc.

 PIC32
TABLE 14-1: INITIATE FLASH ROW WRITE OP CODES
Op Code Instruction
Step 1: All PIC32 devices: Initialize constants. Registers a1, a2, and a3 are set for WREN = 1 or NVMOP[3:0] = 0011, WR = 1
and WREN = 1, respectively. Registers s1 and s2 are set for the unlock data values and s0 is initialized to ‘0’.
34054003 ori a1,$0,0x4003
34068000 ori a2,$0,0x8000
34074000 ori a3,$0,0x4000
3c11aa99 lui s1,0xaa99
36316655 ori s1,s1,0x6655
3c125566 lui s2,0x5566
365299aa ori s2,s2,0x99aa
3c100000 lui s0,0x0000
Step 2: PIC32MX devices only: Set register a0 to the base address of the NVM register (0xBF80_F400).
3c04bf80 lui a0,0xbf80
3484f400 ori a0,a0,0xf400
Step 2: PIC32MK and PIC32MZ family devices only: Set register a0 to the base address of the NVM register (0xBF80_0600).
Register s3 is set for the value used to disable write protection in NVMBPB.
3c04bf80 lui a0,0xbf80
34840600 ori a0,a0,0x0600
34138080 ori s3,$0,0x8080
Step 3: PIC32MK and PIC32MZ family devices only: Unlock and disable Boot Flash write protection.
ac910010 sw s1,16(a0)
ac920010 sw s2,16(a0)
ac930090 sw s3,144(a0)
00000000 nop
Step 4: All PIC32 devices: Set the NVMADDR register with the address of the Flash row to be programmed.
3c08<ADDR> lui t0,<FLASH_ROW_ADDR(31:16)>
3508<ADDR> ori t0,t0,<FLASH_ROW_ADDR(15:0)>
ac880020 sw t0,32(a0)
Step 5: PIC32MX devices only: Set the NVMSRCADDR register with the physical source SRAM address (offset is 64).
3c10<ADDR> lui s0, <RAM_ADDR(31:16)>
3610<ADDR> ori s0,s0,<RAM_ADDR(15:0)>
ac900040 sw s0,64(a0)
Step 5: PIC32MK and PIC32MZ family devices only: Set the NVMSRCADDR register with the physical source SRAM address
(offset is 112).
3c10<ADDR> lui s0, <RAM_ADDR(31:16)>
3610<ADDR> ori s0,s0,<RAM_ADDR(15:0)>
ac900070 sw s0,112(a0)
Step 6: All PIC32 devices: Set up the NVMCON register for write operation.
ac850000 sw a1,0(a0)
delay (6 μs)

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PIC32
TABLE 14-1: INITIATE FLASH ROW WRITE OP CODES (CONTINUED)
Op Code Instruction
Step 7: PIC32MX devices only: Poll the LVDSTAT register.
here1:
8C880000 lw t0,0(a0)
31080800 andi t0,t0,0x0800
1500fffd bne t0,$0,here1
00000000 nop
Step 8: All PIC32 devices: Unlock the NVMCON register and start the write operation.
ac910010 sw s1,16(a0)
ac920010 sw s2,16(a0)
ac860008 sw a2,8(a0)
Step 9: All PIC32 devices: Loop until the WR bit (NVMCON[15]) is clear.
here2:
8c880000 lw t0,0(a0)
01064024 and t0,t0,a2
1500fffd bne t0,$0,here2
00000000 nop
Step 10: All PIC32 devices: Wait at least 500 ns after the WR bit (NVMCON[15]) clears before writing to any of the NVM registers.
This requires inserting a delay in the execution. The programming tools and program executive utilizes the FRC 8 MHz
clock. Therefore four NOP instructions equate to 500 ns (see Note 1).
00000000 nop
00000000 nop
00000000 nop
00000000 nop
Step 11: All PIC32 devices: Clear the WREN bit (NVMCONM[14]).
ac870004 sw a3,4(a0)
Step 12: All PIC32 devices: Check the WRERR bit (NVMCON[13]) to ensure that the program sequence has completed
successfully. If an error occurs, jump to the error processing routine.
8c880000 lw t0,0(a0)
30082000 andi t0,zero,0x2000
1500<ERR_PROC> bne t0, $0, <err_proc_offset>
00000000 nop
Note 1: For programming the Flash at runtime in the users application, the following code is recom-
mended:
while(NVMCON.WR) //Wait for WR bit (NVMCON[15]) to clear
{};
{
unsigned int start_count = _CP0_GET_COUNT();
unsigned int total_count = (.00000025 * SYSCLK); //count for 500 ns and CPU
frequency in MHz
while ((_CP0_GET_COUNT()- start_count) < total_count);
}

DS60001145AA-page 36  2007-2021 Microchip Technology Inc.

 PIC32
15.0 VERIFY DEVICE MEMORY 15.2 Verifying Memory without the PE
The verify step involves reading back the code memory Reading from the Flash memory is performed by exe-
space and comparing it with the copy held in the cuting a series of read accesses from the Fastdata reg-
programmer’s buffer. The Configuration registers are ister. Table 20-4 shows the EJTAG programming
verified with the rest of the code. details, including the address and op code data for per-
forming processor access operations.
Note: Because the Configuration registers
include the device code protection bit,
FIGURE 15-2: VERIFYING MEMORY
code memory should be verified immedi-
ately after writing (if code protection is WITHOUT THE PE
enabled). This is because the device will
not be readable or verifiable if a device Read Memory Location
Reset occurs after the code-protect bit using ReadFromAddress
has been cleared. Pseudo Operation

15.1 Verifying Memory with the PE

Memory verify is performed using the GET_CRC Verify Location
command. Table 17-2 lists the op codes and
instructions.

FIGURE 15-1: VERIFYING MEMORY

WITH THE PE No
Done

Issue Verify Command

The following steps are required to verify memory:

1. XferInstruction (op code).
Receive Response
2. Repeat Step 1 until the last instruction is
transferred to the CPU.
3. Verify that valRead matches the copy held in the
programmer’s buffer.
The following steps are required to verify memory using
4. Repeat Steps 1-3 for each memory location.
the PE:
1. XferFastData (GET_CRC). TABLE 15-1: VERIFY DEVICE OP CODES
2. XferFastData (start_Address).
Op code Instruction
3. XferFastData (length).
Step 1: Initialize some constants.
4. valCkSum = XferFastData (32’h0x00).
3c13ff20 lui s3, 0xFF20
Verify that valCkSum matches the checksum of the
copy held in the programmer’s buffer. Step 2: Read memory Location.
3c08<ADDR> lui t0,<FLASH_WORD_ADDR(31:16)>
3508<ADDR> ori t0, t0, <FLASH_WORD_ADDR(15:0)>
Step 3: Write to Fastdata location.
8d090000 lw t1, 0(t0)
ae690000 sw t1, 0(s3)
Step 4: Read data from Fastdata register 0xFF200000.
Step 5: Repeat Steps 2-4 until all configuration locations
are read.

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PIC32
16.0 EXITING PROGRAMMING 16.2 2-wire Interface
MODE Exiting programming mode is done by removing VIH
Once a device is programmed, it must be taken out of from the MCLR pin, as illustrated in Figure 16-2. The
programming mode to start proper execution of its new only requirement for exit is that an interval, P16, should
program memory contents. elapse between the last clock and program signals on
PGECx and PGEDx before removing VIH.
16.1 4-wire Interface
FIGURE 16-2: 2-WIRE EXIT
Exiting programming mode is done by removing VIH PROGRAMMING MODE
from the MCLR pin, as illustrated in Figure 16-1. The
P16 P17
only requirement for exit is that an interval, P16, should
elapse between the last clock and program signals VIH
MCLR
before removing VIH.
VDD/VDDIO
FIGURE 16-1: 4-WIRE EXIT
VIH
PROGRAMMING MODE PGEDx

P16 PGECx
MCLR
PGEDx = Input
VDD/VDDIO

TCK Use the following steps to exit programming mode:

TMS 1. SetMode (5’b11111).
‘1’ ‘1’ ‘0’
2. Assert the MCLR pin.
TDI 3. Issue a clock pulse on PGECx.
TDO 4. Remove power (if the device is powered).

The following steps are required to exit programming

mode:
1. SetMode (5’b11111).
2. Assert the MCLR pin.
3. Remove power (if the device is powered).

DS60001145AA-page 38  2007-2021 Microchip Technology Inc.

 PIC32
17.0 THE PROGRAMMING EXAMPLE 17-1: GetPEResponse EXAMPLE
EXECUTIVE WORD GetPEResponse()
{
Note: The Programming Executive (PE) is WORD response;
included with your installation of MPLAB X
// Wait until CPU is ready
IDE. To download the appropriate PE file
SendCommand(ETAP_CONTROL);
for your device, please visit the related
product page on the Microchip web site // Check if Proc. Access bit (bit 18) is set
(www.microchip.com). do {
controlVal=XferData(32’h0x0004C000 );
} while(PrAcc(contorlVal[18]) is not ‘1’ );
17.1 PE Communication
The programmer and the PE have a master-slave // Select Data Register
relationship, where the programmer is the master SendCommand(ETAP_DATA);
programming device and the PE is the slave.
// Receive Response
All communication is initiated by the programmer in the response = XferData(0);
form of a command. The PE is able to receive only one
command at a time. Correspondingly, after receiving // Tell CPU to execute instruction
and processing a command, the PE sends a single SendCommand(ETAP_CONTROL);
response to the programmer. XferData(32’h0x0000C000);

// return 32-bit response

17.1.1 2-WIRE ICSP EJTAG RATE
return response;
In Enhanced ICSP mode, the PIC32 family devices }
operate from the internal Fast RC oscillator, which has
a nominal frequency of 8 MHz. The typical communication sequence between the
programmer and the PE is shown in Table 17-1.
17.1.2 COMMUNICATION OVERVIEW The sequence begins when the programmer sends the
The programmer and the PE communicate using the command and optional additional data to the PE, and
EJTAG Address, Data and Fastdata registers. In partic- the PE carries out the command.
ular, the programmer transfers the command and data When the PE has finished executing the command, it
to the PE using the Fastdata register. The programmer sends the response back to the programmer.
receives a response from the PE using the Address
and Data registers. The pseudo operation of receiving The response may contain more than one response.
a response is shown in the GetPEResponse pseudo For example, if the programmer sent a READ
operation below: command, the response will contain the data read.
Format:
TABLE 17-1: COMMUNICATION
response = GetPEResponse()
SEQUENCE FOR THE PE
Purpose:
Enables the programmer to receive the 32-bit Operation Operand
response value from the PE. Step 1: Send command and optional data from
programmer to the PE.
XferFastData (Command | data len)
XferFastData.. optional data..
Step 2: Programmer reads the response from the PE.
GetPEResponse response
GetPEResponse... response...

 2007-2021 Microchip Technology Inc. DS60001145AA-page 39

PIC32
17.2 The PE Command Set FIGURE 17-1: COMMAND FORMAT
Table 17-2 provides PE command set details, such 31 16
as op code, mnemonic and short description for Op code
each command. Functional details on each
15 0
command are provided in Section 17.2.3
“ROW_PROGRAM Command” through Operand (optional)
Section 17.2.14 “CHANGE_CFG Command”. 31 16
The PE sends a response to the programmer for each Command Data High (if required)
command that it receives. The response indicates if the 15 0
command was processed correctly. It includes any
required response data or error data. Command Data Low (if required)

17.2.1 COMMAND FORMAT The command in the op code field must match one of
the commands in the command set that is listed in
All PE commands have a general format consisting of Table 17-2. Any command received that does not
a 32-bit header and any required data for the match a command the list returns a NACK response,
command, see Figure 17-1. The 32-bit header consists as shown in Table 17-3.
of a 16-bit op code field, which is used to identify the
command, and a 16-bit command Operand field. Use The PE uses the command Operand field to determine
of the Operand field varies by command. the number of bytes to read from or to write to. If the
value of this field is incorrect, the command is not be
Note: Some commands have no Operand properly received by the PE.
information; however, the Operand field
must be sent and the programming
executive will ignore the data.

TABLE 17-2: PE COMMAND SET

Op code Mnemonic Description
0x0 ROW_PROGRAM(1) Program one row of Flash memory at the specified address
0x1 READ Read N 32-bit words of memory starting from the specified address (N < 65,536)
0x2 PROGRAM Program Flash memory starting at the specified address
0x3 WORD_PROGRAM(3) Program one word of Flash memory at the specified address
0x4 CHIP_ERASE Chip Erase of entire chip
0x5 PAGE_ERASE Erase pages of code memory from the specified address
0x6 BLANK_CHECK Blank Check code
0x7 EXEC_VERSION Read the PE software version
0x8 GET_CRC Get the CRC of Flash memory
0x9 PROGRAM_CLUSTER Programs the specified number of bytes to the specified address
0xA GET_DEVICEID Returns the hardware ID of the device
0xB CHANGE_CFG(2) Used by the probe to set various configuration settings for the PE
0xC GET_CHECKSUM Get the checksum of Flash memory
0xD QUAD_WORD_PGRM(4) Program four words of Flash memory at the specified address
Note 1: Refer to Table 5-1 for the row size for each device.
2: This command is not available in PIC32MX1XX/2XX devices.
3: On the PIC32MZ family devices, which incorporate ECC, the WORD_PROGRAM command will not generate
the ECC parity bits. Reading a location programmed with the WORD_PROGRAM command with ECC enabled
will cause a DED fault.
4: This command is available on PIC32MK and PIC32MZ family devices only.

DS60001145AA-page 40  2007-2021 Microchip Technology Inc.

 PIC32
17.2.2 RESPONSE FORMAT 17.2.3 ROW_PROGRAM COMMAND
The PE response set is shown in Table 17-3. All PE The ROW_PROGRAM command instructs the PE to
responses have a general format consisting of a 32-bit program a row of data at a specified address.
header and any required data for the response (see The data to be programmed to memory, located in
Figure 17-2). command words Data_1 through Data_N, must be
arranged using the packed instruction word format
FIGURE 17-2: RESPONSE FORMAT provided in Table 17-4 (this command expects an
31 16 entire row of data).
Last Command FIGURE 17-3: ROW_PROGRAM COMMAND
15 0 31 16
Response Code Op code
31 16 15 0
Data_High_1
Operand
15 0
31 16
Data_Low_1
Addr_High
31 16
15 0
Data_High_N
Addr_Low
15 0
31 16
Data_Low_N
Data_High_1
15 0
17.2.2.1 Last_Cmd Field
Data_Low_1
Last_Cmd is a 16-bit field in the first word of the
31 16
response and indicates the command that the PE
processed. It can be used to verify that the PE correctly Data_High_N
received the command that the programmer 15 0
transmitted. Data_Low_N
17.2.2.2 Response Code
TABLE 17-4: ROW_PROGRAM FORMAT
The response code indicates whether the last
command succeeded or failed, or if the command is a Field Description
value that is not recognized. The response code values
Op code 0x0
are shown in Table 17-3.
Operand Not used
TABLE 17-3: RESPONSE VALUES Addr_High High 16 bits of 32-bit destination
Op code Mnemonic Description address
Addr_Low Low 16 bits of 32-bit destination
0x0 PASS Command successfully
address
processed
Data_High_1 High 16 bits data word 1
0x2 FAIL Command unsuccessfully
processed Data_Low_1 Low 16 bits data word 1
0x3 NACK Command not known Data_High_N High 16 bits data word 2 through N
Data_Low_N Low 16 bits data word 2 through N
17.2.2.3 Optional Data
The response header may be followed by optional data Expected Response (1 word):
in case of certain commands such as read. The
number of 32-bit words of optional data varies FIGURE 17-4: ROW_PROGRAM RESPONSE
depending on the last command operation and its 31 16
parameters.
Last Command
15 0
Response Code

 2007-2021 Microchip Technology Inc. DS60001145AA-page 41

PIC32
17.2.4 READ COMMAND 17.2.5 PROGRAM COMMAND
The READ command instructs the PE to read from The PROGRAM command instructs the PE to program
memory. The number of 32-bit words specified in the the Flash memory, including Configuration Words,
Operand field starting from the 32-bit address specified starting from the 32-bit address specified in the
by the Addr_Low and Addr_High fields. This command Addr_Low and Addr_High fields. A 32-bit length field
can be used to read Flash memory and Configuration specifies the number of bytes to program.
Words. All data returned in response to this command The address must be aligned to a Flash row size
uses the packed data format that is provided in boundary and the length must be a multiple of a Flash
Table 17-5. row size. See Table 5-1 for the correct row size for the
device to be programmed.
FIGURE 17-5: READ COMMAND
31 16 FIGURE 17-7: PROGRAM COMMAND
Op code 31 16
15 0 Op code
Operand 15 0
31 16 Operand
Addr_High 31 16
15 0 Addr_High
Addr_Low 15 0
Addr_Low
TABLE 17-5: READ FORMAT
31 16
Field Description Length_High
Op code 0x1 15 0
Operand N number of 32-bit words to read Length_Low
(maximum of 65,535) 31 16
Addr_Low Low 16 bits of 32-bit source address Data_High_1
Addr_High High 16 bits of 32-bit source 15 0
address Data_Low_1

Expected Response: 31 16
Data_High_N
FIGURE 17-6: READ RESPONSE 15 0
31 16 Data_Low_N
Last Command
15 0 TABLE 17-6: PROGRAM FORMAT
Response Code Field Description
31 16 Op code 0x2
Data_High_1
Operand Not used
15 0
Addr_Low Low 16 bits of 32-bit destination
Data_Low_1 address
31 16 Addr_High High 16 bits of 32-bit destination
Data_High_N address
15 0 Length_Low Low 16 bits of Length
Data_Low_N Length_High High 16 bits Length
Data_Low_N Low 16 bits data word 2 through N
Note: Reading unimplemented memory will Data_High_N High 16 bits data word 2 through N
cause the PE to Reset. Ensure that only
memory locations present on a particular
device are accessed.

DS60001145AA-page 42  2007-2021 Microchip Technology Inc.

 PIC32
The following are three programming scenarios: If the PE encounters an error in programming any of
• The length of the data to be programmed is the the blocks, it sends a failure status to the probe and
size of a single Flash row aborts the PROGRAM command. On receiving the failure
status, the probe must stop sending data. The PE will
• The length of the data to be programmed is the
not process any other data for this command from the
size of two Flash rows
probe. The process is illustrated in Figure 17-9.
• The length of the data to be programmed is larger
than the size of two Flash rows Note: If the PROGRAM command fails, the
programmer should read the failing row
When the data length is equal to 512 bytes, the PE
using the READ command from the Flash
receives the 512-byte block of data from the probe and
memory. Then the programmer should
immediately sends the response for this command
compare the row received from the Flash
back to the probe.
memory to its local copy, word-by-word, to
The PE will respond for each row of data that it determine the address where Flash
receives. If the data length of the command is equal to programming fails.
a single row, a single PE response is generated. If the
data length is equal to two rows, the PE waits to The response for this command is a little different than
receive both rows of data, then sends back-to-back the response for other commands. The 16 MSbs of the
responses for each data row. If the data length is response contain the 16 LSbs of the destination
greater than two rows of data, the PE will send the address, where the last block is programmed. This
response for the first row after receiving the first two helps the probe and the PE maintain proper
rows of data. Subsequent responses are sent after synchronization of sending and receiving data and
receiving subsequent data row packets. The responses.
responses will lag the data by one row. When the last
row of data is received, the PE will respond with back- Expected Response (1 word):
to-back responses for the second-to-last data row
followed by the last row. FIGURE 17-8: PROGRAM RESPONSE
31 16
LSB 16 bits of the destination address of last block
15 0
Response Code

 2007-2021 Microchip Technology Inc. DS60001145AA-page 43

PIC32
FIGURE 17-9: PROGRAM COMMAND ALGORITHM

Start

Data is Data is Data

equal to a equal to is larger than
single row two rows two rows

Send one row Send first row Send first row

of data of data of data

Receive status
(LSB 16 bits of Send second row Send second row
Destination Address of data of data
Status Value)

Receive status Receive status

for Row 1 for Row 1

Receive status Send third row

for Row 2 of data

Receive status
for Row 2

Send Nth row

of data

Receive status
for Row N-1

Receive status
for Row N

Done

DS60001145AA-page 44  2007-2021 Microchip Technology Inc.

 PIC32
17.2.6 WORD_PROGRAM COMMAND 17.2.7 CHIP_ERASE COMMAND
The WORD_PROGRAM command instructs the PE to The CHIP_ERASE command erases the entire chip,
program a 32-bit word of data at the specified address. including the configuration block.
After the erase is performed, the entire Flash memory
FIGURE 17-10: WORD_PROGRAM contains 0xFFFFFFFF.
COMMAND
31 16
FIGURE 17-12: CHIP_ERASE COMMAND
Op code
31 16
15 0
Op code
Operand
15 0
31 16
Operand
Addr_High
15 0
TABLE 17-8: CHIP_ERASE FORMAT
Addr_Low
31 16 Field Description
Data_High Op code 0x4
15 0 Operand Not used
Data_Low Addr_Low Low 16 bits of 32-bit destination
address
TABLE 17-7: WORD_PROGRAM FORMAT Addr_High High 16 bits of 32-bit destination
Field Description address

Op code 0x3 Expected Response (1 word):

Operand Not used
Addr_High High 16 bits of 32-bit destination FIGURE 17-13: CHIP_ERASE RESPONSE
address 31 16
Addr_Low Low 16 bits of 32-bit destination Last Command
address 15 0
Data_High High 16 bits data word Response Code
Data_Low Low 16 bits data word

Expected Response (1 word):

FIGURE 17-11: WORD_PROGRAM

RESPONSE
31 16
Last Command
15 0
Response Code

 2007-2021 Microchip Technology Inc. DS60001145AA-page 45

PIC32
17.2.8 PAGE_ERASE COMMAND 17.2.9 BLANK_CHECK COMMAND
The PAGE_ERASE command erases the specified The BLANK_CHECK command queries the PE to
number of pages of code memory from the specified determine whether the contents of code memory and
base address. Depending on the device, the specified code-protect Configuration bits (GCP and GWRP) are
base address must be a multiple of 0x400 or 0x100. blank (contains all ‘1’s).
After the erase is performed, all targeted words of code
memory contain 0xFFFFFFFF. FIGURE 17-16: BLANK_CHECK COMMAND
31 16
FIGURE 17-14: PAGE_ERASE COMMAND Op code
31 16 15 0
Op code Operand
15 0 31 16
Operand Addr_High
31 16 15 0
Addr_High Addr_Low
15 0 31 16
Addr_Low Length_High
15 0
TABLE 17-9: PAGE_ERASE FORMAT
Length_Low
Field Description
TABLE 17-10: BLANK_CHECK FORMAT
Op code 0x5
Operand Number of pages to erase Field Description
Addr_Low Low 16 bits of 32-bit destination Op code 0x6
address
Operand Not used
Addr_High High 16 bits of 32-bit destination
address Address Address where to start the Blank
Check
Expected Response (1 word): Length Number of program memory locations
to check in terms of bytes
FIGURE 17-15: PAGE_ERASE RESPONSE
Expected Response (1 word for blank device):
31 16
Last Command
FIGURE 17-17: BLANK_CHECK RESPONSE
15 0 31 16
Response Code Last Command
15 0
Response Code

DS60001145AA-page 46  2007-2021 Microchip Technology Inc.

 PIC32
17.2.10 EXEC_VERSION COMMAND 17.2.11 GET_CRC COMMAND
EXEC_VERSION queries for the version of the PE GET_CRC calculates the CRC of the buffer from the
software stored in RAM. specified address to the specified length, using the
table look-up method. The CRC details are as follows:
FIGURE 17-18: EXEC_VERSION • CRC-CCITT, 16-bit
COMMAND • Polynomial: X^16+X^12+X^5+1, hex 0x00011021
31 16 • Seed: 0xFFFF
Op code • Most Significant Byte (MSB) shifted in first
15 0 Note 1: In the response, only the CRC Least
Significant 16 bits are valid.
Operand
2: The PE will automatically determine if the
hardware CRC is available and use it by
TABLE 17-11: EXEC_VERSION FORMAT default. The hardware CRC is not used
Field Description on PIC32MX1XX/2XX devices.

Op code 0x7 FIGURE 17-20: GET_CRC COMMAND

Operand Not used 31 16
Op code
Expected Response (1 word): 15 0
Operand
FIGURE 17-19: EXEC_VERSION
RESPONSE 31 16
31 16 Addr_High
Last Command 15 0
15 0 Addr_Low
Version Number 31 16
Length_High
15 0
Length_Low

TABLE 17-12: GET_CRC FORMAT

Field Description

Op code 0x8
Operand Not used
Address Address where to start calculating the
CRC
Length Length of buffer on which to calculate
the CRC, in number of bytes

Expected Response (2 words):

FIGURE 17-21: GET_CRC RESPONSE

31 16
Last Command
15 0
Response Code
31 16
CRC_High
15 0
CRC_Low

 2007-2021 Microchip Technology Inc. DS60001145AA-page 47

PIC32
17.2.12 PROGRAM_CLUSTER COMMAND 17.2.13 GET_DEVICEID COMMAND
PROGRAM_CLUSTER programs the specified number of The GET_DEVICEID command returns the hardware
bytes to the specified address. The address must be ID of the device.
32-bit aligned, and the number of bytes must be a
multiple of a 32-bit word. FIGURE 17-24: GET_DEVICEID
COMMAND
FIGURE 17-22: PROGRAM_CLUSTER 31 16
COMMAND
Op code
31 16
15 0
Op code
Operand
15 0
Operand TABLE 17-14: GET_DEVICEID FORMAT
31 16 Field Description
Addr_High
Op code 0xA
15 0
Operand Not used
Addr_Low
31 16 Expected Response (1 word):
Length_High
FIGURE 17-25: GET_DEVICEID
15 0
RESPONSE
Length_Low 31 16
Last Command
TABLE 17-13: PROGRAM_CLUSTER FORMAT
15 0
Field Description
Device ID
Op code 0x9
Operand Not used
Address Start address for programming
Length Length of area to program in number
of bytes

Note: If the PROGRAM_CLUSTER command fails,

the programmer should read the failing row
using the READ command from the Flash
memory. Then the programmer should
compare the row received from the Flash
memory to its local copy word-by-word to
determine the address where Flash
programming fails.

Expected Response (1 word):

FIGURE 17-23: PROGRAM_CLUSTER

RESPONSE
31 16
Last Command
15 0
Response Code

DS60001145AA-page 48  2007-2021 Microchip Technology Inc.

 PIC32
17.2.14 CHANGE_CFG COMMAND 17.2.15 GET_CHECKSUM COMMAND
CHANGE_CFG is used by the probe to set various GET_CHECKSUM returns the sum of all the bytes
configuration settings for the PE. Currently, the single starting at the address argument up to the length
configuration setting determines which of the following argument. The result is a 32-bit word.
calculation methods the PE should use:
• Software CRC calculation method FIGURE 17-28: CHANGE_CFG COMMAND
• Hardware calculation method 31 16
Op code
FIGURE 17-26: CHANGE_CFG COMMAND 15 0
31 16
Operand
Op code
31 16
15 0
Addr_High
Operand
15 0
31 16
Addr_Low
CRCFlag_High
31 16
15 0
Length_High
CRCFlag_Low
15 0

TABLE 17-15: CHANGE_CFG FORMAT Length_Low

Field Description TABLE 17-16: GET_CHECKSUM FORMAT

Op code 0xB Field Description
Operand Not used
Op code 0x0C
CRCFlag If the value is ‘0’, the PE uses the
Operand Not used
software CRC calculation method.
If the value is ‘1’, the PE uses the Addr_High High-order 16 bits of the 32-bit starting
hardware CRC unit to calculate the address of the data to calculate the
CRC. checksum for.
Addr_Low Low-order 16 bits of the 32-bit starting
Expected Response (1 word): address of the data to calculate the
checksum for.
FIGURE 17-27: CHANGE_CFG RESPONSE
Length_High High-order 16 bits of the 32-bit length
31 16 of data to calculate the checksum for
Last Command in bytes.
15 0 Length_Low Low-order 16 bits of the 32-bit length
of data to calculate the checksum for
Response Code
in bytes.

Expected Response (1 word):

Note: The CHANGE_CFG command is not
available in PIC32MX1XX/2XX devices.
FIGURE 17-29: GET_CHECKSUM
RESPONSE
31 16
Last Command
15 0
Response Code
31 16
Checksum_High
15 0
Checksum_Low

 2007-2021 Microchip Technology Inc. DS60001145AA-page 49

PIC32
17.2.16 QUAD_WORD_PROGRAM COMMAND TABLE 17-17: QUAD_WORD_PROGRAM
QUAD_WORD_PROGRAM instructs the PE to program FORMAT
four, 32-bit words at the specified address. The Data2_High High-order 16 bits of data word 2.
address must be an aligned four word boundary (bits 0-
1 must be ‘0’). If not, the command will return a FAIL Data2_Low Low-order 16 bits of data word 2.
response value and no data will be programmed. Data3_High High-order 16 bits of data word 3.
Data3_Low Low-order 16 bits of data word 3.
FIGURE 17-30: QUAD_WORD_PROGRAM
COMMAND Expected Response (1 word):
31 16
Op code FIGURE 17-31: QUAD_WORD_PROGRAM
RESPONSE
15 0
31 16
Operand
Last Command
31 16
15 0
Addr_High
Response Code
15 0
Addr_Low
31 16
Data0_High
15 0
Data0_Low
31 16
Data1_High
15 0
Data1_Low
31 16
Data2_High
15 0
Data2_Low
31 16
Data3_High
15 0
Data3_Low

TABLE 17-17: QUAD_WORD_PROGRAM

FORMAT
Field Description
Op code 0x0D
Operand Not used
Addr_High High-order 16 bits of the 32-bit starting
address.
Addr_Low Low -order 16 bits of the 32-bit starting
address.
Data0_High High-order 16 bits of data word 0.
Data0_Low Low-order 16 bits of data word 0.
Data1_High High-order 16 bits of data word 1.
Data1_Low Low-order 16 bits of data word 1.

DS60001145AA-page 50  2007-2021 Microchip Technology Inc.

 PIC32
17.2.17 QUAD_DOUBLE_WORD_PROGRAM Data6_Low
COMMAND
31 16
QUAD_DOUBLE_WORD_PROGRAM instructs the PE to
Data7_High
program four, 64-bit words at the specified address.
The address must be an aligned four word boundary 15 0
(bits 0-1 must be ‘0’). If not, the command will return a Data7_Low
FAIL response value and no data will be programmed.
TABLE 17-18: QUAD_DOUBLE_WORD_PROGRAM
FIGURE 17-32: QUAD_DOUBLE_WORD_PROGRAM FORMAT
COMMAND Field Description

31 16 Op code 0x10
Op code Operand Not used
15 0 Addr_High High-order 16 bits of the 32-bit starting
address.
Operand
Addr_Low Low-order 16 bits of the 32-bit starting
31 16
address.
Addr_High
Data0_High High-order 16 bits of data word 0.
15 0
Data0_Low Low-order 16 bits of data word 0.
Addr_Low
Data1_High High-order 16 bits of data word 1.
31 16
Data1_Low Low-order 16 bits of data word 1.
Data0_High
Data2_High High-order 16 bits of data word 2.
15 0
Data2_Low Low-order 16 bits of data word 2.
Data0_Low
Data3_High High-order 16 bits of data word 3.
31 16
Data3_Low Low-order 16 bits of data word 3.
Data1_High
Data4_High High-order 16 bits of data word 4.
15 0
Data4_Low Low-order 16 bits of data word 4.
Data1_Low
Data5_High High-order 16 bits of data word 5.
31 16
Data5_Low Low-order 16 bits of data word 5.
Data2_High
Data6_High High-order 16 bits of data word 6.
15 0
Data6_Low Low-order 16 bits of data word 6.
Data2_Low
Data7_High High-order 16 bits of data word 7.
31 16
Data7_Low Low-order 16 bits of data word 7.
Data3_High
Expected Response (1 word):
15 0
Data3_Low FIGURE 17-33: QUAD_DOUBLE_WORD_PROGRAM
31 16 RESPONSE
Data4_High 31 16
15 0 Last Command
Data4_Low 15 0
31 16 Response Code
Data5_High
15 0
Data5_Low
31 16
Data6_High
15 0

 2007-2021 Microchip Technology Inc. DS60001145AA-page 51

PIC32
18.0 CHECKSUM 18.2 Mask Values
The mask value of a device Configuration is calculated
18.1 Theory by setting all the unimplemented bits to ‘0’ and all the
The checksum is calculated as the 32-bit summation of implemented bits to ‘1’.
all bytes (8-bit quantities) in program Flash, Boot Flash For example, Register 18-1 shows the DEVCFG0
(except device Configuration Words), the Device ID register of the PIC32MX360F512L device. The mask
register with applicable mask, and the device Configu- value for this register is as follows:
ration Words with applicable masks. Then the 2’s mask_value_devcfg0 = 0x110FF00B
complement of the summation is calculated. This final
32-bit number is presented as the checksum.
Note: The PIC32MKXXXXGPK/MCM/GPG/
MCJXXX devices use the CRC32 check-
sum. For additional information on the
CRC32 checksum, refer to the "Checksum
Changes" chapter of the document
"Readme for MPLABX IDE.htm", which can
be found at <MPLABX Installation
Path>\<MPLABX Revision>\docs.

REGISTER 18-1: DEVCFG0 REGISTER OF PIC32MX360F512L

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-0 r-1 r-1 R/P-1 r-1 r-1 r-1 R/P-1
31:24
— — — CP — — — BWP
r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1 R/P-1
23:16
— — — — PWP19 PWP18 PWP17 PWP16
R/P-1 R/P-1 R/P-1 R/P-1 r-1 r-1 r-1 r-1
15:8
PWP15 PWP14 PWP13 PWP12 — — — —
r-1 r-1 r-1 r-1 R/P-1 r-1 R/P-1 R/P-1
7:0
— — — — ICESEL — DEBUG[1:0]

Legend: P = Programmable bit r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS60001145AA-page 52  2007-2021 Microchip Technology Inc.

 PIC32
Table 18-1 lists the mask values of the four device Con- MPLABX IDE.htm", which can be found at <MPLABX
figuration registers and Device ID registers to be used Installation Path>\<MPLABX Revi-
in the checksum calculations for PIC32MX, PIC32MZ sion>\docs.
and PIC32MKXXXXGPD/GPE/MCFXXX devices.
PIC32MKXXXXGPK/MCM/GPG/MCJXXX devices use
the CRC32 checksum. For additional information on
the CRC32 checksum, refer to the "Checksum
Changes" chapter of the document "Readme for

TABLE 18-1: DEVICE CONFIGURATION REGISTER MASK VALUES OF CURRENTLY

SUPPORTED PIC32MX, PIC32MZ AND PIC32MKXXXXGPD/GPE/MCFXXX DEVICES

Flash
Device Family Memory DEVCFG0 DEVCFG1 DEVCFG2 DEVCFG3 DEVCFG4 DEVID
Sizes (KB)
PIC32MX110/120/130/
150F0xx
PIC32MX150F128 16, 32, 64,
0x1100FC1F 0x03DFF7A7 0x00070077 0xF000FFFF — 0x0FFFFFFF
(28/36/44-pin devices 128
only)

PIC32MX130F128/256
PIC32MX150F256
16, 32, 64,
(28/36/44-pin devices 0x1100FC1F 0x03DFF7A7 0x00070077 0xF0000000 — 0x0FFFFFFF
128
only)

PIC32MX210/220/230/
16, 32, 64,
250 (28/36/44-pin 0x1100FC1F 0x03DFF7A7 0x00078777 0xF0000000 — 0x0FFFFFFF
128
devices only)
PIC32MX15X/17X (28/
128, 256 0x1187F01F 0x03FFF7A7 0xFFB700F7 0x30C00000 — 0x0FFFFFFF
44-pin devices only)
PIC32MX25X/27X (28/
128, 256 0x1187F01F 0x03FFF7A7 0xFFB787F7 0x70C00000 — 0x0FFFFFFF
44-pin devices only)
PIC32MX320/340/360 32, 64, 128,
0x110FF00B 0x009FF7A7 0x00070077 0x0000FFFF — 0x000FF000
256, 512
PIC32MX420/440/460 32, 64, 128,
0x110FF00B 0x009FF7A7 0x00078777 0x0000FFFF — 0x000FF000
256, 512
PIC32MX110/120/130/
150F0xx
PIC32MX150F128 64, 128, 256, 0xF000FFFF
0x110FFC1F 0x03DFF7A7 0x00070077 — 0x0FFFFFFF
PIC32MX170F256 512
(64/100-pin Devices
only)
PIC32MX130F128/256
PIC32MX150F256
64, 128, 256,
PIC32MX170F512 0x110FFC1F 0x03DFF7A7 0x00070077 0xF0000000 — 0x0FFFFFFF
512
(64/100-pin devices
only)
PIC32MX230F0xx
PIC32MX250F128
64, 128, 256,
PIC32MX270F256 0x110FFC1F 0x03DFF7A7 0x00078777 0xF000FFFF — 0x0FFFFFFF
512
(64/100-pin devices
only)
Note 1: Applicable only to the PIC32MZ DA family of devices.
2: Device Configuration register mask values of PIC32MZ for:
• USERID: 0x0000FFF
• BCFG0: 0x8000000B

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PIC32
TABLE 18-1: DEVICE CONFIGURATION REGISTER MASK VALUES OF CURRENTLY
SUPPORTED PIC32MX, PIC32MZ AND PIC32MKXXXXGPD/GPE/MCFXXX DEVICES
(CONTINUED)
Flash
Device Family Memory DEVCFG0 DEVCFG1 DEVCFG2 DEVCFG3 DEVCFG4 DEVID
Sizes (KB)
PIC32MX230F128
PIC32MX230F256
PIC32MX250F256
PIC32MX270F512
64, 128, 256,
PIC32MX530 0x110FFC1F 0x03DFF7A7 0x00078777 0xF0000000 — 0x0FFFFFFF
512
PIC32MX550
PIC32MX570
(64/100-pin devices
only)
PIC32MX330/350/370 64, 128, 256,
0x110FF01F 0x03DFF7A7 0x00070077 0x3007FFFF — 0x0FFFFFFF
512
PIC32MX430/450/470 64, 128, 256,
0x110FF01F 0x03DFF7A7 0x00078777 0xF007FFFF — 0x0FFFFFFF
512
PIC32MX534/564 64, 128 0x110FF00F 0x009FF7A7 0x00078777 0xC407FFFF — 0x0FFFF000
PIC32MX664 64, 128 0x110FF00F 0x009FF7A7 0x00078777 0xC307FFFF — 0x0FFFF000
PIC32MK0512/
512, 1024 0x7FFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFF0000 — 0x0FFFFFFF
1024XXD/E/F
PIC32MX764 128 0x110FF00F 0x009FF7A7 0x00078777 0xC707FFFF — 0x0FFFF000
PIC32MX170F256
(28/36/44-pin devices 256 0x1107FC1F 0x03DFF7A7 0x00070077 0xF000FFFF — 0x0FFFFFFF
only)
PIC32MX170F512
(28/36/44-pin devices 256 0x1107FC1F 0x03DFF7A7 0x00070077 0xF0000000 — 0x0FFFFFFF
only)
PIC32MX270F256
(28/36/44-pin devices 256 0x1107FC1F 0x03DFF7A7 0x00078777 0xF000FFFF — 0x0FFFFFFF
only)
PIC32MX270F512
(28/36/44-pin devices 256 0x1107FC1F 0x03DFF7A7 0x00078777 0xF0000000 — 0x0FFFFFFF
only)
PIC32MZ05XX/10XX/ 512, 1024, 0xFFFFFFFF
0x7FFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFF0000 0x0FFFFFFF
20XX 2048 (Note 1)
PIC32MX575 256, 512 0x110FF00F 0x009FF7A7 0x00078777 0xC407FFFF — 0x000FF000
PIC32MX675/695 256, 512 0x110FF00F 0x009FF7A7 0x00078777 0xC307FFFF — 0x000FF000
PIC32MX775/795 256, 512 0x110FF00F 0x009FF7A7 0x00078777 0xC707FFFF — 0x000FF000
PIC32MZ W1 1024 0xFFB3FDFD 0x1FFFFF3B 0xFFFFFF38 0x0003FFFF 0x5FF800FF 0xFFFFFFFF
Note 1: Applicable only to the PIC32MZ DA family of devices.
2: Device Configuration register mask values of PIC32MZ for:
• USERID: 0x0000FFF
• BCFG0: 0x8000000B

DS60001145AA-page 54  2007-2021 Microchip Technology Inc.

 PIC32
18.3 Algorithm Then the 2’s complement of the summation is
calculated. This final 32-bit number is presented as the
Figure 18-1 illustrates an example of a high-level algo- checksum.
rithm for calculating the checksum for a PIC32 device to
demonstrate one method to derive a checksum. This is The mask values of the device Configuration and
merely an example of how the actual calculations can be Device ID registers are derived as described in the
accomplished, the method that is ultimately used is left to previous section, Section 18.2 “Mask Values”.
the discretion of the software developer. An arithmetic AND operation of these device
As stated earlier, the PIC32 checksum is calculated as Configuration register values is performed with the
the 32-bit summation of all bytes (8-bit quantities) in appropriate mask value, before adding their bytes to
program Flash, Boot Flash (except device the checksum.
Configuration Words), the Device ID register with Similarly, an arithmetic AND operation of the Device ID
applicable mask, and the device Configuration Words register is performed with the appropriate mask value,
with applicable masks. before adding its bytes to the checksum, see
Section 19.0 “Configuration Memory and Device
ID” for more information.

FIGURE 18-1: HIGH-LEVEL ALGORITHM FOR CHECKSUM CALCULATION

pic32_checksum

Read Program Flash, Boot Flash (including DEVCFG

registers) and DEVID register in tmpBuffer

Apply DEVCFG and DEVID masks to appropriate

locations in tmpBuffer

tmpChecksum (32-bit quantity) = 0

Finish processing all No tmpChecksum = tmpChecksum + Current Byte Value

bytes (8-bit quantities) in (8-bit quantity) in tmpBuffer
tmpBuffer?

Yes

Checksum (32-bit quantity) = 2’s complement

of tmpChecksum

Done

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PIC32
Equation 18-1 provides a formula to calculate the
checksum for a PIC32 device.

EQUATION 18-1: CHECKSUM FORMULA

Checksum = 2s complement  PF + BF + DCR + DIR 

Where,
PF = 32-bit summation of all bytes in Program Flash
BF = 32-bit summation of all bytes in Boot Flash, except device Configuration registers (see Note 1)
y
DCR =  32-bit summation of bytes  MASK DEVCFGX & DEVCFGx 
X = 0
Where,
y = 3 for PIC32MX, PIC32MKXXXXGPD/GPE/MCFXXX, PIC32MZ EC and PIC32MZ EF family of devices
y = 4 for all other PIC32MZ family of devices

DIR = 32-bit summation of bytes  MASK DEVID & DEVID 

MASKDEVCFGX = mask value from Table 18-1

MASKDEVID = mask value from Table 18-1 (Note 2)

DEVCP = 32-bit summation of bytes (MASKDEVCP & DEVCP)

Where,
MASKDEVCP = 0x10000000 for PIC32MKXXXXGPD/GPE/MCFXXX

Note 1: For the PIC32MZ family of devices, the Boot Flash memory that resides at 0x1FCxFF00 through
0x1FCxFFFF is not summed, as these memory locations contain the device configuration and CP
values. For PIC32MKXXXXGPD/GPE/MCFXXX family of devices, the Boot Flash memory that
resides at 0x1FC03F00 through 0x1FC03FFF is not summed.
2: For PIC32MZ and PIC32MKXXXXGPD/GPE/MCFXXX family of devices, the checksum calculated
in MPLAB X IDE only uses the primary DEVCFGx registers. Neither the alternate nor second Boot
Flash (if available) registers are calculated.

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 PIC32
18.4 Example of Checksum Calculation 18.4.2 CALCULATING FOR “BF” IN THE
CHECKSUM FORMULA
The following five sections demonstrate a checksum
calculation for the PIC32MX360F512L device using The size of the Boot Flash is 12 KB, which equals
Equation 18-1. 12288 bytes. However, the last 16 bytes are device
Configuration registers, which are treated separately.
The following assumptions are made for the purpose of
Therefore, the number of bytes in Boot Flash that we
this checksum calculation example:
consider in this step is 12272. Since the Boot Flash is
• Program Flash and Boot Flash are in the erased assumed to be in erased state, the value of “BF” is
state (all bytes are 0xFF) resolved through the following calculation:
• Device Configuration is in the default state of the BF = 0xFF + 0xFF + … 12272 times
device (no configuration changes are made)
BF = 0x002FC010 (32-bit number)
Each item on the right side of the equation (PF, BF,
DCR, DIR) is individually calculated. After deriving the 18.4.3 CALCULATING FOR “DCR” IN THE
values, the final value of the checksum can be CHECKSUM FORMULA
calculated.
Since the device Configuration registers are left in their
18.4.1 CALCULATING FOR “PF” IN THE default state, the value of the appropriate DEVCFG
CHECKSUM FORMULA register – as read by the PIC32 core, its respective
mask value, the value derived from applying the mask
The size of Program Flash is 512 KB, which equals and the 32-bit summation of bytes (all as shown in
524288 bytes. Since the program Flash is assumed to Table 18-2) provide the total of the 32-bit summation of
be in erased state, the value of PF is resolved through bytes.
the following calculation:
From Table 18-2, the value of “DCR” is:
PF = 0xFF + 0xFF + … 524288 times
DCR = 0x000003D6 (32-bit number)
PF = 0x7F80000 (32-bit number)

TABLE 18-2: DCR CALCULATION EXAMPLE

POR Default Value & 32-Bit Summation of
Register POR Default Value Mask
Mask Bytes
DEVCFG0 0x7FFFFFFF 0x110FF00B 0x110FF00B 0x0000011B
DEVCFG1 0xFFFFFFFF 0x009FF7A7 0x009FF7A7 0x0000023D
DEVCFG2 0xFFFFFFFF 0x00070077 0x00070077 0x0000007E
DEVCFG3 0xFFFFFFFF 0x00000000 0x00000000 0x00000000
Total of the 32-bit Summation of Bytes = 0x000003D6

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PIC32
18.4.4 CALCULATING FOR “DIR” IN THE
CHECKSUM FORMULA
The value of Device ID register and its mask value, the
value derived from applying the mask and the 32-bit
summation of bytes are shown in Table 18-3.
From Table 18-3, the value of “DIR” is:
DIR = 0x00000083 (32-bit number.)

TABLE 18-3: DIR CALCULATION EXAMPLE

POR Default Value 32-Bit Summation of
Register POR Default Value Mask
& Mask Bytes
DEVID 0x00938053 0x000FF000 0x00038000 0x00000083

18.4.5 COMPLETING THE PIC32

CHECKSUM CALCULATION
The values derived in previous sections (PF, BF, DCR,
DIR) are used to calculate the checksum value.
Perform the 32-bit summation of the PF, BF, DCR and
DIR as derived in previous sections and store it in a
variable, called temp, as shown in Example 18-1.

EXAMPLE 18-1: CHECKSUM CALCULATION PROCESS

1. First, temp = PF + BF + DCR + DIR, which translates to:

temp = 0x7F80000 + 0x002FC010 + 0x000003D6 + 0x00000083
2. Adding all four values results in temp being equal to 0x0827C469
3. Finally, the 2’s complement of temp is the checksum:
Checksum = 2’s complement (temp), which is Checksum = (1’s complement (temp)) + 1, resulting in
0xF7D83B97

18.4.6 CHECKSUM VALUES WHILE

DEVICE IS CODE-PROTECTED
Since the device Configuration Words are not readable
while the PIC32 devices are in code-protected state,
the checksum values are zeros for all devices.

DS60001145AA-page 58  2007-2021 Microchip Technology Inc.

 PIC32
19.0 CONFIGURATION MEMORY TABLE 19-2: DEVCFG LOCATIONS FOR 28/
AND DEVICE ID 36/44-PIN PIC32MX1XX/2XX
AND 64/100-PIN PIC32MX1XX/
PIC32 devices include several features intended to 2XX/5XX DEVICES ONLY
maximize application flexibility and reliability, and
minimize cost through elimination of external Configuration Word Physical Address
components. These features are configurable through DEVCFG0 0x1FC00BFC
specific Configuration bits for each device. DEVCFG1 0x1FC00BF8
Refer to the “Special Features” chapter in the specific DEVCFG2 0x1FC00BF4
device data sheet for a full list of available features,
DEVCFG3 0x1FC00BF0
Configuration bits and the Device ID register.
On Power-on Reset (POR) or any Reset, the
Refer to Appendix C: “Device IDs” to locate the
Configuration Words are copied from the Boot Flash
Device ID for a particular PIC32MX, PIC32MZ or
PIC32MK family of devices. memory to their corresponding Configuration registers.
A Configuration bit can only be programmed = 0
For the current silicon revision and revision ID for a (unprogrammed state = 1).
particular device, refer to the related Family Silicon
Errata and Data Sheet Clarification. These During programming, a Configuration Word can be
documents are available for download from the programmed a maximum of two times for PIC32MX
Microchip web site: http://www.microchip.com/PIC32 devices and only one time for PIC32MZ, and PIC32MK
and navigating to: Documentation > Errata. family devices before a page erase must be performed.
After programming the Configuration Words, a device
19.1 Device Configuration Reset will cause the new values to be loaded into the
In PIC32 devices, the Configuration Words select Configuration registers. Because of this, the programmer
various device configurations that are set at device should program the Configuration Words just prior to ver-
Reset prior to execution of any code. These values are ification of the device. The final step is programming the
located at the highest locations of the Boot Flash Mem- code protection Configuration Word.
ory (BFM) and since they are part of the program mem- These Configuration Words determine the oscillator
ory, are included in the programming file along with source. If using the 2-wire Enhanced ICSP mode the
executable code and program constants. The names Configuration Words are ignored and the device will
and locations of these Configuration Words are listed in always use the FRC; however, in 4-wire mode this is
Table 19-1 through Table 19-4. not the case. If an oscillator source is selected by the
Additionally, Table 19-3 and Table 19-4 include Config- Configuration Words that is not present on the device
uration Words for PIC32MZ and PIC32MK family after Reset, the programmer will not be able to perform
devices, respectively, with dual boot and dual panel Flash operations on the device after it is Reset. See the
Flash. Refer to Section 48. “Memory Organization “Special Features” chapter in the specific device data
and Permissions” (DS60001214) of the “PIC32 sheet for details regarding oscillator selection using the
Family Reference Manual” for a detailed description of Configuration Words.
the dual boot regions.

TABLE 19-1: DEVCFG LOCATIONS FOR

15X/17X/25X/27X AND
PIC32MX3XX/4XX/5XX/6XX/
7XX DEVICES ONLY
Configuration Word Physical Address
DEVCFG0 0x1FC02FFC
DEVCFG1 0x1FC02FF8
DEVCFG2 0x1FC02FF4
DEVCFG3 0x1FC02FF0

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PIC32
TABLE 19-3: CONFIGURATION WORD LOCATIONS FOR PIC32MZ FAMILY DEVICES
Register Physical Address
Configuration Word Active Boot Inactive Boot
(see Note 1) Fixed Boot Fixed Boot
Alias Region Alias Region
Region 1 Region 2
(see Note 2) (see Note 2)
Boot Sequence Number 0x1FC4FFF0 0x1FC6FFF0 0x1FC0FFF0 0x1FC2FFF0
Code Protection 0x1FC4FFD0 0x1FC6FFD0 0x1FC0FFD0 0x1FC2FFD0
DEVCFG0 0x1FC4FFCC 0x1FC6FFCC 0x1FC0FFCC 0x1FC2FFCC
DEVCFG1 0x1FC4FFC8 0x1FC6FFC8 0x1FC0FFC8 0x1FC2FFC8
DEVCFG2 0x1FC4FFC4 0x1FC6FFC4 0x1FC0FFC4 0x1FC2FFC4
DEVCFG3 0x1FC4FFC0 0x1FC6FFC0 0x1FC0FFC0 0x1FC2FFC0
DEVCFG4 (see Note 3) 0x1FC4FFBC 0x1FC6FFBC 0x1FC0FFBC 0x1FC2FFBC
Alternate Boot Sequence Number 0x1FC4FF70 0x1FC6FF70 0x1FC0FF70 0x1FC2FF70
Alternate Code Protection 0x1FC4FF50 0x1FC6FF50 0x1FC0FF50 0x1FC2FF50
Alternate DEVCFG0 0x1FC4FF4C 0x1FC6FF4C 0x1FC0FF4C 0x1FC2FF4C
Alternate DEVCFG1 0x1FC4FF48 0x1FC6FF48 0x1FC0FF48 0x1FC2FF48
Alternate DEVCFG2 0x1FC4FF44 0x1FC6FF44 0x1FC0FF44 0x1FC2FF44
Alternate DEVCFG3 0x1FC4FF40 0x1FC6FF40 0x1FC0FF40 0x1FC2FF40
Alternate DEVCFG4 (see Note 3) 0x1FC4FF3C 0x1FC6FF3C 0x1FC0FF3C 0x1FC2FF3C
Note 1: All values in the 0x1FCxFF00-0x1FCxFFFF memory regions should be programmed using the
QUAD_WORD_PROGRAM command to ensure proper ECC configuration. Refer to Section 17.2.16
“QUAD_WORD_PROGRAM Command” for details.
2: Active/Inactive boot alias selections are assumed for an unprogrammed device where Fixed Region 1 is
active and Fixed Region 2 is inactive. Refer to Section 48. “Memory Organization and Permissions”
(DS60001214) for a detailed description of the alias boot regions.
3: These Configuration Words are available only on PIC32MZ DA family devices.

TABLE 19-4: CONFIGURATION WORD LOCATIONS FOR PIC32MKXXXXXXD/E/FXX FAMILY

DEVICES
Register Physical Address
Configuration Word Fixed Boot Active Boot Inactive Boot
(see Note 1) Fixed Boot
Region 2 Alias Region Alias Region
Region 1
(see Note 2) (see Note 2)
Boot Sequence Number 0x1FC43FF0 0x1FC63FF0 0x1FC03FF0 0x1FC23FF0
Code Protection 0x1FC43FD0 0x1FC63FD0 0x1FC03FD0 0x1FC23FD0
DEVCFG0 0x1FC43FCC 0x1FC63FCC 0x1FC03FCC 0x1FC23FCC
DEVCFG1 0x1FC43FC8 0x1FC63FC8 0x1FC03FC8 0x1FC23FC8
DEVCFG2 0x1FC43FC4 0x1FC63FC4 0x1FC03FC4 0x1FC23FC4
DEVCFG3 0x1FC43FC0 0x1FC63FC0 0x1FC03FC0 0x1FC23FC0
Note 1: If the device has ECC memory, each of the following Configuration Word Groups should be programmed
using the QUAD_WORD_PROGRAM command:
• Boot Sequence Number (single quad word programming operation)
• Code Protection (single quad word programming operation)
• DEVCFG3, DEVCFG2, DEVCFG1 and DEVCFG0 (single quad word programming operation)
2: Active/Inactive boot alias selections are assumed for an unprogrammed device where Fixed Region 1 is
active and Fixed Region 2 is inactive. Refer to the Section 48. “Memory Organization and Permis-
sions” (DS60001214) for a detailed description of the alias boot regions.

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 PIC32
TABLE 19-5: CONFIGURATION WORD LOCATIONS FOR PIC32MKXXXXXXH/G/J/K/L/MXX
FAMILY DEVICES
Register Physical Address
Configuration Word Fixed Boot Active Boot Inactive Boot
(see Note 1) Fixed Boot
Region 2 Alias Region Alias Region
Region 1
(see Notes 2, 3) (see Notes 2, 3)
Boot Sequence Number 0x1FC43FF0 0x1FC63FF0 0x1FC03FF0 0x1FC23FF0
Code Protection 0x1FC43FD0 0x1FC63FD0 0x1FC03FD0 0x1FC23FD0
DEVCFG0 0x1FC43FCC 0x1FC63FCC 0x1FC03FCC 0x1FC23FCC
DEVCFG1 0x1FC43FC8 0x1FC63FC8 0x1FC03FC8 0x1FC23FC8
DEVCFG2 0x1FC43FC4 0x1FC63FC4 0x1FC03FC4 0x1FC23FC4
DEVCFG3 0x1FC43FC0 0x1FC63FC0 0x1FC03FC0 0x1FC23FC0
DEVCFG4 0x1FC43FBC — — —
Alternate Boot Sequence Number 0x1FC43F70 0x1FC63F70 0x1FC03F70 0x1FC23F70
Alternate Code Protection 0x1FC43F50 0x1FC63F50 0x1FC03F50 0x1FC23F50
Alternate DEVCFG0 0x1FC43F4C 0x1FC63F4C 0x1FC03F4C 0x1FC23F4C
Alternate DEVCFG1 0x1FC43F48 0x1FC63F48 0x1FC03F48 0x1FC23F48
Alternate DEVCFG2 0x1FC43F44 0x1FC63F44 0x1FC03F44 0x1FC23F44
Alternate DEVCFG3 0x1FC43F40 0x1FC63F40 0x1FC03F40 0x1FC23F40
Alternate DEVCFG4 0x1FC43F3C 0x1FC63F3C 0x1FC03F3C 0x1FC23F3C
Note 1: If the device has ECC memory, each of the following Configuration Word Groups should be programmed
using the QUAD_WORD_PROGRAM command:
• Boot Sequence Number (single quad word programming operation)
• Code Protection (single quad word programming operation)
• DEVCFG3, DEVCFG2, DEVCFG1 and DEVCFG0 (single quad word programming operation)
2: All values in the 0x1FCxFF00-0x1FCxFFFF memory regions should be programmed using the
QUAD_WORD_PROGRAM command to ensure proper ECC configuration. Refer to the Section 17.2.16
“QUAD_WORD_PROGRAM Command” for details.
3: Active or Inactive boot alias selections are assumed for an unprogrammed device where Fixed Region 1 is
active and Fixed Region 2 is inactive. Refer to the Section 48. “Memory Organization and Permis-
sions” (DS60001214) for a detailed description of the alias boot regions.

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PIC32
19.1.1 DEVICE CONFIGURATION FOR To ensure integrity of the 128-bit data, a comparison is
PIC32MZ W1 DEVICES made between each Configuration bit and its stored
complement continuously. If a mismatch is detected, a
In PIC32MZ W1 devices, the Configuration Words
Configuration Mismatch Reset is generated, which
select various device configurations that are set at the
causes a device Reset.
device Reset prior to the execution of any code. They
are part of the program memory and are included in the 19.2 Device Code Protection Bit (CP)
programming file along with the executable code and
program constants. The names and locations of these The PIC32 family of devices feature code protec-
Configuration Words are listed in Table 19-6. tion, which when enabled, prevents reading of the
Flash memory by an external programming device.
TABLE 19-6: DEVCFG LOCATIONS FOR Once code protection is enabled, it can only be dis-
PIC32MZ W1 abled by erasing the device with the Chip Erase
command (MCHP_ERASE).
Configuration Word Physical Address
When programming a device that has opted to uti-
BCFG0 0x1F800100 lize code protection, the programming device must
CFGCON0 0x1F800000 perform verification prior to enabling code protec-
CFGCON1 0x1F800010 tion. Enabling code protection should be the last step
CFGCON2 0x1F800020 of the programming process. Location of the code
protection enable bits vary by device. Refer to the
CFGCON3 0x1F800030
“Special Features” chapter in the specific device
CFGCON4 0x1F800040 data sheet for details.
USERID 0x1F800070
Note: Once code protection is enabled, the
Flash memory can no longer be read and
TABLE 19-7: Flash Register Locations for can only be disabled by an external
PIC32MZ W1 programmer using the Chip Erase
Command (MCHP_ERASE).
Configuration Word
Physical Address
(see Note 1)
BFDEVCFG0 0x1FC5_5F9C
BFDEVCFG1 0x1FC5_5F98
BFDEVCFG2 0x1FC5_5F94
BFDEVCFG3 0x1FC5_5F90
BFDEVCFG4 0x1FC5_5F8C
BFDEVCFG5 0x1FC5_5F88
Note 1: The user-configured setting of
BFDEVCFG0 to BFDEVCFG5 loaded from
the boot Flash into the following counterpart
registers at system start-up.
• BFDEVCFG0 to BCFG0(L)
• BFDEVCFG1 to CFGCON0(L)
• BFDEVCFG2 to CFGCON1(L)
• BFDEVCFG3 to CFGCON2(L)
• BFDEVCFG4 to CFGCON4(L)
• BFDEVCFG5 to USERID

19.1.2 CONFIGURATION REGISTER

PROTECTION
To prevent inadvertent Configuration bit changes
during code execution, all programmable Configuration
bits are write-once. After a bit is initially programmed
during a power cycle, it cannot be written to again.
Changing a device configuration requires changing the
Configuration data in the Boot Flash memory, and
cycling power to the device.

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 PIC32
19.3 Program Write Protection Bits (PWP)
The PIC32 families of devices include write protection
features, which prevent designated boot and program
Flash regions from being erased or written during
program execution.
In PIC32MX devices, write protection is implemented in
Configuration memory by the Device Configuration
Words, while in PIC32MZ and PIC32MK family
devices, this feature is implemented through SFRs in
the Flash controller.
When write protection is implemented by Device
Configuration Words, the write protection register
should only be written when all boot and program Flash
memory has been programmed. Refer to the “Special
Features” chapter in the specific device data sheet for
details.
If write protection is implemented using SFRs, certain
steps may be required during initialization of the device
by the external programmer prior to programming
Flash regions. Refer to the “Flash Program Memory”
chapter in the specific device data sheet for details.

 2007-2021 Microchip Technology Inc. DS60001145AA-page 63

PIC32
20.0 TAP CONTROLLERS

TABLE 20-1: MCHP TAP INSTRUCTIONS

Command Value Description
MTAP_COMMAND 5’h0x07 TDI and TDO connected to MCHP Command Shift register (See Table 20-2)
MTAP_SW_MTAP 5’h0x04 Switch TAP controller to MCHP TAP controller
MTAP_SW_ETAP 5’h0x05 Switch TAP controller to EJTAG TAP controller
MTAP_IDCODE 5’h0x01 Select Chip Identification Data register

20.1 Microchip TAP Controllers (MTAP) 20.1.1.6 MCHP_FLASH_DISABLE

INSTRUCTION
20.1.1 MTAP_COMMAND INSTRUCTION
MCHP_FLASH_DISABLE clears the FAEN bit which
MTAP_COMMAND selects the MCHP Command Shift controls processor accesses to the Flash memory. The
register. See Table 20-2 for available commands. FAEN bit’s state is returned in the field of the same
name. This command has no effect if CPS = 0. This
20.1.1.1 MCHP_STATUS INSTRUCTION command requires a NOP to complete.
MCHP_STATUS returns the 8-bit Status value of the Note: This command is not required for
Microchip TAP controller. Table 20-3 provides the PIC32MZ and PIC32MK family devices.
format of the Status value returned.

20.1.1.2 MCHP_ASSERT_RST INSTRUCTION 20.1.2 MTAP_SW_MTAP INSTRUCTION

MTAP_SW_MTAP switches the TAP instruction set to the
MCHP_ASSERT_RST performs a persistent device
MCHP TAP instruction set.
Reset. It is similar to asserting and holding the MCLR
pin. Its associated Status bit is DEVRST. Each of these commands should be followed with a
SetMode (6'b011111) to force the Chip TAP controller
20.1.1.3 MCHP_DE_ASSERT_RST to the Run Test/Idle state.
INSTRUCTION
20.1.3 MTAP_SW_ETAP INSTRUCTION
MCHP_DE_ASSERT_RST removes the persistent
device Reset. It is similar to deasserting the MCLR pin. MTAP_SW_ETAP effectively switches the TAP
Its associated Status bit is DEVRST. instruction set to the EJTAG TAP instruction set. It does
this by holding the EJTAG TAP controller in the Run
20.1.1.4 MCHP_ERASE INSTRUCTION Test/Idle state until a MTAP_SW_ETAP instruction is
decoded by the MCHP TAP controller.
MCHP_ERASE performs a Chip Erase. The CHIP_
ERASE command sets an internal bit that requests Each of these commands should be followed with a
the Flash Controller to perform the erase. Once the SetMode (6'b011111) to force the Chip TAP controller
controller becomes busy, as indicated by FCBUSY to the Run Test/Idle state.
(Status bit), the internal bit is cleared.
20.1.4 MTAP_IDCODE INSTRUCTION
20.1.1.5 MCHP_FLASH_ENABLE MTAP_IDCODE returns the value stored in the DEVID
INSTRUCTION register.
MCHP_FLASH_ENABLE sets the FAEN bit, which con-
trols processor accesses to the Flash memory. The
FAEN bit’s state is returned in the field of the same
name. This command has no effect if CPS = 0. This
command requires a NOP to complete.
Note: This command is not required for
PIC32MZ and PIC32MK family devices.

DS60001145AA-page 64  2007-2021 Microchip Technology Inc.

 PIC32
TABLE 20-2: MTAP_COMMAND DR COMMANDS
Command Value Description
MCHP_STATUS 8’h0x00 NOP and return Status.
MCHP_ASSERT_RST 8’h0xD1 Requests the Reset controller to assert device Reset.
MCHP_DE_ASSERT_RST 8’h0xD0 Removes the request for device Reset, which causes the reset
controller to deassert device Reset if there is no other source
requesting Reset (i.e., MCLR).
MCHP_ERASE 8’h0xFC Cause the Flash controller to perform a Chip Erase.
MCHP_FLASH_ENABLE(1) 8’h0xFE Enables fetches and loads to the Flash (from the processor).
(1)
MCHP_FLASH_DISABLE 8’h0xFD Disables fetches and loads to the Flash (from the processor).
Note 1: This command is not required for PIC32MK and PIC32MZ family of devices.

TABLE 20-3: MCHP STATUS VALUE

Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Range
7:0 CPS 0 NVMERR(1) 0 CFGRDY FCBUSY FAEN(2) DEVRST

bit 7 CPS: Code-Protect State bit

1 = Device is not code-protected
0 = Device is code-protected
bit 6 Unimplemented: Read as ‘0’
bit 5 NVMERR: NVMCON Status bit(1)
1 = An Error occurred during NVM operation
0 = An Error did not occur during NVM operation
bit 4 Unimplemented: Read as ‘0’
bit 3 CFGRDY: Code-Protect State bit
1 = Configuration has been read and CP is valid
0 = Configuration has not been read
bit 2 FCBUSY: Flash Controller Busy bit
1 = Flash controller is busy (Erase is in progress)
0 = Flash controller is not busy (either erase has not started or it has finished)
bit 1 FAEN: Flash Access Enable bit(2)
This bit reflects the state of CFGCON.FAEN.
1 = Flash access is enabled
0 = Flash access is disabled (i.e., processor accesses are blocked)
bit 0 DEVRST: Device Reset State bit
1 = Device Reset is active
0 = Device Reset is not active

Note 1: This bit is not implemented in PIC32MX320/340/360/420/440/460 devices.

2: This bit is not implemented in PIC32MK and PIC32MZ family devices.

TABLE 20-4: EJTAG TAP INSTRUCTIONS

Command Value Description
ETAP_ADDRESS 5’h0x08 Select Address register.
ETAP_DATA 5’h0x09 Select Data register.
ETAP_CONTROL 5’h0x0A Select EJTAG Control register.
ETAP_EJTAGBOOT 5’h0x0C Set EjtagBrk, ProbEn and ProbTrap to ‘1’ as the Reset value.
ETAP_FASTDATA 5’h0x0E Selects the Data and Fastdata registers.

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PIC32
20.2 EJTAG TAP Controller 20.2.3 ETAP_CONTROL COMMAND
ETAP_CONTROL selects the Control register. The
20.2.1 ETAP_ADDRESS COMMAND EJTAG Control register (ECR) handles processor Reset
ETAP_ADDRESS selects the Address register. The and soft Reset indication, Debug mode indication,
read-only Address register provides the address for a access start, finish and size and read/write indication.
processor access. The value read in the register is The ECR also provides the following features:
valid if a processor access is pending, otherwise the • Controls debug vector location and indication of
value is undefined. serviced processor accesses
The two or three Least Significant Bytes (LSBs) of the • Allows a debug interrupt request
register are used with the Psz field from the EJTAG • Indicates a processor low-power mode
Control register to indicate the size and data position of
• Allows implementation-dependent processor and
the pending processor access transfer. These bits are
peripheral Resets
not taken directly from the address referenced by the
load/store.
20.2.3.1 EJTAG Control Register (ECR)
20.2.2 ETAP_DATA COMMAND The EJTAG Control register (see Register 20-1) is not
updated/written in the Update-DR state unless the
ETAP_DATA selects the Data register. The read/write
Reset occurred; that is ROCC (bit 31) is either already
Data register is used for op code and data transfers
‘0’ or is written to ‘0’ at the same time. This condition
during processor accesses. The value read in the Data
ensures proper handling of processor accesses after a
register is valid only if a processor access for a write is
Reset.
pending, in which case the Data register holds the store
value. The value written to the Data register is only Reset of the processor can be indicated through the
used if a processor access for a pending read is ROCC bit in the TCK domain a number of TCK cycles
finished afterwards; in which case, the data value after it is removed in the processor clock domain in
written is the value for the fetch or load. This behavior order to allow for proper synchronization between the
implies that the Data register is not a memory location two clock domains.
where a previously written value can be read Bits that are Read/Write (R/W) in the register return
afterwards. their written value on a subsequent read, unless other
behavior is defined.
Internal synchronization ensures that a written value is
updated for reading immediately afterwards, even
when the TAP controller takes the shortest path from
the Update-DR to Capture-DR state.

DS60001145AA-page 66  2007-2021 Microchip Technology Inc.

 PIC32
REGISTER 20-1: ECR: EJTAG CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R-0 R-0 U-0 U-0 U-0 U-0 U-0
31:24
Rocc Psz[1:0] — — — — —
R-0 R-0 R-0 R/W-0 R-0 R/W-0 U-0 R/W-0
23:16
VPED Doze Halt PerRst PrnW PrACC — PrRst
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0
15:8
ProbEn ProbTrap — EjtagBrk — — — —
U-0 U-0 U-0 U-0 R-0 U-0 U-0 U-0
7:0
— — — — DM — — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 See Note 1

bit 28-24 Unimplemented: Read as ‘0’
bit 23-19 See Note 1
bit 18 PrACC: Pending Processor Access and Control bit
This bit indicates a pending processor access and controls finishing of a pending processor access. A write
of ‘0’ finishes processor access if pending. A write of ‘1’ is ignored. A successful FASTDATA access will clear
this bit.
1 = Pending processor access
0 = No pending preprocessor access
bit 17 Unimplemented: Read as ‘0’
bit 16 See Note 1
bit 15 ProbEn: Processor Access Service Control bit
This bit controls where the probe handles accesses to the DMSEG segment through servicing of processor
accesses.
1 = Probe services processor accesses
0 = Probe does not service processor access
bit 14 ProbTrap: Debug Exception Vector Control Location bit
This bit controls the location of the debug exception vector.
1 = 0xFF200200
0 = 0xBFC00480
bit 13 Unimplemented: Read as ‘0’
bit 12 EjtagBrk: Debug Interrupt Exception Request bit
This bit requests a debug interrupt exception to the processor when this bit is written as ‘1’. A write of ‘0’ is
ignored.
1 = A debug interrupt exception request is pending
0 = A debug interrupt exception request is not pending
bit 11-4 Unimplemented: Read as ‘0’
bit 3 See Note 1
bit 2-0 Unimplemented: Read as ‘0’

Note 1: For descriptions of these bits, please refer to the Imagination Technologies Limited web site.
(www.imgtec.com).

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PIC32
20.2.4 ETAP_EJTAGBOOT COMMAND 20.2.5 ETAP_FASTDATA COMMAND
The ETAP_EJTAGBOOT command causes the The ETAP_FASTDATA command provides a
processor to fetch code from the debug exception mechanism for quickly transferring data between the
vector after a Reset. This allows the programmer to processor and the probe. The width of the Fastdata
send instructions to the processor to execute, instead register is one bit. During a fast data access, the
of the processor fetching them from the normal Reset Fastdata register is written and read (i.e., a bit is shifted
vector. The Reset value of the EjtagBrk, ProbTrap and in and a bit is shifted out). During a fast data access,
ProbE bits follows the setting of the internal the Fastdata register value shifted in specifies whether
EJTAGBOOT indication. the fast data access should be completed or not. The
If the EJTAGBOOT instruction has been given, and the value shifted out is a flag that indicates whether the fast
internal EJTAGBOOT indication is active, then the data access was successful or not (if completion was
Reset value of the three bits is set (‘1’), otherwise the requested). The FASTDATA access is used for efficient
Reset value is clear (‘0’). block transfers between the DMSEG segment (on the
probe) and target memory (on the processor). An
The results of setting these bits are: “upload” is defined as a sequence that the processor
• Setting the EjtagBrk causes a Debug interrupt loads from target memory and stores to the DMSEG
exception to be requested right after the segment. A “download” is a sequence of processor
processor Reset from the EJTAGBOOT instruction loads from the DMSEG segment and stores to target
• The debug handler is executed from the EJTAG memory. The “Fastdata area” specifies the legal range
memory because ProbTrap is set to indicate of DMSEG segment addresses (0xFF200000 to
debug vector in EJTAG memory at 0xFF200200 0xFF20000F) that can be used for uploads and
downloads. The Data and Fastdata registers (selected
• Service of the processor access is indicated
with the FASTDATA instruction) allow efficient
because ProbEn is set
completion of pending Fastdata area accesses.
With this configuration in place, an interrupt exception
During Fastdata uploads and downloads, the
will occur and the processor will fetch the handler from
processor will stall on accesses to the Fastdata area.
the DMSEG at 0xFF200200. Since ProbEn is set, the
The PrAcc (processor access pending bit) will be ‘1’
processor will wait for the instruction to be provided by
indicating the probe is required to complete the access.
the probe.
Both upload and download accesses are attempted by
shifting in a zero SPrAcc value (to request access
completion) and shifting out SPrAcc to see if the
attempt will be successful (i.e., there was an access
pending and a legal Fastdata area address was used).
Downloads will also shift in the data to be used to
satisfy the load from the DMSEG segment Fastdata
area, while uploads will shift out the data being stored
to the DMSEG segment Fastdata area.
As indicated, the following two conditions must be true
for the Fastdata access to succeed:
• PrAcc must be ‘1’ (i.e., there must be a pending
processor access)
• The Fastdata operation must use a valid Fastdata
area address in the DMSEG segment
(0xFF200000 to 0xFF20000F)

DS60001145AA-page 68  2007-2021 Microchip Technology Inc.

 PIC32
21.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
TABLE 21-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: 0ºC to +70ºC. Programming at +25ºC is recommended.

Param.
Symbol Characteristic Min. Max. Units Conditions
No.
D111 VDDIO Supply Voltage During Programming — — V See Note 1
D112a VDDCORE Core Power Supply Voltage During Programming — — V See Note 1
D112b VDDR1V8 DDR SDRAM Supply Voltage During Programming — — V See Note 1
D113 IDDP Supply Current During Programming — — mA See Note 1
D114 IPEAK Instantaneous Peak Current During Start-up — — mA See Note 1
D115a IDDCORE Core Power Supply Current During Programming — — mA See Note 1
D115b IDDR1V8P DDR SDRAM Supply Current During Programming — — mA See Note 1
D116 VDDVBAT VBAT Supply Voltage During Programming — — V See Note 1
D117 IDDVBAT VBAT Supply Current During Programming — — mA See Note 1
D031 VIL Input Low Voltage — — V See Note 1
D041 VIH Input High Voltage — — V See Note 1
D080 VOL Output Low Voltage — — V See Note 1
D090 VOH Output High Voltage — — V See Note 1
D012 CIO Capacitive Loading on I/O pin (PGEDx) — — pF See Note 1
D013 CF Filter Capacitor Value on VCAP — — F See Note 1
P1 TPGC Serial Clock (PGECx) Period 100 — ns —
P1A TPGCL Serial Clock (PGECx) Low Time 40 — ns —
P1B TPGCH Serial Clock (PGECx) High Time 40 — ns —
P6 TSET2 VDD Setup Time to MCLR  100 — ns —
P7 THLD2 Input Data Hold Time from MCLR  500 — ns —
P9a TDLY4 PE Command Processing Time 40 — s —
Delay between PGEDx by the PE to PGEDx
P9b TDLY5 15 — s —
Released by the PE
P11 TDLY7 Chip Erase Time — — ms See Note 1
P12 TDLY8 Page Erase Time — — ms See Note 1
P13 TDLY9 Row Programming Time — — ms See Note 1
P14 TR MCLR Rise Time to Enter ICSP™ mode — 1.0 s —
P15 TVALID Data Out Valid from PGECx  10 — ns —
P16 TDLY8 Delay between Last PGECx  and MCLR  0 — s —
P17 THLD3 MCLR to VDD  — 100 ns —
Delay from First MCLR to First PGECx for Key
P18 TKEY1 40 — ns —
Sequence on PGEDx
Delay from Last PGECx for Key Sequence on
P19 TKEY2 40 — ns —
PGEDx to Second MCLR 
P20 TMCLRH MCLR High Time — 500 µs —
Note 1: Refer to the “Electrical Characteristics” chapter in the specific device data sheet for the Minimum and
Maximum values for this parameter.

 2007-2021 Microchip Technology Inc. DS60001145AA-page 69

PIC32
APPENDIX A: PIC32 FLASH APPENDIX B: HEX FILE FORMAT
MEMORY MAP Flash programmers process the standard hexadecimal
(hex) format used by the Microchip development tools.
FIGURE A-1: FLASH MEMORY MAP The format supported is the Intel® HEX32 Format
(INHX32). Refer to the Section 1.75 “Hex file
0x1D000000 Formats” in the “MPASM™ Assembler, MPLINK™
Object Linker, MPLIB™ Object Librarian User’s Guide”
(DS33014) for more information about hex file formats.
The basic format of the hex file is:
:BBAAAATTHHHH...HHHHCC
Each data record begins with a 9-character prefix and
always ends with a 2-character checksum. All records
begin with ‘:’, regardless of the format. The individual
elements are described below.
• BB – is a two-digit hexadecimal byte count
representing the number of data bytes that appear
on the line. Divide this number by two to get the
PFM

Program Flash Memory number of words per line.

• AAAA – is a four-digit hexadecimal address
representing the starting address of the data
record. Format is high byte first followed by low
byte.
• TT – is a two-digit record type that will be ‘00’ for
data records, ‘01’ for end-of-file records and ‘04’
for extended-address record.
• HHHH – is a four-digit hexadecimal data word.
Format is low byte followed by high byte. There
will be BB/2 data words following TT.
• CC – is a two-digit hexadecimal checksum that is
the 2’s complement of the sum of all the
0x1D007FFF preceding bytes in the line record.
Because the Intel hex file format is byte-oriented but
0x1F000000 the 16-bit program counter is not, program memory
sections require special treatment. Each 24-bit
Boot Page 0 program word is extended to 32 bits by inserting a so-
called “phantom byte”. Each program memory
address is multiplied by 2 to yield a byte address.
Boot Page 1
BFM

As an example, a section that is located at 0x100 in

0x1F001FFF program memory will be represented in the hex file as
Boot Page 2 0x200.
Debug Page
0x1F002FF0 The hex file will be produced with the following
Configuration Words contents:
(4 x 32 bits)
0x1F002FFF :020000040000fa
:040200003322110096
:00000001FF
Note: The memory map shown is for reference The data record (second line) has a load address of
only. Refer to the “Memory Organization” 0200, while the source code specified address is
chapter in the specific device data sheet for 0x100. The data is represented in “little-endian”
the memory map for your device. format, that is the Least Significant Byte appears first
and the phantom byte appears last, before the
checksum.

DS60001145AA-page 70  2007-2021 Microchip Technology Inc.

 PIC32
APPENDIX C: DEVICE IDS TABLE C-3: PIC32MX534/564/664/764
FAMILY DEVICE IDS
TABLE C-1: PIC32MX320/340/360/440/460
Part Number Device ID (See Note 1)
FAMILY DEVICE IDS
PIC32MX534F064H 0x04400053
Part Number Device ID (See Note 1)
PIC32MX564F064H 0x04401053
PIC32MX360F512L 0x0938053 PIC32MX564F128H 0x04403053
PIC32MX360F256L 0x0934053 PIC32MX664F064H 0x04405053
PIC32MX340F128L 0x092D053 PIC32MX664F128H 0x04407053
PIC32MX320F128L 0x092A053 PIC32MX764F128H 0x0440B053
PIC32MX340F512H 0x0916053 PIC32MX534F064L 0x0440C053
PIC32MX340F256H 0x0912053 PIC32MX564F064L 0x0440D053
PIC32MX340F128H 0x090D053 PIC32MX564F128L 0x0440F053
PIC32MX320F128H 0x090A053 PIC32MX664F064L 0x04411053
PIC32MX320F064H 0x0906053 PIC32MX664F128L 0x04413053
PIC32MX320F032H 0x0902053 PIC32MX764F128L 0x04417053
PIC32MX460F512L 0x0978053
PIC32MX460F256L 0x0974053
TABLE C-4: PIC32MX1XX/2XX 28/36/44-
PIC32MX440F128L 0x096D053
PIN FAMILY DEVICE IDS
PIC32MX440F256H 0x0952053
Part Number Device ID (See Note 1)
PIC32MX440F512H 0x0956053
PIC32MX440F128H 0x094D053 PIC32MX110F016B 0x04A07053
PIC32MX420F032H 0x0942053 PIC32MX110F016C 0x04A09053
PIC32MX110F016D 0x04A0B053
TABLE C-2: PIC32MX575/675/695/775/795 PIC32MX210F016B 0x04A01053
FAMILY DEVICE IDS PIC32MX210F016C 0x04A03053
PIC32MX210F016D 0x04A05053
Part Number Device ID (See Note 1)
PIC32MX120F032B 0x04A06053
PIC32MX575F256H 0x04317053
PIC32MX120F032C 0x04A08053
PIC32MX675F256H 0x0430B053
PIC32MX120F032D 0x04A0A053
PIC32MX775F256H 0x04303053
PIC32MX220F032B 0x04A00053
PIC32MX575F512H 0x04309053
PIC32MX220F032C 0x04A02053
PIC32MX675F512H 0x0430C053
PIC32MX220F032D 0x04A04053
PIC32MX695F512H 0x04325053
PIC32MX130F064B 0x04D07053
PIC32MX775F512H 0x0430D053
PIC32MX130F064C 0x04D09053
PIC32MX795F512H 0x0430E053
PIC32MX130F064D 0x04D0B053
PIC32MX575F256L 0x04333053
PIC32MX230F064B 0x04D01053
PIC32MX675F256L 0x04305053
PIC32MX230F064C 0x04D03053
PIC32MX775F256L 0x04312053
PIC32MX230F064D 0x04D05053
PIC32MX575F512L 0x0430F053
PIC32MX150F128B 0x04D06053
PIC32MX675F512L 0x04311053
PIC32MX150F128C 0x04D08053
PIC32MX695F512L 0x04341053
PIC32MX150F128D 0x04D0A053
PIC32MX775F512L 0x04307053
PIC32MX250F128B 0x04D00053
PIC32MX795F512L 0x04307053
PIC32MX250F128C 0x04D02053
PIC32MX250F128D 0x04D04053
PIC32MX170F256B 0x06610053
PIC32MX170F256D 0x0661A053
PIC32MX270F256B 0x06600053
PIC32MX270F256D 0x0660A053
PIC32MX270F256DB 0x0660C053
PIC32MX130F256B 0x06703053
PIC32MX130F256D 0x06705053
PIC32MX230F256B 0x06700053
PIC32MX230F256D 0x06702053

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PIC32
TABLE C-5: PIC32MX330/350/370/430/450/ TABLE C-7: PIC32MX1XX/2XX/5XX 64/100-
470 FAMILY DEVICE IDS PIN FAMILY DEVICE IDS
Part Number Device ID (See Note 1) Part Number Device ID (See Note 1)
PIC32MX330F064H 0x05600053 PIC32MX150F256H 0x06A10053
PIC32MX330F064L 0x05601053 PIC32MX150F256L 0x06A11053
PIC32MX350F256H 0x05704053 PIC32MX170F512H 0x06A30053
PIC32MX350F256L 0x05705053 PIC32MX170F512L 0x06A31053
PIC32MX430F064H 0x05602053 PIC32MX250F256H 0x06A12053
PIC32MX430F064L 0x05603053 PIC32MX250F256L 0x06A13053
PIC32MX450F256H 0x05706053 PIC32MX270F512H 0x06A32053
PIC32MX450F256L 0x05707053 PIC32MX270F512L 0x06A33053
PIC32MX350F128H 0x0570C053 PIC32MX550F256H 0x06A14053
PIC32MX350F128L 0x0570D053 PIC32MX550F256L 0x06A15053
PIC32MX450F128H 0x0570E053 PIC32MX570F512H 0x06A34053
PIC32MX450F128L 0x0570F053 PIC32MX570F512L 0x06A35053
PIC32MX370F512H 0x05808053 PIC32MX120F064H 0x06A50053
PIC32MX370F512L 0x05809053 PIC32MX130F128H 0x06A00053
PIC32MX470F512H 0x0580A053 PIC32MX130F128L 0x06A01053
PIC32MX470F512L 0x0580B053 PIC32MX230F128H 0x06A02053
PIC32MX450F256HB 0x05710053 PIC32MX230F128L 0x06A03053
PIC32MX470F512LB 0x05811053 PIC32MX530F128H 0x06A04053
PIC32MX530F128L 0x06A05053
TABLE C-6: PIC32MZ EMBEDDED
CONNECTIVITY (EC) FAMILY
DEVICE IDS
Part Number Device ID (See Note 1)
PIC32MZ1024ECG064 0x05103053
PIC32MZ1024ECH064 0x05108053
PIC32MZ1024ECM064 0x05130053
PIC32MZ2048ECG064 0x05104053
PIC32MZ2048ECH064 0x05109053
PIC32MZ2048ECM064 0x05131053
PIC32MZ1024ECG100 0x0510D053
PIC32MZ1024ECH100 0x05112053
PIC32MZ1024ECM100 0x0513A053
PIC32MZ2048ECG100 0x0510E053
PIC32MZ2048ECH100 0x05113053
PIC32MZ2048ECM100 0x0513B053
PIC32MZ1024ECG124 0x05117053
PIC32MZ1024ECH124 0x0511C053
PIC32MZ1024ECM124 0x05144053
PIC32MZ2048ECG124 0x05118053
PIC32MZ2048ECH124 0x0511D053
PIC32MZ2048ECM124 0x05145053
PIC32MZ1024ECG144 0x05121053
PIC32MZ1024ECH144 0x05126053
PIC32MZ1024ECM144 0x0514E053
PIC32MZ2048ECG144 0x05122053
PIC32MZ2048ECH144 0x05127053
PIC32MZ2048ECM144 0x0514F053

DS60001145AA-page 72  2007-2021 Microchip Technology Inc.

 PIC32

TABLE C-8: PIC32MZ EMBEDDED TABLE C-9: PIC32MZ GRAPHICS (DA)

CONNECTIVITY WITH FPU FAMILY DEVICE IDS
(EF) FAMILY DEVICE IDS Part Number Device ID (See Note 1)
Part Number Device ID (See Note 1) PIC32MZ1025DAA169 0x05F0C053
PIC32MZ0512EFE064 0x07201053 PIC32MZ1025DAB169 0x05F0D053
PIC32MZ0512EFF064 0x07206053 PIC32MZ1064DAA169 0x05F0F053
PIC32MZ0512EFK064 0x0722E053 PIC32MZ1064DAB169 0x05F10053
PIC32MZ1024EFE064 0x07202053 PIC32MZ2025DAA169 0x05F15053
PIC32MZ1024EFF064 0x07207053 PIC32MZ2025DAB169 0x05F16053
PIC32MZ1024EFK064 0x0722F053 PIC32MZ2064DAA169 0x05F18053
PIC32MZ1024EFG064 0x07203053 PIC32MZ2064DAB169 0x05F19053
PIC32MZ1024EFH064 0x07208053 PIC32MZ1025DAG169 0x05F42053
PIC32MZ1024EFM064 0x07230053 PIC32MZ1025DAH169 0x05F43053
PIC32MZ2048EFG064 0x07204053 PIC32MZ1064DAG169 0x05F45053
PIC32MZ2048EFH064 0x07209053 PIC32MZ1064DAH169 0x05F46053
PIC32MZ2048EFM064 0x07231053 PIC32MZ2025DAG169 0x05F4B053
PIC32MZ0512EFE100 0x0720B053 PIC32MZ2025DAH169 0x05F4C053
PIC32MZ0512EFF100 0x07210053 PIC32MZ2064DAG169 0x05F4E053
PIC32MZ0512EFK100 0x07238053 PIC32MZ2064DAH169 0x05F4F053
PIC32MZ1024EFE100 0x0720C053 PIC32MZ1025DAA176 0x05F78053
PIC32MZ1024EFF100 0x07211053 PIC32MZ1025DAB176 0x05F79053
PIC32MZ1024EFK100 0x07239053 PIC32MZ1064DAA176 0x05F7B053
PIC32MZ1024EFG100 0x0720D053 PIC32MZ1064DAB176 0x05F7C053
PIC32MZ1024EFH100 0x07212053 PIC32MZ2025DAA176 0x05F81053
PIC32MZ1024EFM100 0x0723A053 PIC32MZ2025DAB176 0x05F82053
PIC32MZ2048EFG100 0x0720E053 PIC32MZ2064DAA176 0x05F84053
PIC32MZ2048EFH100 0x07213053 PIC32MZ2064DAB176 0x05F85053
PIC32MZ2048EFM100 0x0723B053 PIC32MZ1025DAG176 0x05FAE053
PIC32MZ0512EFE124 0x07215053 PIC32MZ1025DAH176 0x05FAF053
PIC32MZ0512EFF124 0x0721A053 PIC32MZ1064DAG176 0x05FB1053
PIC32MZ0512EFK124 0x07242053 PIC32MZ1064DAH176 0x05FB2053
PIC32MZ1024EFE124 0x07216053 PIC32MZ2025DAG176 0x05FB7053
PIC32MZ1024EFF124 0x0721B053 PIC32MZ2025DAH176 0x05FB8053
PIC32MZ1024EFK124 0x07243053 PIC32MZ2064DAG176 0x05FBA053
PIC32MZ1024EFG124 0x07217053 PIC32MZ2064DAH176 0x05FBB053
PIC32MZ1024EFH124 0x0721C053 PIC32MZ1025DAA288 0x05F5D053
PIC32MZ1024EFM124 0x07244053 PIC32MZ1025DAB288 0x05F5E053
PIC32MZ2048EFG124 0x07218053 PIC32MZ1064DAA288 0x05F60053
PIC32MZ2048EFH124 0x0721D053 PIC32MZ1064DAB288 0x05F61053
PIC32MZ2048EFM124 0x07245053 PIC32MZ2025DAA288 0x05F66053
PIC32MZ0512EFE144 0x0721F053 PIC32MZ2025DAB288 0x05F67053
PIC32MZ0512EFF144 0x07224053 PIC32MZ2064DAA288 0x05F69053
PIC32MZ0512EFK144 0x0724C053 PIC32MZ2064DAB288 0x05F6A053
PIC32MZ1024EFE144 0x07220053 PIC32MZ1025DAK169 0x08A0C053
PIC32MZ1024EFF144 0x07225053 PIC32MZ1025DAL169 0x08A0D053
PIC32MZ1024EFK144 0x0724D053
PIC32MZ1064DAK169 0x08A0F053
PIC32MZ1024EFG144 0x07221053
PIC32MZ1064DAL169 0x08A10053
PIC32MZ1024EFH144 0x07226053
PIC32MZ1024EFM144 0x0724E053 PIC32MZ2025DAK169 0x08A15053
PIC32MZ2048EFG144 0x07222053 PIC32MZ2025DAL169 0x08A16053
PIC32MZ2048EFH144 0x07227053 PIC32MZ2064DAK169 0x08A18053
PIC32MZ2048EFM144 0x0724F053
PIC32MZ2064DAL169 0x08A19053

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PIC32
TABLE C-9: PIC32MZ GRAPHICS (DA)
FAMILY DEVICE IDS
Part Number Device ID (See Note 1)
PIC32MZ1025DAR169 0x08A42053
PIC32MZ1025DAS169 0x08A43053
PIC32MZ1064DAR169 0x08A45053
PIC32MZ1064DAS169 0x08A46053
PIC32MZ2025DAR169 0x08A4B053
PIC32MZ2025DAS169 0x08A4C053
PIC32MZ2064DAR169 0x08A4E053
PIC32MZ2064DAS169 0x08A4F053
PIC32MZ1025DAK176 0x08A78053
PIC32MZ1025DAL176 0x08A79053
PIC32MZ1064DAK176 0x08A7B053
PIC32MZ1064DAL176 0x08A7C053
PIC32MZ2025DAK176 0x08A81053
PIC32MZ2025DAL176 0x08A82053
PIC32MZ2064DAK176 0x08A84053
PIC32MZ2064DAL176 0x08A85053
PIC32MZ1025DAR176 0x08AAE053
PIC32MZ1025DAS176 0x08AAF053
PIC32MZ1064DAR176 0x08AB1053
PIC32MZ1064DAS176 0x08AB2053
PIC32MZ2025DAR176 0x08AB7053
PIC32MZ2025DAS176 0x08AB8053
PIC32MZ2064DAR176 0x08ABA053
PIC32MZ2064DAS176 0x08ABB053

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 PIC32
TABLE C-12: PIC32MK GENERAL
TABLE C-10: PIC32MX1XX/2XX 28/44-PIN PURPOSE AND MOTOR
XLP FAMILY DEVICE IDS CONTROL (GP/MC) with ECC
Part Number Device ID (See Note 1) FLASH FAMILY DEVICE IDS
PIC32MX154F128B 0x07800053 Part Number Device ID (See Note 1)

PIC32MX154F128D 0x07804053 PIC32MK1024MCM100 0x08B01053

PIC32MX155F128B 0x07808053 PIC32MK1024MCM064 0x08B02053
PIC32MX155F128D 0x0780C053 PIC32MK0512MCM100 0x08B04053
PIC32MX174F256B 0x07801053 PIC32MK0512MCM064 0x08B05053
PIC32MX174F256D 0x07805053 PIC32MK1024GPL100 0x08B07053
PIC32MX175F256B 0x07809053 PIC32MK1024GPL064 0x08B08053
PIC32MX175F256D 0x0780D053 PIC32MK0512GPL100 0x08B0A053
PIC32MX254F128B 0x07802053 PIC32MK0512GPL064 0x08B0B053
PIC32MX254F128D 0x07806053 PIC32MK1024GPK100 0x08B0D053
PIC32MX255F128B 0x0780A053 PIC32MK1024GPK064 0x08B0E053
PIC32MX255F128D 0x0780E053 PIC32MK0512GPK100 0x08B10053
PIC32MX274F256B 0x07803053 PIC32MK0512GPK064 0x08B11053
PIC32MX274F256D 0x07807053 PIC32MK0512MCJ064 0x06300053
PIC32MX275F256B 0x0780B053 PIC32MK0512MCJ048 0x06301053
PIC32MX275F256D 0x0780F053 PIC32MK0512MCJ040 0x06302053
PIC32MK0256MCJ064 0x06304053
TABLE C-11: PIC32MK GENERAL PIC32MK0256MCJ048 0x06305053
PURPOSE AND MOTOR PIC32MK0256MCJ040 0x06306053
CONTROL (GP/MC) FAMILY PIC32MK0512GPH064 0x06308053
DEVICE IDS PIC32MK0512GPH048 0x06309053
PIC32MK0512GPH040 0x0630A053
Part Number Device ID (See Note 1)
PIC32MK0256GPH064 0x0630C053
PIC32MK1024MCF100 0x06201053
PIC32MK0256GPH048 0x0630D053
PIC32MK1024MCF064 0x06202053
PIC32MK0256GPH040 0x0630E053
PIC32MK0512MCF100 0x06204053
PIC32MK0512GPG064 0x06318053
PIC32MK0512MCF064 0x06205053
PIC32MK0512GPG048 0x06319053
PIC32MK1024GPE100 0x06207053
PIC32MK0512GPG040 0x0631A053
PIC32MK1024GPE064 0x06208053
PIC32MK0256GPG064 0x0631C053
PIC32MK0512GPE100 0x0620A053
PIC32MK0256GPG048 0x0631D053
PIC32MK0512GPE064 0x0620B053
PIC32MK0256GPG040 0x0631E053
PIC32MK1024GPD100 0x0620D053
PIC32MK1024GPD064 0x0620E053
TABLE C-13: PIC32MZ W1 WI-FI®
PIC32MK0512GPD100 0x06210053
CONNECTIVITY FAMILY
PIC32MK0512GPD064 0x06211053
DEVICE ID
Part Number Device ID (See Note 1)
PIC32MZ1025W104 0x08C03053

Note 1: The first 4 bits of 32-bit device ID indicates

silicon revision.

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PIC32
APPENDIX D: REVISION HISTORY Revision E (July 2009) (Continued)
• Added the following devices to Table 17-5:
Revision A (August 2007) - PIC32MX565F256H
This is the initial released version of the document. - PIC32MX575F512H
- PIC32MX675F512H
Revision B (February 2008) - PIC32MX795F512H
Update records for this revision are not available. - PIC32MX575F512L
- PIC32MX675F512L
Revision C (April 2008) - PIC32MX795F512L
• Added Notes 1-3 and the following bits to the
Update records for this revision are not available.
DEVCFG - Device Configuration Word Summary
and the DEVCFG3: Device Configuration Word 3
Revision D (May 2008) (see Table 18-1 and Register ):
Update records for this revision are not available. - FVBUSIO
- FUSBIDIO
Revision E (July 2009) - FCANIO
- FETHIO
This version of the document includes the following
additions and updates: - FMIIEN
- FPBDIV[1:0]
• Minor changes to style and formatting have been
incorporated throughout the document - FJTAGEN
• Added the following devices: • Updated the DEVID Summary (see Table 18-1)
- PIC32MX565F256H • Updated ICESEL bit description and added the
FJTAGEN bit in DEVCFG0: Device Configuration
- PIC32MX575F512H
Word 0 (see Register 16-1)
- PIC32MX675F512H
• Updated DEVID: Device and Revision ID register
- PIC32MX795F512H
• Added Device IDs and Revision table (Table 18-4)
- PIC32MX575F512L
• Added MCLR High Time (parameter P20) to
- PIC32MX675F512L Table 20-1
- PIC32MX795F512L • Added Appendix B: “Hex File Format” and
• Updated MCLR pulse line to show active-high Appendix D: “Revision History”
(P20) in Figure 7-1
• Updated Step 7 of Table 11-1 to clarify repeat of Revision F (April 2010)
the last instruction in the step
• The following instructions in Table 13-1 were This version of the document includes the following
updated: additions and updates:
- Seventh, ninth and eleventh instructions in • The following global bit name changes were
Step 1 made:
- All instructions in Step 2 - NVMWR renamed as WR
- First instruction in Step 3 - NVMWREN renamed as WREN
- Third instruction in Step 4 - NVMERR renamed as WRERR
• Added the following devices to Table 17-1: - FVBUSIO renamed as FVBUSONIO
- PIC32MX565F256H - FUPLLEN renamed as UPLLEN
- PIC32MX575F512H - FUPLLIDIV renamed as UPLLIDIV
- PIC32MX575F512L - POSCMD renamed as POSCMOD
- PIC32MX675F512H • Updated the PIC32MX family data sheet
- PIC32MX675F512L references in the fourth paragraph of Section 2.0
“Programming Overview”
- PIC32MX795F512H
• Updated the note in Section 5.2.2 “2-Phase
- PIC32MX795F512L
ICSP”
• Updated address values in Table 17-2
• Updated the Initiate Flash Row Write Op Codes and
instructions (see steps 4, 5 and 6 in Table 13-1)

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 PIC32
Revision F (April 2010) (Continued) • Removed Register 18-1 through Register 18-5.
• Removed Table 17-2
• Added the following devices:
• Removed Section 17.5 “Checksum for PIC32
- PIC32MX534F064H
Devices” and its sub sections
- PIC32MX534F064L
- PIC32MX564F064H • The Flash Program Memory Write-Protect
- PIC32MX564F064L Ranges table was removed (formerly Table 18-4)
- PIC32MX564F128H • Added DEVCFG Locations for PIC32MX1X0 and
- PIC32MX564F128L PIC32MX20X Devices Only (see Table 18-3)
- PIC32MX575F256L • In Section 18.0 “Configuration Memory and
- PIC32MX664F064H Device ID”, removed Table 18-1 and updated
- PIC32MX664F064L Table 18-2: DEVID Summary as Table 18-1
- PIC32MX664F128H • Added the NVMERR bit to the MCHP Status
- PIC32MX664F128L Value table (see Table 19-3)
- PIC32MX675F256H • The following Silicon Revision and Revision ID
- PIC32MX675F256L are added to Table 18-4:
- PIC32MX695F512H
- 0x5 - B6 Revision
- PIC32MX605F512L
- PIC32MX764F128H - 0x1 - A1 Revision
- PIC32MX764F128L • Added a note to the Flash Memory Map (see
- PIC32MX775F256H Figure A-1)
- PIC32MX775F256L • Added Appendix C: “Flash Program Memory
- PIC32MX775F512H Data Sheet Clarification”
- PIC32MX775F512L
Revision J (August 2011)
Revision G (August 2010)
This revision of the document includes the following Note: The revision history in this document
updates: intentionally skips from Revision H to
Revision J to avoid confusing the
• Updated Step 3 in Table 11-1: Download the PE uppercase letter “I” (EY) with the
• Minor corrections to formatting and text have lowercase letter “l” (EL).
been incorporated throughout the document
This revision includes the following updates:
Revision H (April 2011) • All occurrences of VCORE/VCAP have been changed
to VCAP
This version of the document includes the following
additions and updates: • Updated the fourth paragraph of Section 2.0
“Programming Overview”
• Updates to formatting and minor typographical
• Removed the column, Programmer Pin Name, from
changes have been incorporated throughout the
the 2-Wire Interface Pins table and updated the Pin
document
Type for MCLR (see Table 4-2)
• The following devices were added:
• Added the following new devices to the Code
- PIC32MX110F016B Memory Size table (see Table 5-1) and the Device
- PIC32MX110F016C IDs and Revision table (see Table 18-4):
- PIC32MX110F016D
- PIC32MX130F064B
- PIC32MX120F032B
- PIC32MX130F064C
- PIC32MX120F032C
- PIC32MX130F064D
- PIC32MX120F032D
- PIC32MX150F128B
- PIC32MX210F016B
- PIC32MX150F128C
- PIC32MX210F016C
- PIC32MX150F128D
- PIC32MX210F016D
- PIC32MX230F064B
- PIC32MX220F032B
- PIC32MX230F064C
- PIC32MX220F032C
- PIC32MX230F064D
- PIC32MX220F032D
- PIC32MX250F128B
• The following rows were added to Table 17-1: - PIC32MX250F128C
- PIC32MX1X0 - PIC32MX250F128D
- PIC32MX2X0 • Added Row Size and Page Size columns to the
• Added a new sub section Section 17.4.6 Code Memory Size table (see Table 5-1)
“Checksum Values While Device Is Code-
Protected”

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PIC32
Revision J (August 2011) (Continued) • Updated Section 12.2 “With the PE”
• Updated Step 3 in Initiate Flash Row Write Op
• Updated the PGCx signal in Entering Enhanced
Codes (see Table 13-1)
ICSP Mode (see Figure 7-1)
• Updated Step 1 in Verify Device op Codes (see
• Updated the Erase Device block diagram (see
Table 14-1)
Figure 9-1)
• Updated the interval in Section 15.1 “4-wire
• Added a new step 4 to the process to erase a target
Interface” and Section 15.2 “2-wire Interface”
device in Section 9.0 “Erasing the Device”
• Added a note regarding the PE location in
• Updated the MCLR signal in 2-Wire Exit Test
Section 16.0 “The Programming Executive”
Mode (see Figure 15-2)
• Added references to the Operand field throughout
• Updated the PE Command Set with the following
Section 16.2 “The PE Command Set”
commands and modified Note 2 (see Table 16-2):
• Updated the PROGRAM Command Algorithm (see
- PROGRAM_CLUSTER
Figure 16-9)
- GET_DEVICEID
• Updated the mask values for All PIC32MX1XX
- CHANGE_CFG and PIC32MX2XX devices, and DEVCFG3 for all
• Added a second note to Section 16.2.11 devices (see Table 17-1)
“GET_CRC Command” • Updated the DCR value (see Section 17.4.3
• Updated the Address and Length descriptions in the “Calculating for “DCR” in the Checksum
PROGRAM_CLUSTER Format (see Table 16-13) Formula” and Table 17-2)
• Added a note after the CHANGE_CFG Response (see • Updated the Checksum Calculation Process (see
Figure 16-27) Example 17-1)
• Updated the DEVCFG0 and DEVCFG1 values for • Added these new devices to the Code Memory Size
All PIC32MX1XX and All PIC32MX2XX devices in table (see Table 5-1) and the Device IDs and
Table 17-1 Revision table (see Table 18-4):
• The following changes were made to the AC/DC - PIC32MX420F032H - PIC32MX450F128L
Characteristics and Timing Requirements - PIC32MX330F064H - PIC32MX440F256H
(Table 20-1): - PIC32MX330F064L - PIC32MX450F256H
- Updated the Min. value for parameter D111 (VDD) - PIC32MX430F064H - PIC32MX450F256L
- Added parameter D114 (IPEAK) - PIC32MX430F064L - PIC32MX460F256L
- Removed parameters P2, P3, P4, P4A, P5, P8 - PIC32MX340F128H - PIC32MX340F512H
and P10 - PIC32MX340F128L - PIC32MX360F512H
• Removed Appendix C: “Flash Program Memory - PIC32MX350F128H - PIC32MX370F512H
Data Sheet Clarification” - PIC32MX350F128L - PIC32MX370F512L
• Minor updates to text and formatting were - PIC32MX350F256H - PIC32MX440F512H
incorporated throughout the document - PIC32MX350F256L - PIC32MX460F512L
- PIC32MX440F128H - PIC32MX470F512H
Revision K (July 2012) - PIC32MX440F128L - PIC32MX470F512L
- PIC32MX450F128H
This revision includes the following updates:
• Added a Note to Section 18.2 “Device Code
• All occurrences of PGC and PGD were changed to:
Protection bit (CP)”
PGEC and PGED, respectively
• Added the EJTAG Control Register (see
• Updated Section 1.0 “Device Overview” with a list
Register 19-1)
of all major topics in this document
• Updated Section 19.2.4 “ETAP_EJTAGBOOT
• Added Section 2.3 “Data Sizes”
Command”
• Updated Section 4.0 “Connecting to the Device”
• AC/DC Characteristics and Timing Requirements
• Added Note 2 to Connections for the On-chip updates (see Table 20-1):
Regulator (see Figure 4-2)
- Removed parameter D112
• Added Note 2 to the 4-wire and 2-wire Interface Pins
- Replaced Notes 1 and 2 with a new Note 1
tables (see Table 4-1 and Table 4-2)
- Updated parameters D111, D113, D114, D031,
• Updated Section 7.0 “Entering 2-Wire Enhanced
D041, D080, D090, D012, D013, P11, P12 and
ICSP Mode”
P13
• Updated Entering Serial Execution Mode (see
• Minor updates to text and formatting were
Figure 10-1)
incorporated through the document
• Updated step 11 in Section 10.2 “2-wire Interface”

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 PIC32
Revision L (January 2013) Revision M (September 2013)
This revision includes the following updates: This revision includes the following updates:
• The following sections were added or updated: • All references to MIPS Technologies Inc. and
- Section 2.1 “Devices with Dual Flash www.mips.com were updated to Imagination
Panel and Dual Boot Regions” (new) Technologies Limited and www.imgtec.com,
- Section 4.3 “Power Requirements” respectively
- Section 13.0 “Initiating a Flash Row Write” • Updated Section 2.0 “Programming Overview”
- Section 16.1.1 “2-wire ICSP EJTAG RATE” • Updated the last paragraph in Section 5.1.6
“Flash Memory”
• Updated the Device Configuration Register Mask
Values (see Table 17-1) • Updated Code Memory Sizes and added Note 3
(see Table 5-1)
• The following devices were added to the Code
Memory Size table and the Device IDs and Revision • Updated the Erase Device flow diagram (see
table (see Table 5-1 and Table 18-4): Figure 9-1)
- PIC32MZ0256ECE064 - PIC32MZ1024ECF064
• Updated Steps 1, 2, 3 and 5 in Table 11-1
- PIC32MZ0256ECE100 - PIC32MZ1024ECF100 • Added a new paragraph in Section 13.2
- PIC32MZ0256ECE124 - PIC32MZ1024ECF124
“Without the PE”
- PIC32MZ0256ECE144 - PIC32MZ1024ECF144 • Updated Step 2, 3 and 5 in Table 13-1
- PIC32MZ0256ECF064 - PIC32MZ1024ECG064 • Updated the Op code description in Table 16-17
- PIC32MZ0256ECF100 - PIC32MZ1024ECG100 • Updated Device Configuration Mask Values (see
- PIC32MZ0256ECF124 - PIC32MZ1024ECG124 Table 17-1)
- PIC32MZ0256ECF144 - PIC32MZ1024ECG144 • Removed the first sentence in the fourth
- PIC32MZ0512ECE064 - PIC32MZ1024ECH064 paragraph of Section 17.3 “Algorithm”
- PIC32MZ0512ECE100 - PIC32MZ1024ECH100 • Updated Device IDs and Revision (see Table 18-4)
- PIC32MZ0512ECE124 - PIC32MZ1024ECH124
- PIC32MZ0512ECE144 - PIC32MZ1024ECH144 Revision N (April 2014)
- PIC32MZ0512ECF064 - PIC32MZ2048ECG064
This revision includes the following updates:
- PIC32MZ0512ECF100 - PIC32MZ2048ECG100
- PIC32MZ0512ECF124 - PIC32MZ2048ECG124
• Note 2 was updated in TABLE 4-1: “4-wire
Interface Pins”
- PIC32MZ0512ECF144 - PIC32MZ2048ECG144
- PIC32MZ1024ECE064 - PIC32MZ2048ECH064
• Note 2 was updated in TABLE 4-2: “2-wire
Interface Pins”
- PIC32MZ1024ECE100 - PIC32MZ2048ECH100
- PIC32MZ1024ECE124 - PIC32MZ2048ECH124
• The Delay value in Step 5 of Section 9.0
“Erasing the Device” was updated
- PIC32MZ1024ECE144 - PIC32MZ2048ECH144
• The Revision ID and Silicon Revision column
• Note 3 and Note 4 and the GET_CHECKSUM and
was updated and the following devices were
QUAD_WORD_PRGM commands were added to the
added to the Device IDs and Revision table (see
PE Command Set (see Table 16-2)
Table 18-4):
• Added Section 16.2.15 “GET_CHECKSUM
- PIC32MX170F256B - PIC32MX350F256H
Command”
- PIC32MX170F256D - PIC32MX350F256L
• Added Section 16.2.16 “QUAD_WORD_PRO-
- PIC32MX270F256B - PIC32MX430F064H
GRAM Command”
- PIC32MX270F256D - PIC32MX430F064L
• Updated all addresses in DEVCFG Locations
- PIC32MX330F064H - PIC32MX450F128H
(see Table 18-1 and Table 18-2)
- PIC32MX330F064L - PIC32MX450F128L
• Added Configuration Word Locations for
- PIC32MX350F128H - PIC32MX450F256H
PIC32MZ EC Family Devices (see Table 18-3)
- PIC32MX350F128L - PIC32MX450F256L
• Updated Section 18.2 “Device Code Protection
Bit (CP)”
• Updated Section 18.3 “Program Write Protection
Bits (PWP)”
• All references to Test mode were updated to
programming mode throughout the document
• Minor updates to text and formatting were
incorporated through the document

 2007-2021 Microchip Technology Inc. DS60001145AA-page 79

PIC32
Revision P (October 2014) • Parameters D112 (VDD1V8) and D115 (IDD1V8P)
were added to TABLE 21-1: “AC/DC
Note: The revision history in this document
Characteristics and Timing Requirements”
intentionally skips from Revision N to
Revision P to avoid confusing the • Section 4.3 “PIC32MX Power Requirements” was
uppercase letter “O” with the number updated
zero “0”. • Section 4.4 “PIC32MX With VBAT Pin Power
Requirements” was added
The following updates were implemented:
• Section 4.5 “PIC32MZ EC and PIC32MZ EF
• TABLE 5-1: “Code Memory Size” was updated Power Requirements” was added
to include PIC32MK device information
• Section 4.6 “PIC32MZ DA Power Requirements”
• TABLE 18-1: “Device Configuration Register was added
Mask Values of Currently Supported PIC32MX,
• Section 4.7 “PIC32MK Power Requirements”
PIC32MZ and PIC32MK Devices” was updated
was added
to include PIC32MK device information
• Section 5.3.3 “Synchronization” was added
• The original table, Table 18-4: Device IDs and
Revision was removed as this information is • Section 6.7 “Synchronize Pseudo Operation”
readily available in the current Family Silicon was added
Errata • Section 8.1 “4-wire Interface” was updated
• TABLE 19-4: “Configuration Word Locations • Section 8.2 “2-wire Interface” was updated
for PIC32MK family Devices” was added • TABLE 13-1: “Page Erase Op Codes” was
updated
Revision Q (July 2015) • TABLE 18-1: “Device Configuration Register
Mask Values of Currently Supported PIC32MX,
This revision includes the following updates: PIC32MZ and PIC32MK Devices” was updated
• Section 14.0 “Initiating a Flash Row Write” was • Note 1 in the Checksum Formula was updated
added (see Equation 18-1)
• TABLE 18-1: “Device Configuration Register
Mask Values of Currently Supported PIC32MX, Revision S (September 2016)
PIC32MZ and PIC32MK Devices” was updated to
include DEVCFG4 This revision includes the following updates:
• EQUATION 18-1: “Checksum Formula” was • The Programming Interfaces diagram was
updated updated (see Figure 4-1)
• TABLE 19-3: “Configuration Word Locations for • The 4-Wire Interface Pins table was updated (see
PIC32MZ family Devices” was updated to include Table 4-1)
DEVCFG4 • The 2-Wire Interface Pins table was updated (see
• Minor updates to text and formatting were Table 4-2)
incorporated throughout the document • The PIC32MZ DA Power Connections diagram
was updated (see Figure 4-5)
Revision R (April 2016) • The Basic PIC32 Programming Interface Block
Diagram was updated (see Figure 5-2)
This revision includes the following updates: • The Note in Section 5.3.2 “2-phase ICSP” was
• FIGURE 4-1: “Programming Interfaces” was updated
updated • The AC/DC Characteristics and Timing Require-
• TABLE 4-1: “4-wire Interface Pins” was updated ments were updated (see Table 21-1)
• TABLE 4-2: “2-wire Interface Pins” was updated • Device IDs were added (see Table C-1 through
• FIGURE 4-4: “PIC32MZ EC/EF Power Table C-11 in Appendix C: “Device IDs”)
Connections” was updated
• FIGURE 4-5: “PIC32MZ DA Power Connections” Revision T (May 2017)
was updated
This revision includes the following updates:
• TABLE 5-1: “Code Memory Size” was updated
• Updated Table 20-1, Table 4-1, Table 4-2
• FIGURE 5-2: “Basic PIC32 Programming
Interface Block Diagram” was updated • Updated Figure 4-1, Figure 4-2, Figure 5-2
• FIGURE 16-1: “4-wire Exit Programming Mode” • Added Table C-12
was updated • Minor updates to text and formatting were
• FIGURE 16-2: “2-wire Exit Programming Mode” incorporated throughout the document
was updated

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 PIC32
Revision U (July 2017) Revision X (November 2019)
This revision includes the following updates: This revision includes the following updates:
• Updated the PIC32MK devices (see Section 2.1 • Added a new note to 18.1 “Theory” that applies
“Devices with Dual Flash Panel and Dual Boot to PIC32MKXXXXGPD/GPE/MCFXXX devices
Regions”) • Updated TABLE 18-1: “Device Configuration
• Updated the PIC32MK devices in Code Memory Register Mask Values of Currently Supported
Size (see Table 5-1) PIC32MX, PIC32MZ and PIC32MKxxxxGPD/
• Updated the PIC32MK devices in Device Configu- GPE/MCFxxx Devices” with
ration Register Mask Values of Currently Sup- PIC32MKXXXXGPD/GPE/MCFXXX device infor-
ported PIC32MX, PIC32MZ and PIC32MK mation
Devices (see Table 18-1) • Updated EQUATION 18-1: “Checksum For-
• Updated the Configuration Word Locations for mula” with PIC32MKXXXXGPD/GPE/MCFXXX
PIC32MK Family Devices (see Table 19-4) device information
• Added TABLE 19-5: “Configuration Word Loca-
tions for PIC32MKXXXXXXH/G/J/K/L/MXX Revision Y (September 2020)
Family Devices”
This revision includes the following updates:
• Updated the PIC32MK General Purpose and
Motor Control (GP/MC) Family Device IDs (see • Added Section 4.8 “PIC32MZ W1 Power
Table C-11) Requirements”
• In additions, minor updates to text and formatting • Updated Section 5.1.6 “Flash Memory” with
were incorporated throughout the document PIC32MZ W1 device information
• Updated Table 5-1 with PIC32MZ W1 device
Revision V (July 2018) information
• Added a note to Table 5-1 that applies to
This revision includes the following updates: PIC32MZ W1 devices
• In Table 18-1: Renamed PIC32MK0256/ • Updated Table 18-1 with PIC32MZ W1 device
0512XXG/H to PIC32MK0256/0512XXH/G/J. information
Also, updated Device Configuration Register • Added Section 19.1.1 “Device Configuration
Mask Values for PIC32MK0512/1024XXK/L/M for PIC32MZ W1 devices” that applies to
and PIC32MK0512/1024XXH/G/J PIC32MZ W1 devices
• In Table 19-5: Renamed family name from • Added Table 19-6 with DEVCFG locations for
PIC32MKXXXXXXG/H/K/L/MXX to PIC32MZ W1 devices
PIC32MKXXXXXXH/G/J/K/L/MXX • Added Table C-13 with PIC32MZ W1 Wi-Fi Con-
• In Table C-11: Removed references to nectivity Family Device ID
PIC32MKXXXXMCM/GPL/GPKXXX and
PIC32MKXXXXMCH/GPGXXX Revision AA (July 2021)
• In Table C-12: Rearranged PIC32MKXXXX/MCM/
GPL/GPKXXX devices. Added PIC32MKXXXX- This revision includes the following update:
MCJ/GPH/GPGXXX devices • Updated Table 19-6 with new physical address.
• A note reference to the revision ID has been
added from Table C-1 to Table C-12, which identi-
fies the revision ID field within 32-bit device ID.

Revision W (October 2018)

This revision includes the following updates:
• Added note below Table 13-1 and Table 14-1
• Table C-13 content has been moved to Table C-9

 2007-2021 Microchip Technology Inc. DS60001145AA-page 81

PIC32

DS60001145AA-page 82  2007-2021 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specifications contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip
devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications
contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished
without violating Microchip's intellectual property rights.

• Microchip is willing to work with any customer who is concerned about the integrity of its code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or
other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication is provided for the sole Trademarks

purpose of designing with and using Microchip products. Infor- The Microchip name and logo, the Microchip logo, Adaptec,
mation regarding device applications and the like is provided AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
only for your convenience and may be superseded by updates. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
It is your responsibility to ensure that your application meets LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
with your specifications. Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
MICROCHIP MAKES NO REPRESENTATIONS OR WAR- SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A. and
WRITTEN OR ORAL, STATUTORY OR OTHERWISE, other countries.
RELATED TO THE INFORMATION INCLUDING BUT NOT
LIMITED TO ANY IMPLIED WARRANTIES OF NON- AgileSwitch, APT, ClockWorks, The Embedded Control Solutions
INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight
PARTICULAR PURPOSE OR WARRANTIES RELATED TO Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3,
Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-
ITS CONDITION, QUALITY, OR PERFORMANCE. Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, WinPath, and ZL are registered
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- trademarks of Microchip Technology Incorporated in the U.S.A.
RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN-
TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
WHATSOEVER RELATED TO THE INFORMATION OR ITS Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky,
BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive,
USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net,
BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES Dynamic Average Matching, DAM, ECAN, Espresso T1S,
ARE FORESEEABLE. TO THE FULLEST EXTENT EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP,
ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON INICnet, Intelligent Paralleling, Inter-Chip Connectivity,
ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi,
MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,
OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
FOR THE INFORMATION. Use of Microchip devices in life sup- Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O,
port and/or safety applications is entirely at the buyer's risk, and simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI,
the buyer agrees to defend, indemnify and hold harmless SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total
Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY,
Microchip from any and all damages, claims, suits, or expenses ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks
resulting from such use. No licenses are conveyed, implicitly or of Microchip Technology Incorporated in the U.S.A. and other
otherwise, under any Microchip intellectual property rights countries.
unless otherwise stated.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.

© 2007-2021, Microchip Technology Incorporated, All Rights

Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality. ISBN: 978-1-5224-8373-1

 2007-2021 Microchip Technology Inc. DS60001145AA-page 83

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DS60001145AA-page 84  2007-2021 Microchip Technology Inc.

02/28/20