IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO.

11, NOVEMBER 2018 5111

A Novel Method of Discrete-Time Signal

Amplification Using NEMS Devices
Sivaneswaran Sankar , Student Member, IEEE , Mayank Goel,
Maryam Shojaei Baghini, Senior Member, IEEE,
and V. Ramgopal Rao, Fellow, IEEE

Abstract — In this paper, we propose a novel tech-

nique of realizing discrete-time (D-T) signal amplifica-
tion using Nano-Electro-Mechanical systems (NEMS). The
amplifier uses mechanical switches instead of traditional
solid-state devices and acts as an inherent sample and
hold amplifier. The proposed NEMS D-T amplifier operates
on a wide dynamic range of signals without consuming
the dc power. Moreover, the proposed amplifier does not
suffer from the leakage current and the nonlinearity asso-
ciated with the sampling ohmic switch. As a proof of con-
cept, the proposed NEMS D-T amplifier is demonstrated in Fig. 1. (a) Traditional switched capacitor amplifier using op-amp. (b) D-T
circuit simulations using the calibrated verilog-A models MOS parametric amplifier circuit. (c) Sample phase. (d) Hold phase.
of the NEMS device. The simulated amplifier achieves a
gain of ∼5, handles the maximum differential input signal
of 0.65 V, and consumes only 0.6 µW of power for a sampling are present in analog-to-digital converters (ADC), digital-to-
frequency of 100 kHz. The nonidealities present in the
proposed amplifier are highlighted and possible ways to analog converters, and dc–dc voltage converters. The most
overcome them are discussed. Finally, the design consid- common signal processing function needed is the ampli-
erations required for the NEMS D-T amplifier are described. fication. In D-T systems, the amplification is traditionally
Index Terms — Nano-Electro-Mechanical (NEM) capac- implemented using the operational amplifier (op-amp)-based
itive switch, NEM ohmic switch, parametric amplifier, circuits [7], of which an example is shown in Fig. 1(a).
switched capacitor circuits In the sampling phase (1 ), the input “Vin ” is sampled
across capacitor C1 . In the hold phase (2 ), the charge
I. I NTRODUCTION “C1 Vin ” present in capacitor C1 is transferred to the
capacitor C2 by the op-amp. Hence, if C1 > C2 , one can obtain
T HE development of integrated circuits using mechanical
switch has attracted significant interest in the recent
years due to its high ratio of resistance in the OFF-state and
a voltage gain equal to C1 /C2 . Limitations of the op-amp
(finite open-loop dc gain and bandwidth, voltage swing limit,
ON -state. Hence, Nano-Electro-Mechanical (NEM) switches nonlinearity, and noise) greatly influence the performance of
helps in reducing the energy consumption of the the amplifier, while it is also the most power hungry block
system [1]–[3]. In [4], the MEMS resonator was used of the circuit. Moreover, metal–oxide–semiconductor (MOS)
for harnessing the vibration energy. Continuous-time signal switches used for the sampling and charge transfer suffer from
amplification utilizing the parametric effect of MEMS the charge injection problem and nonlinear ON -resistance,
capacitor is demonstrated in [5]. MEMS switch as an analog which affect the overall performance [7]. The key idea in
transconductance element is proposed in [6]. switched capacitor amplifier is as follows: sample the input
Analog signals from the real world are processed through voltage across a large capacitor and dump the same charge on
discrete-time (D-T) systems before being digitized. As an to a smaller capacitor. Hence, the input voltage gets amplified
example of D-T system, the switched capacitor networks by a factor equal to the ratio of capacitances.
In [8], the MOS capacitor is utilized for D-T signal amplifi-
Manuscript received May 23, 2018; revised August 17, 2018; accepted cation as shown in Fig. 1(b). The input is sampled at 1 across
August 26, 2018. Date of publication September 14, 2018; date of current
version October 22, 2018. The review of this paper was arranged by the largest capacitance available in a MOS capacitor, i.e., oxide
Editor R. M. Todi. (Corresponding author: Sivaneswaran Sankar.) capacitance “COX ” in strong inversion, as shown in Fig. 1(c).
S. Sankar, M. S. Baghini, and V. R. Rao are with the Department In the hold phase (2 ), the gate terminal is left floating and
of Electrical Engineering, IIT Bombay, Mumbai 400076, India (e-mail:
[email protected]; [email protected]; [email protected]). an external voltage source (VPULL ) is used to remove all the
M. Goel is with Intel Corporation, 85579 Neubiberg, Germany (e-mail: inversion layer charges from the channel as shown in Fig. 1(d).
[email protected]). Thus, gate-to-body capacitance becomes series connection
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. of COX and CDEP (depletion capacitance), which becomes
Digital Object Identifier 10.1109/TED.2018.2867547 approximately equal to CDEP . Hence, the gate-to-body

0018-9383 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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 5112 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 11, NOVEMBER 2018

TABLE I
E XTRACTED PARAMETERS OF NEMS C APACITIVE S WITCH

Fig. 2. (a) Schematic of NEMS capacitive switch. (b) Switch in off-state

and on-state.

capacitance is reduced while keeping the gate charge constant,

thus amplifying the input voltage at the gate by a factor
of COX /CDEP .
The achievable gain using the MOS capacitor-based
D-T amplification is typically within the range of 5–10 [8].
For obtaining a determined gain, the MOS device needs to
be biased and the input signal is applied over the bias. In the
hold phase, the dc bias also gets amplified, which causes the
gate voltage to elevate to higher values. This puts a restriction Fig. 3. Simulated characteristics of NEMS capacitive switch using the
calibrated verilog-A model. (a) C–V curve. (b) Transient characteristics.
on the voltage swing limits and causes reliability issues.
In a differential implementation, even for low gain (using
low dc bias), the input swing is limited, since VBIAS ± Vin+
should be high enough to create a strong inversion. Moreover,
VPULL [Fig. 2(c)] has to be high enough such that the amplified
gate voltage should not cause the channel inversion during 2 .
In this paper, two types of NEMS devices are used: NEMS
capacitive switch and NEMS ohmic switch. NEMS device
due to its movable mass creates a capacitance that varies
with the displacement. The variable capacitance of the NEMS
capacitive switch is used for amplifying the signal. The
ON -resistance of the NEMS ohmic switch is highly linear
and the switch operation does not suffer from the charge Fig. 4. (a) Side view of NEMS ohmic switch. (b) Top view of the switch. (c)
injection problem. Therefore, the NEMS ohmic switch is used Cross section of the switch along A–A’ during OFF-state and ON-state.
for the sampling and charge transfer. The proposed NEMS
D-T amplifier circuit is verified using circuit simulations
beam gets pulled in and the switch is closed, otherwise it is
deploying calibrated verilog-A model of the NEMS device.
open. For the ON-condition, the applied voltage |V | >VPI, C
This paper is organized as follows. In Section II, the NEMS
(pull-in voltage) and for the OFF-condition, |V |<VPO,C (pull-
devices used in this paper are described and their charac-
out voltage). Fig. 2(b) depicts the OFF-state and ON-state of
teristics are presented. Section III describes the principle
the switch, respectively.
of operation of the NEMS D-T amplifier. In Section IV,
The NEMS capacitive switch described in Fig. 2 is designed
the details of the amplifier along with the simulation results
in CoventorWare (FEM CAD tool) [9] for the purpose of the
are presented. Nonidealities present in the amplifier are dis-
accurate extraction of its relevant parameters that are provided
cussed in Section V. The design guidelines required for the
in Table I. The verilog-A model [10] of the NEMS capacitive
NEMS D-T amplifier are provided in Section VI, followed by
switch is calibrated to match the results from CoventorWare
conclusions in Section VII.
and is then subsequently used for the circuit simulation. The
C–V curve and transient characteristics of the NEMS capac-
II. D ESCRIPTION OF THE NEMS S WITCH itive switch using the calibrated verilog-A model are plotted
A. NEMS Capacitive Switch in Fig. 3(a) and (b).
Structure of the NEMS capacitive switch and its practi-
cal designed dimensions are shown in Fig. 2(a). The beam B. NEMS Ohmic Switch
clamped at the two ends forms the top plate of the capacitor. The side view and top view of the NEMS ohmic switch
Between the top plate and the bottom plate, there is a bilayer along with its dimensions are shown in Fig. 4(a) and (b),
consisting of air and a dielectric layer (εd ). If the electrostatic respectively. The cantilever beam fixed at one end forms
attractive force (due to applied voltage) between the two plates the gate terminal, to which the floating channel is attached
is higher than the spring restoring force of the beam, then the through the dielectric material. The electrostatic attractive

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 SANKAR et al.: NOVEL METHOD OF D-T SIGNAL AMPLIFICATION USING NEMS DEVICES 5113

TABLE II
E XTRACTED PARAMETERS OF NEMS O HMIC S WITCH

Fig. 7. Amplifier circuit during the sample phase.

Fig. 8. Amplifier circuit in (a) beginning of hold and (b) middle of hold
phase.

Fig. 5. Simulated characteristics of NEMS ohmic switch using the

calibrated verilog-A model (a) I–V curve. (b) Transient characteristics.

Fig. 9. Amplifier circuit in the final stage of amplification in the hold

phase.

in the top plates of the capacitors is given by Q TOTAL =

C ON (Vin + VBIAS ) + C ON (Vin − VBIAS ). There will be a transfer
of charge between C A (left side) and C B (right side) due to
the potential difference. Therefore, the charges due to VBIAS
Fig. 6. Simplified circuit of the NEMS D-T amplifier. get canceled.
Step 3: The total charge in the top plates is now given
force between the gate and the body sets the state of the
by Q TOTAL = 2 × C ON (Vin ) since the two capacitors are in
switch. For the ON-condition, |VGB |>VPI,R (pull-in voltage)
parallel [Fig. 8(b)]. It is assumed Vin is less than the pull-out
and for the OFF-condition, |VGB | < VPO,R (pull-out voltage).
voltage of the NEMS capacitive switch (VPO,C ).
Fig. 4(c) depicts the switch in OFF -state and ON-state, respec-
Step 4: Since Vin < VPO,C , the beams get released due
tively. The relevant parameters of the switch extracted from
to the fact that the spring restoring force is now stronger
CoventorWare are provided in Table II. I –V characteristic
than the electrostatic force between the plates. As a result,
curve and the transient characteristics of the NEMS ohmic
the value of capacitors C A and C B is reduced to C OFF as
switch using the calibrated verilog-A model are plotted
indicated in Fig. 9. For the charge conservation to hold,
in Fig. 5(a) and (b).
Q TOTAL = 2 × C OFF (Vout ) = 2 × C ON (Vin ). Thus, Vin is
amplified and the theoretical gain ( A V ) of the NEMS D-T
III. P RINCIPLE OF NEMS D-T A MPLIFICATION
amplifier is given in the following equation:
Consider the schematic of the NEMS D-T amplifier shown
Vout C ON
in Fig. 6. “VBIAS ” and “Vin ” correspond to the dc bias and AV = = . (1)
the input signal of the amplifier, with Vin < VBIAS . Let us Vin C OFF
assume two voltages “Vin + VBIAS ” and “Vin − VBIAS ” are
available. In the next section, the technique of generating them IV. I MPLEMENTATION OF NEMS D-T A MPLIFIER
is described. The mechanism of amplification is as follows. The implementation of the NEMS D-T amplifier in the
Step 1: During the sample phase (1 ), the voltages “Vin + Cadence Spectre circuit simulator is given in Fig. 10. The
VBIAS ” and “Vin − VBIAS ” are sampled across the two NEMS NEMS capacitive and ohmic switches are implemented using
capacitive switch as shown in Fig. 7. If |Vin ± VBIAS | > VPI,C , the calibrated verilog-A models as discussed in Section II.
the beams get pulled in due to the always attractive nature of To obtain a voltage equal to Vin+ ± VBIAS , two large capacitors
the electrostatic forces. Hence, C A = C B = C ON , which is (normal parallel plate devices) are used to sample the volt-
of relatively high value (the flat part in Fig. 3). The voltages age VBIAS (with appropriate polarity) during the hold phase
are sampled and stored across C A and C B . The top plate of (forming two floating dc sources) and add them in series with
C B has negative charges, since Vin < VBIAS . the input signal during the sample phase. The clock signals
Step 2: In the hold phase (2 ), the moment at which the (1 , 2 ) are entirely nonoverlapping with each other. The
two capacitors are shorted is depicted in Fig. 8(a). Total charge clock frequency ( f CLK ), dc bias (VBIAS ), and Clarge are chosen

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 5114 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 11, NOVEMBER 2018

Fig. 10. Circuit implementation of the NEMS D-T amplifier.

Fig. 12. (a) Sampled and amplified sinusoidal input (fIN = 5 kHz, fCLK =
100 kHz) using differential NEMS D-T amplifier. (b) Transient waveforms
depicting the loaded gain in the modified NEMS D-T amplifier (V+ in =
0.2 V, VBIAS = 4 V).

Fig. 11. Transient simulation waveforms of the NEMS D-T amplifier using Fig. 13. (a) Parasitic capacitances in the NEMS ohmic switch. (b) Mod-
Cadence Spectre for V+ in = 0.2 V, VBIAS = 4 V, and fCLK = 100 kHz.
ified NEMS D-T amplifier.

beam of the NEMS capacitive switch to displace and change

to be 100 kHz, 4 V, and 30 pF, respectively, throughout this the value of capacitance during the end of the hold phase.
paper. From Fig. 3(a), we observe that the capacitance of the NEMS
As an example, assume Vin+ to be a dc signal equal capacitive switch varies with its terminal voltage in a weak
to 0.2 V (Fig. 10). Fig. 11 shows the corresponding tran- fashion until the pull-in point is reached. Hence, the capaci-
sient waveforms of the D-T amplifier. In the sample phase, tance of the NEMS capacitive switch during the hold phase
“0.2 V + 4 V” is sampled across C A and “0.2 V − 4 V” is (at the end of the amplification), i.e., C OFF , is a function of
sampled across C B . In the hold phase, the voltages V A+ and the output voltage. The plot of gain (denoted in red color)
V B+ are equal to 1 V as shown in Fig. 11, thus providing versus input signal amplitude shown in Fig. 14(a) indicates
a gain equal to 5. The capacitance of the NEMS capacitive the reduction in gain by 4.7% for an increase in the input
switch and the displacement of the beam during the sample amplitude from 1 to 325 mV.
and hold phase are clearly depicted in Fig. 11.
The bias voltage (VBIAS ) of the amplifier does not appear B. Parasitic Capacitances of NEMS Ohmic Switch
at the nodes V A+ and V B+ at the end of hold phase.
The other non-ideality is the presence of parasitic capaci-
Hence, only the amplified signal will appear as an input to
tances in the NEMS ohmic switch. The parasitic capacitance
the subsequent stages, e.g., CMOS buffer, and thus proper
model of the NEMS ohmic switch is described in Fig. 13(a).
dc voltage isolation is achievable. For a sinusoidal input signal,
The parasitic capacitances load the capacitance C A and C B ,
the sampled and amplified differential output waveform are
and share their charge. To reduce the clock feedthrough due to
plotted in Fig. 12(a). The differential outputs were generated
the gate-to-source and gate-to-drain capacitances of the ohmic
by taking the difference between the outputs of the two
switch [7], the clock signal can be applied to the body terminal
separate amplifiers having inputs as Vin+ and Vin− , respectively.
instead of gate terminal as indicated in Fig. 13(b).
Furthermore, using multiple NEMS capacitive switches in
V. N ON - IDEALITIES IN NEMS D-T A MPLIFIER parallel as shown in Fig. 13(b), will lower the gain reduction.
A. Non-linearity The loaded gain for the modified NEMS D-T amplifier with
10 parallel switches [Fig. 13(b)] is now given in the following
Two of the major non-idealities present in the NEMS
equation:
D-T amplifier are identified and discussed as follows. The first
one being the variation of gain with input signal amplitude. (10 × C ON ) + CGS(D),ON + CGS(D),OFF
A V ,loaded = . (2)
This is because, the amplified signal (Vout ) will cause the (10 × C OFF ) + CGS(D),ON + CGS(D),OFF

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 SANKAR et al.: NOVEL METHOD OF D-T SIGNAL AMPLIFICATION USING NEMS DEVICES 5115

the practical gain is 5.1 (=6.63 fF/1.3 fF). The maximum

achievable voltage gain is limited by the fabrication process
of the NEMS switch.
 
go εd
AV,practical = 1 + × γ. (5)
td

B. Voltage Range
The input and output voltage swings needed in the amplifier
determine the condition on the pull-in (VPI,C ) and the pull-
out voltages (VPO,C ) of the NEMS capacitive switch. The
following equations describe the conditions:
VBIAS ≥ VPI,C + Vin,max (6)
Fig. 14. (a) Variation of gain with respect to the input signal amplitude.
(b) Ratio of VPO,C /VPI,C versus the amplifier gain. Vout,max < VPO,C . (7)
The condition given in (6) ensures that both the NEMS
In (2), CGS(D),ON and CGS(D),OFF represent the parasitic capacitive switches are pulled in during the sampling phase.
capacitance between the gate and the source/drain terminal The condition given in (7) ensures that the NEMS capacitive
in the NEMS ohmic switch during ON -state and OFF-state, switches are pulled out during the hold phase. The expression
respectively. They load the capacitances C A and C B during of VPI,C and VPO,C for the NEMS capacitive switch is given
both the phases. The values of CGS(D),ON and CGS(D) , OFF are in the following equation [11]:

1 fF and 0.13 fF, respectively. Hence, the loaded gain for the  3 
 8K td 
modified NEMS D-T amplifier is equal to 4.77. Fig. 12(b)  eff go + εd  2K eff go td2
shows the waveforms of the modified NEMS D-T amplifier VPI,C = ; VPO,C =  (8)
27εo A εd2 εo A
for a 0.2-V input dc signal, confirming the reduction in loaded
gain. The NEMS D-T amplifier could also be co-designed by where K eff is the effective spring constant of the beam and
including the parasitic capacitances of the ohmic switch for “A” is the overlap area that is given by W × L B [Fig. 2(a)].
obtaining the gain. Based on (4) and (8), the expressions for VPI,C and VPO,C are
The variation of gain (denoted in blue color) with the input given by the following equations:
amplitude for the modified NEMS D-T amplifier [Fig. 13(b)]  

is shown in Fig. 14(a). The gain reduces by 5.4% at an input  A V td 3  K eff
 
amplitude of 325 mV. If the differential gain is considered, VPI,C = α1 (9)
εd A
then the effect of non-linearity in the gain is considerably 
 
reduced due to the cancelation of even order non-linear terms.    K
 t 3  eff
This is evident in the plot of gain (denoted in black color) in
VPO,C = α2  A V −1
d
. (10)
Fig. 14(a) for the differential implementation of the modified εd A
NEMS D-T amplifier, where the gain reduces only by 2%
(at 325-mV input). In (9) and (10), α1 and α2 are given by (8/27εo )1/2
and (2/εo )1/2 , respectively. For the NEMS capacitive switch
VI. D ESIGN C ONSIDERATIONS FOR considered in this paper, the term (K eff /A) is given in (11),
NEMS D-T A MPLIFIER where “E” is Young’s Modulus of the beam material. The
A. Voltage Gain term (K eff /A) is dependent on the structure of the switch and
can be controlled independently without affecting the gain.
The gain of the amplifier depends on the value of C ON and Based on the maximum output voltage swing needed, (K eff /A)
C OFF of the NEMS capacitive switch and is given in (3). The can be used to set the VPO,C . The terms VPI,C and VPO,C are
theoretical voltage gain (A V ) is defined in (4). interrelated with each other. This is quantified in (12), which
εo εd A εo A provides the ratio of VPO,C /VPI,C as a function of the amplifier
C ON = ; C OFF =   (3)
td go + εtdd gain. Hence, when the term (K eff /A) is used to set VPO,C ,
C ON go εd VPI,C is also fixed.
AV = =1+ . (4)  
C OFF td K eff 32E t 3
≈ (11)
The switch parameters go , t D , and ε D (Fig. 3) determine the A L B L3
gain. In reality, the presence of parasitic fringe capacitances  
VPO,C α2 AV − 1
and the curvature of the beam causes the gain to reduce from = (12)
VPI,C α1 A3V
the theoretical value. This effect is presented by including
parameter γ (γ < 1) in the description for the practical gain As the gain increases, the ratio of VPO,C /VPI,C falls due
as given in (5). For the NEMS capacitive switch considered to the increment in the hysteresis window of the NEMS
in this paper, the theoretical gain possible is 10.36, but capacitive switch [Fig. 14(b)]. Hence, it is desirable to have

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 5116 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 11, NOVEMBER 2018

TABLE III
P ERFORMANCE C OMPARISON OF THE NEMS D-T A MPLIFIER

a capacitive switch with low hysteresis so as to increase the of the modified NEMS D-T amplifier, the power dissipated in
usable range of the amplifier. Finally, the bias voltage (VBIAS ) the amplifier (PAmp ) and the power dissipated in driving the
required for the amplifier is chosen to satisfy the condition switches (Psw ) are given by (14) and (15), respectively.
required for the pull in, based on maximum Vin as given 2
PAmp = 2 × (20C ON + 4CGS(D),ON + 4CGS(D),OFF )VBIAS f CLK
in (6). The NEMS switches in this paper are chosen to keep
the structure simple enough. The design procedure discussed (14)
2
in this section can be extended to different structures of the Psw = 2 × (6CPAR,ON + 3CGB,ON )VGB f CLK . (15)
switch as well.
In (14), CPAR,ON (= CGS,ON + CGD,ON + CGB,ON ) is the
total parasitic capacitance looking into the gate terminal of
C. Scaling and Process Integration
the NEMS ohmic switch in the ON-state. Some amount of
If all the geometrical parameters of the NEMS capacitive power (Pclk ) is dissipated in the nonoverlap clock generator
switch in the proposed D-T amplifier are scaled by a factor “,” circuit. Hence, the total power dissipation is given by PAmp +
then the voltage gain remains unchanged and the switch Psw + Pclk . For the differential implementation of the modified
parameters VPI,C , VPO,C , C ON , C OFF , and TMech are linearly NEMS D-T amplifier, the total power consumption is 0.6 μW.
scaled by “” as given in the following equation:
f n =  × f n . (13) E. Performance Comparison
Table III compares the performance of NEMS D-T amplifier
In (13), the terms f n and f n represent the parameters before
with the op-amp and metal-oxide-semiconductor capacitor-
and after scaling, respectively. The scaling of the NEMS
based D-T amplifier. As we see from the table, the proposed
ohmic switch follows a similar trend. The downscaling of
NEMS D-T amplifier handles a maximum differential input
the vertical dimensions (beam and airgap) of the switch poses
signal of 0.65 V and consumes only 0.6 μW of power for a
fabrication challenges. However, the tremendous progress in
sampling frequency of 100 kHz.
the NEMS fabrication has resulted in low voltages, low
footprint [12], [13] along with considerable improvement in
VII. C ONCLUSION
the reliability of scaled switches [14], [15]. NEMS switches of
the proposed D-T amplifier can be integrated with the CMOS In this paper, we have presented a technique of realizing
die on the same substrate using wire bonds or at the package a D-T signal amplification using NEMS devices and sub-
level. Recent approaches of the integration include the direct sequently verified the same using the calibrated verilog-A
realization of NEMS structures at the CMOS back-end-of-line models. The presented NEMS D-T amplifier opens up a new
level [16] and 3-D ICs [17]. avenue for utilizing NEMS switches in analog applications,
which further motivates the development of low voltage and
low-footprint devices. In the Internet of Things (IoT) sensor
D. Power Dissipation nodes, the output signal of the sensor is typically of low
The power dissipation in the NEMS D-T-amplifier is amplitude and bandwidth. This paper shows the proposed
entirely dynamic in nature. For a differential implementation NEMS D-T amplifier can receive signals as low as 1 mV

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 SANKAR et al.: NOVEL METHOD OF D-T SIGNAL AMPLIFICATION USING NEMS DEVICES 5117

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