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Digital logic gates and Boolean function

The document outlines objectives related to understanding various logic gates (AND, OR, NOT, NAND, NOR, XOR) and their applications in digital circuits using Boolean algebra and truth tables. It also includes equipment needed for experiments, such as specific integrated circuits, and discusses the fundamental principles of digital logic design and analysis. Additionally, it addresses practical considerations for implementing circuits and troubleshooting power supply issues.

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adnannafis2001
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0% found this document useful (0 votes)
5 views

Digital logic gates and Boolean function

The document outlines objectives related to understanding various logic gates (AND, OR, NOT, NAND, NOR, XOR) and their applications in digital circuits using Boolean algebra and truth tables. It also includes equipment needed for experiments, such as specific integrated circuits, and discusses the fundamental principles of digital logic design and analysis. Additionally, it addresses practical considerations for implementing circuits and troubleshooting power supply issues.

Uploaded by

adnannafis2001
Copyright
© © All Rights Reserved
Available Formats
Download as PDF or read online on Scribd
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Objectives: * Leann cbout the AND, OR, NOT, NAND, NOR, and xOR gees: + Leann how truth ables , Aogie graphs and Boolean algebna can be ysed to show how Boolean Punctiong vsoak. + Use the “associative Law” to show that the input of AND and OR gotes treve the seme tongth + Get to Know what aombinetional dogie cineuits ana Equipment list : + I¢@ 7400 Quednuple Q- input NAND getes +12 7402 Quadauple Q-input NOR gets + 1¢ 7404 Hex Inventory (NOT gates) Ie F408 Quadnuple 9- input AND gertes + IG 732 Quadnuple Q- input OR gates Td 7496 Gusdnuple 2- inp x0R gates + Thainen boand + Wines ™ Theony + Basie building blocks off digital cineuits ano lage gatet. They proaets one on mone ogiaal inputs to produce one logieal output. Digital dogia goter opencte ot tio voltage lovely, O (logicol Low) and 4, Boslecn algcbng is a type of mathemetaal neasoning thok desariber the neletlonship between vanicbler that acn be true on false, which ane nepresented by the numbeng 1 and 0. Gt is a key pant oP how digital gedgels ane meade. Bodlean Punctiong ane oPter used fo descille digital computing notwonke. The truth mumbey are shown by APPerert voltage tevele, Postulakes b Theonoms Name AtO=A ALE A Idertity [ AtA = AVN 20 At A ZA AAs A wy’. Involuction A+®= BA AQ= BA Commudetive At Ge) = Gro)+?e A(Qe) = Age Associative __AG@4e) = ABt AC Aave= Gr0) (AVC) Distributive | _ @0)'= W0" (ABY = Alto’ | De Mongan | At AB A ACAHB) =A Absonption | 7 A Anath table shows all output Logie aineutt fon eveny possible aombinaction of inpuk . Combinction Logie 16 @ type oft digital nehaonk im which He oul depends only on the aunnent input and not ov the stale of the netuonk in the park Anclyaing combinction Logie nequines uanicting Boolean Sunections and Aruth tables Bon each inet component All tnucth | tees must be combined ty produce the output. Ginait Diagnam Sale ae bh =D>- >>- 2p Figane + Pin conPigueations oP gates in ICs Figure: Exchension of taps ofr ANP ond OR gets aes) ye A re, ee eel [i aes Figure : Logie Diagnam fon the given Boolean Function Results. Trt | AND oR | NAND | yor | NOR (Ineut | NOT AO | F=A:8 | FeMO| Fs RO | Fs A@G) Fe AG) | A be oo 6 (O 0 i ej) | oO ' ole | 3 | o | \ ° io =o dt 7c o | u [fae =} | oe eee ee of 9=.J Table: Truth Table of Logie Gates Table: Toth Tables Poe S-input AND and oR _F2 AG¢= Qa)-¢ . [eit s Ge)ie Fable: Expnesing S-input gates as Q-input gates 8 & 6 using Associative daw ls aa 7 | | ABC |T,2A'C) Ips Ag 1,26¢ |Fel4L+1, | 000 ° 61-6 eS | | oot ' ° | ° | t | joe | o | o o| o | fo | gt} o | os] 1 [aa | ° 1 o. 1 fade Se hag \ t + 1. juelo [ol] o ° [et ° ° i | 1 Table . Toth Table fon the given Boolean Function Diseussion + The experiment on % Digital Logie Gates end Boolean Functions” senves as an intagnated gppnoach to provide honds-on experience with Logie. geter and — Booleon algebra by which we. gen essential insighy into the design , analysis , and application OF digital aincuity. A\though thene wag no nokecable change in [\wehwoen Phapnettad end practical nesully, mang the cinesit ty nedl-tiPe was quite whenesting. One of the major issuer that can be encomtencd is the shontage fe spaee iw the bneadboand. gt is alzo anusiel to track +the numbon of pins of the Ics which % not, may, toad to ennon on breaking the Id. Question / Answer + 4. Wheat ane the names ob the I¢s thet ou would need iP you verted ty use 13 AND geter, 12 NOT gotes and 15 NOR gate im @ cineult 9 How many of ench TA would gou need 9 tr Gote - 1@ AND - — F4Ls08 (on F4He08) Not - #4804 (on 741604) NOR - 74602 (on 74HA02) To implement a cinevit with 13 AND gotes , 1@ NOT gets and 15 NOR gates, you would nequine the Voning number of Ids: a08 AND Gotos: Boch 14 contains ona @- input “AND getes. $0, Pon 18 AND gatos we would need ‘Yq = A325 on 4 Ids. NOT Gates: Ego 7404 IA contains gin NOT gotes. $0, Pon 12 NOT gates we would peed '%=2 Ics. Nok gates: Bash F408 TC aondeing Pour 2- input Non gates. 50, fon 15 Noe grtes, we sould need Wy = 3.75 on 4 Tes, 2. How ean you power youn loge Its iP the +5 pont of youn tnainen boond stops working ? AM “Thea ane 6 Fes ways to powen logic Ids if the 45 pont of +the trainen boand stops wonkcing . 1. Using a gepanate 5V power supply: This is the easiest solution. Most clectnonieg stoner sell modest, cheep BY powen supplies, We just have +o make sune thet [the power supply output ‘have enough auanent +o power aM logie Ids. Many US® changes output 2. Using @ USB changea: ot SV, 50 we een use a chargen Hak can supply need. Least the cunnent Logie 10s $B a bettery oufpule Sv, we 2. Using @ batteny: by connecting barteny ground can powen dogio Tes to the ctnainen board ground. Howeven, we should take eane about the nating of the oxen supply Por the cunnent oP Aogie 125 anh also avoid short ~ dineuiting the on Angie Ids. power supply ‘& ao the Associative Law of Bodleen Algebra. [Am The dospmehes «tus of addition is conitten ay Bollows Pon thace variables + At @ee) = Gro) +¢ This law stoter that when ORing mone than tuo variables , the nesult i the same negandles of Ane grouping of the vanicbles. Assovictive lew Pow multiplicetion also Pollows the same pettenn: aoe) = Qo)e ee aaa nea (a+) e-—=D— W9¢ A A(ee) a—p* Giant ae 2 a a. — aoa 2 A. Whet is a tnucth table 2 Draw the Trudh Table Pon om = XNOR. gcte - ps. A 4nuth table is tabular nepnorentation usedk in Logie ond digital dlectnonies +o show the outouds Gr a Logiack expacstion on a digital cineutt Pon all possible — combinakion of input values. Thoth table Pon an NOR gate: 5. Let us assume yor ‘ave to logical inputs A ond, 9% yor par A and B thnough a NAND gate and then past the owtot oP the NAND gate thmugh a NOT gotte wibak logical — openction will gut Pinel output nepnesent ? Whok is the name of Boolean Algebra that om be used to Pind thie anewen ? ~ - : | | e logical outpk we got if we pas A and | iment: Hhnough NAND gate and then NOT gate lis AB. The Pinal outpt nepneserty the togianl NOT openction. The Boolean Algebna Theonem that con ve used to find this onawer is the Re Mongamt Theonem. Aeconding +0 De Mongant —Theonem: 8 8 AB = A+B | | dn tis cose, the outpt of the NAND gate is the negotion fr togeck AND. openation of A and B. 40, the output of the NOT gete is the negation of the nagation of the lagicoh AND openction of Rand 0, uhich is the seme ag the lagieal AND operction oP Ag = AB all 6. Bnew the I¢ diagram Pon the dineit jm Figuae 2.{, Gn plea of he togio gots daa the 10s and all | the — amnections nequined ty make the aineuit wonk. | & 7. How con you use 3 input AND gate of 2 Q- inpuk AND gate ? Con you Uae the same method t we a 3° inpok OR gete asa Dinpuk OR gete ? [Pt We aan we a S- input AND gcke a a D- inpubs AND gate. Thee ane two ways to do this: 1. Connect two of the inputs of the 3- input AND gate ‘ogethen. This uilll onece 2 common npuct. The pet output of the 3- input AND gate will jonly be 4 uthen the common input and the thind input ore both 4. Gn all othen aaes, the artput uill be O. 9. Gorneet one of He inpute of the @- input AND goke to a constart 4. This will PPrectivdy eliminate thak input Prom the aineuit. The output oP the B-input AND gate ull only be 4 uhen the nemciving two wpule ana both 4. dn all othen casey, He output will be 0 The same method oan be wed ty we 3-inpuct MA Meee Mee ca oR geke as @ B-inpuk OR gete. am this case , connect fro of the inpucke gf the 3-inpet OR gate Angethen . The ovtpet of He S-input OR gate ull only be O when the common input and. the thind input one both 0. gn all other anxer, the output jwill be 4.

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