Scribd
Upload
7 views

slc 1

The document contains a workbook focused on digital electronics, specifically sequential logic circuits. It includes various questions related to synchronous counters, state diagrams, and the functionality of different types of counters and registers. Additionally, it provides contact information for the publisher and indicates the content is aimed at engineers preparing for examinations like IES and GATE.

Uploaded by

rampratap
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
7 views

slc 1

The document contains a workbook focused on digital electronics, specifically sequential logic circuits. It includes various questions related to synchronous counters, state diagrams, and the functionality of different types of counters and registers. Additionally, it provides contact information for the publisher and indicates the content is aimed at engineers preparing for examinations like IES and GATE.

Uploaded by

rampratap
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

IES|GATE | PSsUs

ENGINEERS
Zone Excellence ZONE
of for
Engineers Digital Electronics (Workbook) 21

3 SEQUENTIAL
LOGIC CIRCUITS
1, State diagram of given
diagram 3. Find maximum clock frequency of 3 bit
synchronous series carry counter. If
propagation delay of flipflop 1 second and
propagation delay of AND Gate is 3u second
(a) 250 kHz
(b) 83.3 kHz
(c) 166.66 kHz
(d) 100 kHz
4. Which statement is incorrect about 4 bit
Counters
(a)
(a) Output frequency of ring counter is twice
at Johnson counter

(b) Output frequency of ring counter is half


of Johnson counter
(10) (c) Output frequency of ripple counter half
of Johnson counter
(b)
(d) Max clock frequency fo ring counter is
equal to inverse of propagation delay of
one flipflop
5.

(c)

Clock

(01)

(d) (a)
(10 t, t, t, t,
S
2. Number of AND Gate require to implement 6 (b
bit synchronous series carry counter S
(a) 7 (c .......

(b) 8
(c) 4 (d
(d) 5

Read. office: 65/C, Prateek Market, Near Canara Bank, Munirka Market, New Delhi-110067
Contact No: 011-26194869, 9873000903, 9873664427, 8860182273; Website: www.ghengineerszone ons
IESIGATE |PSu
Digital Electronlcs (Workbook) ENGINEERS
of ZONE
Zone Ecellero ln
Et
22

(10)
(c)
Half
Adder
A=1;
6.
(d)
8. Number of unsued state are
Clock
(a) 0
Which statement is correct (b) 1
(a) = 01010101 .... (c) 2
(b) Q = 011001001001 (d) 3
(c) Q = 000100010001 ...
(d) Q = 110011001100 ... STATMENTS FOR QUESTION 9 AND 10:
The 8-bit left shift register and D-flip-flop
same
Q.7 AND Q.8ARE DATA LINKED shown in fig. is synchronized with
clock. The

CLK>

9. The circuit act as

(a) Binary to 2's complement converter


(b) Binary to Gray code converter
(c) Binary to 1's complement converter
Clock (d) Binary to excess-3 code converter
10. If initially register contains byte B7, then
7. State diagram of above diagram after 4 clock pulse contents of register o!
register will be
00 (a) 73
(b) 72
(a) (c) 7E
(d) 74
1l, The initial state of MOD-16 down counter S
00) - 0110. After 37 clock pulses, the state of the
cOunter will be
(a) 1011
(b)
(b) 0110

New Delhi-110067
Regd. Office: 65/C, Prateek Market, Near Canara Bank, Munirka Market, www.ahengineerszone.co
011-26194869, 9873000903, 9873664427, 8860182273; Website:
Contact No:

You might also like