Perspectives in Science (2016) 8, 760—763

Available online at www.sciencedirect.com

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journal homepage: www.elsevier.com/pisc

Estimation of leakage power and delay in

CMOS circuits using parametric variation夽
Preeti Verma a,∗, Ajay K. Sharma a, Vinay Shankar Pandey a,
Arti Noor b, Anand Tanwar a

a
National Institute of Technology, Delhi, India
b
Centre for Development of Advance Computing, Noida, U.P., India

Received 19 February 2016; accepted 8 June 2016

Available online 4 July 2016

KEYWORDS Summary With the advent of deep-submicron technologies, leakage power dissipation is a
Leakage current; major concern for scaling down portable devices that have burst-mode type integrated circuits.
Aspect ratio; In this paper leakage reduction technique HTLCT (High Threshold Leakage Control Transistor)
Transistor stacking; is discussed. Using high threshold transistors at the place of low threshold leakage control
LCT; transistors, result in more leakage power reduction as compared to LCT (leakage control tran-
Deep submicron sistor) technique but at the scarifies of area and delay. Further, analysis of effect of parametric
variation on leakage current and propagation delay in CMOS circuits is performed. It is found
that the leakage power dissipation increases with increasing temperature, supply voltage and
aspect ratio. However, opposite pattern is noticed for the propagation delay. Leakage power
dissipation for LCT NAND gate increases up to 14.32%, 6.43% and 36.21% and delay decreases
by 22.5%, 42% and 9% for variation of temperature, supply voltage and aspect ratio. Maximum
peak of equivalent output noise is obtained as 127.531 nV/Sqrt(Hz) at 400 mHz.
© 2016 Published by Elsevier GmbH. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/).

Introduction eventually becoming comparable to dynamic power dissi-

pation in many high performance designs. The very large
To limit the power consumption, it is necessary to reduce level of integration results in complication of heat removal,
the power consumption. This force the innovative develop- this in turn increases the cost of cooling and packaging.
ments in low power design. Leakage power dissipation is Several researchers have proposed several methods to con-
trol the leakage power consumption. Kao and Chandrakasan
(2000) used power gating with Multi-Threshold transistors.
Ye et al. (1998) show that ‘‘stacking’’ of two off devices
夽 This article belongs to the special issue on Engineering and Mate-
significantly reduces subthreshold leakage compared to a
rial Sciences.
∗ Corresponding author. Tel.: +91 9717063730. single off device. Kumar and Kursun (2006) presented a
design methodology based on optimizing the supply voltage
E-mail address: [email protected] (P. Verma).

http://dx.doi.org/10.1016/j.pisc.2016.06.081
2213-0209/© 2016 Published by Elsevier GmbH. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/
licenses/by-nc-nd/4.0/).
Estimation of leakage power and delay in CMOS circuits using parametric variation 761

for temperature variation insensitive circuit. Self Controlled biased transistors have their gate and their drain terminal
Stacked Transistor (SCST) or Leakage Control Transistor tied together as a single node. Thus no external control cir-
(LCT) technique (Hanchate and Ranganathan, 2004) is the cuitry is required, signal is generated in the circuit itself
technique to reduce leakage power consumption in CMOS (Gopalakrishnan and Shiue, 2004).
gates without affecting the dynamic power of the circuit.
In its ‘off’ state leakage control transistors acts as dynamic
switch to reduce current flow, the operation of the switch is High Threshold Leakage Control Transistor
controlled by the current flowing in the branch of switch. (HTLCT)
stack effect and operation of the Self-Bias transistor is
explained in section II, the HTLCT design is explained in Dual threshold transistors are used to reduce the leakage
section III, while section IV comprise of circuit behaviour power consumption within given delay constraints. Leakage
with parametric variation. Simulation results and conclu- control transistors used in self-controlled stacked transistor
sions related to the study about leakage and delay for technique are replaced by transistors having high threshold
various cases is discussed in section V. voltage (Verma and Mishra, 2012). Fig. 1(a) shows the LCT
based two input NAND gate circuit having Mt1 and Mt2 as
leakage control self bias stack transistors. Gate of p-channel
Stack effect and self bias transistor
and n-channel MOSFET is connected to the drain terminal
of n-channel and p-channel MOSFET respectively. Voltage at
In deep submicron technology MOS transistor’s subthres- drain terminal controls the operation the these leakage con-
hold current varies exponentially with gate-source voltage trol transistors (LCTs) (Hanchate and Ranganathan, 2004).
of the transistor. In CMOS circuits, very small current flows Fig. 1(b) represents the application of high threshold tran-
even with zero gate to source voltage (Vgs) and is termed sistor technique on NAND gate circuit. Here Mt1 and Mt2
as leakage current. Most of the CMOS logic circuits are are the high threshold transistors, one of these two transis-
designed with series-parallel network of p-channel and n- tors always operates in its cutoff region. This results in an
channel transistors. To measure the DC power consumption, increase of number of OFF transistor from supply voltage to
it is essential to analyse the standby current of stacked ground path and thus increasing stack effect. The advantage
transistors with zero gate-source voltage. Standby current of both high threshold and stack effect is utilized to reduce
decreases as the number of stacked transistors in supply power consumption.
to ground path increases. The standby current is negligibly
small for more than three transistors in a single stack (Gu
and Elmasry, 1999). Circuit behaviour under variation of
  parameters
VDD
Is1 : Is2 : Is3 = 1.8 exp : 1.8 : 1
nVT Temperature fluctuation

where Isi (i = 1, 2, 3) is leakage current for stacked MOS Delay of any path in the circuit depends on the delay of
transistors and i is the number of stacked transistors. The cells and nets. Path delay of digital circuit defines the
above relation shows that as the number of stacked tran- performance of circuit. It is consistently assumed that
sistors are increasing, leakage current is decreasing. Self the cell delay of digital circuits increases with decreasing

VDD
VDD

M1 M2
M1 M2

N_1
N_1
Mt1
Mt1
Out
Out
Mt2
Mt2
N_2
A_in N_2
M3 A_in
M3
N_3
B_in N_3
B_in
M4
M4

Gnd Gnd

(a) (b)
Figure 1 (a) LCT NAND gate and (b) HTLCT based NAND gate.
762 P. Verma et al.

Figure 2 Voltage transfer characteristics of LCT NAND gate (a) with different supply voltages and (b) with varying aspect ratio.

voltage and increasing temperature. But this assumption by aspect ratio (W/L). Reducing L, allows us to reduce W
does not holds for low voltage applications, because increas- while maintaining the same aspect ratio. These FET dimen-
ing temperature may decrease the cell delay. This is due sions are combined with the process parameters to get the
to combativeness of mobility and supply voltage to govern electrical characteristics of the transistor (Bhavnagarwala
the cell delay. This aberration is termed as inverted tem- et al., 2000).
perature dependence (dasdan and hom, 2006). Propagation
Vds
delay is measured by temperature dependent device param- The channel resistance is given as Rchannel = and
eters and for CMOS circuits it is a function of drain current of Ids
     
active transistor. Low temperature operation results in many W (Vgs − Vth ) −Vds
advantages like improvement of sub-threshold swing, higher Ids = 0 Cox VT2 exp 1 − exp
L nVT VT
saturation velocity and operation speed, increase of carrier
mobility, reduced leakage current, refines electro-migration Ids is the drain—source current and is proportional to width
and heat dissipation (Su et al., 1994). of the transistor, thus Rchannel varies inversely with the width
of the transistor.
Effect of supply voltage scaling The area of the gate is defined as Ag

Supply voltage scaling was initially adopted for switching = LW and the gate capacitance is defined as Cg = Cox WL
power reduction. It is proved to be an effective method
for switching power reduction because switching power is
Thus gate capacitance is proportional to the width of the
quadratically dependent on the supply voltage.
channel. Where Cox is the oxide capacitance per unit area.
The channel dimension thus establishes the resistance and
Dynamic Power P = ˛CL VDD
2
fclk and
capacitance of a FET. The equation of Ids shows that leakage
Leakage Power P = VDD Isub current depends upon width, oxide capacitance and other
parameters also. Width of the transistor is directly propor-
where ˛ is the activity factor, CL is the total load capaci- tional to the leakage current. This indicates that if the width
tance, VDD is supply voltage, and fclk is the clock frequency. of the device is increased the leakage current will increase
Along with switching power consumption, supply voltage in direct proportion. High speed digital system design deals
scaling also helps in reduction of leakage power consump- with the ability to perform calculations very fast (Uyemura,
tion, since the subthreshold leakage due to drain induced 2009; Chandrakasan and Brodersen, 1999).
barrier lowering decreases with the scaling of supply voltage
(Fallah and Pedram, 2005). Simulation results and conclusion

Effect of aspect ratio Leakage power consumption is measured by exciting the

circuits with the same set of input vectors.180-nm process
Aspect ratio is defined as the width to length ratio of a tran- technology parameters are taken for the analysis of the cir-
sistor. It is an important design parameter. In deep submicron cuits. Power is measured and average is done for all the input
VLSI both width and length are of the order of micrometres. vectors to obtain the average leakage power dissipations.
Since the maximum current through transistor is determined Fig. 2(a) and (b) shows the voltage transfer characteristics
Estimation of leakage power and delay in CMOS circuits using parametric variation 763

Table 1 Leakage power and delay of LCT NAND gate and basic NAND GATE.

Process technology 180 nm, supply voltage = 1.8 V

Parameters Leakage power (W) Delay (ps)

Basic NAND gate LCT NAND gate Basic NAND gate LCT NAND gate

Temperature variation 7 5.29E−08 1.21E−08 23.68 31.84

(◦ C) at supply 27 1.86E−07 6.88E−08 22.61 29.18
voltage = 1.8 V 47 2.71E−07 6.96E−08 22.02 28.40
67 4.15E−07 7.70E−08 21.37 25.28
87 5.93E−07 8.50E−08 20.89 24.68
Supply voltage variation 1 5.39E−08 4.42E−09 35.89 51.07
(V) at 1.2 6.52E−08 6.01E−09 30.02 41.69
temperature = 25 ◦ C 1.4 6.62E−08 1.61E−08 25.98 36.42
1.6 1.06E−07 1.79E−08 23.78 32.88
1.8 1.22E−07 6.88E−08 22.64 29.32
Aspect ratio variation at  1.23E−07 6.88E−08 22.64 29.32
1.8 V & 25 ◦ C 2 6.87E−07 6.96E−08 21.23 28.76
temperature 4 9.15E−07 1.90E−07 19.15 26.98

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Syst, pp. 306—324.
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The delay of the LCT NAND gate decreases by 22.5%, 42% Kumar, R., Kursun, V., 2006. A design methodology for temperature
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