1

3 ADC buffer

4 with fast settling and lower power consumption

5

6 Thesis Report

9
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18

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21

22

23

24 Yuetian Zou

25 Jun. 2016

1
 1 Contains
2 Abstract .................................................................................................................................................................. 4
3 Preface .................................................................................................................................................................... 5
4 1 Introduction ......................................................................................................................................................... 6
5 2 Theoretical limitation of system .......................................................................................................................... 8
6 2.1 Power use to charge the sampling capacitor................................................................................................ 8
7 2.2 Minimum required gm.................................................................................................................................. 8
8 2.3 Open loop gain limitation - by gm ................................................................................................................ 9
9 2.4 Open loop gain limitation - by 𝜇𝜇 ................................................................................................................. 11
10 2.5 The relation between distortion / trans-conductance / power consumption............................................ 12
11 2.5.1 Numerical solution – transistor width vs. bias current ........................................................................ 15
12 2.5.2 Numerical solution – load capacitor vs. bias current........................................................................... 17
13 2.6 Numerical evaluation of power consumption and distortion .................................................................... 18
14 2.6.1 Distortion vs. bias current.................................................................................................................... 20
15 2.6.2 Distortion vs. input signal voltage ....................................................................................................... 22
16 2.6.3 Distortion vs. transistor width with fixed bias current ........................................................................ 23
17 2.6.4 conclusions .............................................................................................................................................. 25
18 2.7 Class A output stage Large signal settling time vs. bias current analysis with Ideal linear amplifier ......... 26
19 3 Two stage Operational Amplifier ....................................................................................................................... 27
20 3.1 Practical limitations of operational amplifier ............................................................................................. 27
21 3.2 Small signal stability analysis for typical 2-stage amplifier with miller compensation ............................... 28
22 3.3 Optimum unity width current density for highest small signal gain........................................................... 30
23 4 circuit design ...................................................................................................................................................... 33
24 4.1 Pre-charging circuit ..................................................................................................................................... 33
25 4.2 Pre-charging control circuit ........................................................................................................................ 34
26 4.3 Implementation of charge control.............................................................................................................. 34
27 4.4 Comparator................................................................................................................................................. 34
28 4.5 Stop trigger ................................................................................................................................................. 37
29 4.6 Charging control gate ................................................................................................................................. 39
30 4.7 Gate delay compensation ........................................................................................................................... 40
31 4.8 Pre-charge controller input offset control .................................................................................................. 41
32 4.9 Operational Amplifier ................................................................................................................................. 43
33 4.10 operational amplifier in pre-charge configuration ................................................................................... 47
34 5 future work ........................................................................................................................................................ 50
35 Appendix 1 ............................................................................................................................................................ 51
36 Appendix 2 ............................................................................................................................................................ 53
37 Appendix 3 ............................................................................................................................................................ 58
38 Appendix 4 ............................................................................................................................................................ 59

2
1 Appendix 5 ............................................................................................................................................................ 60
2
3

3
 1 Abstract
2

3 An ADC input Buffer amplifier with load capacitor pre-charging technology is shown in this report. The amplifier
4 has high slew rate (peak slew rate = 180 V/us) and consume less power compare to conventional
5 implementation.

7 The conventional negative feedback amplifier under certain fixed load conditions, has its slew rate limited by its
8 GBW and/or static power consumption. The GBW / feedback stability / power consumption are correlated, in
9 case the amplifier under certain fixed load conditions. Not one of these three parameter can be made much
10 better, and at same time not affect to other two parameters. In an application such large slew rate and relatively
11 lower signal frequency is employed, a much larger GBW is need to fulfill the slew rate requirements.

12

13 Such problem can be solved by combining a fast but not very precise pre-charge amplifier and a slower and much
14 more precise amplifier. The fast amplifier only active in the fast slew period, and the precision amplifier only is
15 active in the tracking period. Both amplifiers can be built with low power consumption in this case.

16

17 The speed of the designed fast amplifier is maximized by utilizing one–shot nonlinear feedback technology. The
18 effective gain window only open when the input signal around the determine voltage, such structure make the
19 fast amplifier could operating over the unstable region without having oscillation problem.

20

21 The precision amplifier is operating to several MHz range which, stability will be a problem if more than 2 stages
22 is apply in the feedback loop. This amplifier is optimized for highest open loop linearity, which enable use only
23 2 stages and minimum GBW to meet closed loop distortion requirements. The low GBW results a lower power
24 consumption, as the precision amplifier occupies the most part of total system operating time. The low GBW
25 also results a lower cutoff frequency for the output noise.

26

27 The final results of this project (circuit simulation) preview:

28 P(total) = 396 uW

29 Setting time (to 99%) = 40 ns;

30 Setting time (to 90%) = 2 ns;

31 THD = -59 dB;

32 SFDR = -65 dB;

33 Under conditions:

34 UMC 65nm MOSFET process; C(load) = 1 + 1 pF; Vout(differential, peak to peak) = 2 V; f(input)= 2 MHz;
35 f(sample)= 10 MHz; Vdd= 1.2v

4
1 Preface
2 - What include in this report

3 This report is the sum of many small research parts through the project. Each research parts has targeted to a
4 particular problem meet during the project. Both theory and technical problem appeared to be encountered
5 (mixed) through the project time line. In this report, theory parts have been present at first and followed by the
6 technical parts. There for, the arrangement of the content of this report may not meet the time sequence of
7 these objects’ emerge.

5
 1 1 Introduction
2
3 Digital signal processing has more and more been used in many applications. The overall system performance is
4 limited by the performance of the analog signal chain.
5 A typical analog signal digitizing chain contains an input driver and an analog to digital convertor (ADC).
6 Most ADC have a relatively large sample capacitor at the input. This sample capacitor will draw a large current
7 at the sampling moment. Direct connect the signal source to ADC input may results large distortion of the input
8 signal, in case the signal source has a high output impedance. (Figure 1)
9

10
11 Figure 1 ADC input without driver
12 This problem can be solved by adding a driver amplifier in front of the ADC (Figure 2). This driver amplifier will
13 give these benefits:
14 1. Create a low impedance source for the sample and hold circuit.

15 2. Create a high input impedance for the signal source.

16 3. Isolate the sampler from the signal source to prevent sampler kickback effects.

17
18 Figure 2 ADC input with driver

19 In this project, an ADC buffer amplifier will be designed. The major design challenges for such buffer are:

20 1. Low operating supply voltage. The requirement in this project is 1.2V.

21 2. Low power consumption. The average power consumption should as low as possible.

22 3. Rail to rail performance in both input and output.

6
1 4. Voltage on sampling capacitor settle to 11-bits precision in 50ns

2 The requirements for the final outcome are not clearly defined, but the optimization is towards low power
3 consumption.

4
5
6

7
 1 2 Theoretical limitation of system
2
3 In this chapter, the connection between circuit performance and power consumption will be shown. The theory
4 calculation will give benchmark and guidance for circuit performance optimization.
5
6
7 2.1 Power use to charge the sampling capacitor
8 The driver amplifier must take at least the amount current from power supply to charge the sample capacitor.
9 The amount charge into the capacitor is depend on the signal swing. The charge repeat rate (in 1s) is same as
10 the signal frequency.

11 Define the sampling capacitor has value 𝐶𝐶𝑠𝑠 . The sampling frequency is 𝑓𝑓𝑠𝑠 .

12 Consider in the maximum signal swing, the voltage on the sampling capacitor is varying between 𝑉𝑉𝑠𝑠𝑠𝑠 and 𝑉𝑉𝑑𝑑𝑑𝑑 .

13 The average power used to charge the capacitor is:

1
�����������������
𝑃𝑃𝑐𝑐ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎,𝑀𝑀𝑀𝑀𝑀𝑀 = ����������������
𝐼𝐼𝑐𝑐ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎,𝑀𝑀𝑀𝑀𝑀𝑀 𝑉𝑉𝑑𝑑𝑑𝑑 = 𝑓𝑓𝑠𝑠 (𝑉𝑉𝑑𝑑𝑑𝑑 − 𝑉𝑉𝑠𝑠𝑠𝑠 )𝐶𝐶𝑠𝑠 𝑉𝑉𝑑𝑑𝑑𝑑 Eq. 1
2

14 2.2 Minimum required gm

15 Minimum amount open loop gain is required to make a feedback system retain the expected closed loop gain.
16 E.g. it require a minimum open loop voltage gain of 9 to make a unity gain buffer has its 90% designed closed
17 loop voltage gain (1 x 90% = 0.9). The minimum power consumption to keep the sufficient amount of open loop
18 gain will be calculated in this part. The amplifier here is an operational transconductance amplifier (OTA) with
19 limited gm Figure 3, and its small signal equivalents Figure 4.
20

21
22 Figure 3 simple feedback amplifier

23
24 Figure 4 equivalent circuit of simple feedback amplifier
25
26 The amplifier (Figure 3) with limited transconductance gm (Figure 4) has its transfer function:

8
 𝐼𝐼𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑔𝑔𝑔𝑔𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 (𝑉𝑉𝑖𝑖𝑖𝑖,𝑝𝑝 − 𝑉𝑉𝑖𝑖𝑖𝑖,𝑛𝑛 ) Eq. 2
1 To keep the unity gain buffer working properly (closed loop gain ≃ 1), the requirements are:

2 For the negative feedback loop:

𝐴𝐴
𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑉𝑉 Eq. 3
𝐴𝐴 + 1 𝑠𝑠𝑠𝑠𝑠𝑠

3 And, the open loop gain is:

𝐴𝐴 = 𝑔𝑔𝑔𝑔𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 𝑍𝑍𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 Eq. 4

4 The load impedance is known as:

1
𝑍𝑍𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 = Eq. 5
𝑗𝑗𝑗𝑗𝐶𝐶𝑠𝑠

5 The 𝐴𝐴 will decrease with higher signal frequency 𝜔𝜔. The gain bandwidth product is:

𝑔𝑔𝑔𝑔𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖
𝐺𝐺𝐺𝐺𝐺𝐺 = Eq. 6
2𝜋𝜋𝜋𝜋𝑠𝑠

6 Known a unity gain buffer has its K time designed closed loop voltage gain at:

𝐴𝐴
| | = 𝐾𝐾 Eq. 7
𝐴𝐴 + 1

7 With Eq. 4 Eq. 5 Eq. 7, the minimum 𝑔𝑔𝑔𝑔 required to achieve K times voltage gain at frequency 𝜔𝜔 is:

𝐶𝐶𝑠𝑠 𝐾𝐾𝐾𝐾 √1 − 𝐾𝐾 2 Eq. 8

𝑔𝑔𝑔𝑔𝑚𝑚𝑚𝑚𝑚𝑚 =
1 − 𝐾𝐾 2
8 Note, the Eq. 8 is under the condition: the amplifier has a constant gm over all input and output voltage, and no
9 distortion.
10 The min gm required by amplifier determines the min bias voltage required by the amplifier. The minimum bias
11 current can be calculated based on minimum bias voltage. Minimum theory power consumption so can be
12 computed based on Eq. 8 . (circuit base on Figure 3 Figure 4 )
13
14
15 2.3 Open loop gain limitation - by gm
16 The trans-conductance of a single transistor is limited by the size of that transistor and by its bias conditions.
17 A single transistor amplifier with simple transistor model (Figure 5) is used to analysis the relation between gm
18 and bias current / transistor size. Note, the voltage controlled current source (VCCS) here has variable gm.

9
 1

2 Figure 5 square law model

3 The gm of a transistor is related to the W/L and 𝐼𝐼𝐷𝐷 . The simplified MOS-transistor (square-law) model known as:

1 𝑊𝑊 2
𝐼𝐼𝐷𝐷 = 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺 Eq. 9
2 𝐿𝐿

4 The gm can be found as:

𝑊𝑊 2𝐼𝐼𝐷𝐷
𝑔𝑔𝑚𝑚 = �2𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝐼𝐼 = Eq. 10
𝐿𝐿 𝐷𝐷 𝑉𝑉𝐺𝐺𝐺𝐺

5 And, the transistor go into triode region when 𝑉𝑉𝐷𝐷𝐷𝐷 < 𝑉𝑉𝑆𝑆𝑆𝑆𝑆𝑆 :

𝑉𝑉𝑆𝑆𝑆𝑆𝑆𝑆 = 𝑉𝑉𝐺𝐺𝐺𝐺 Eq. 11

6 There are three major way to increase gm (e.g. by factor of 2):

results
Type of modification modification
gm 𝐼𝐼𝐷𝐷
Increase W --- hold 𝐼𝐼𝐷𝐷 4*W 2 * gm 1 * 𝐼𝐼𝐷𝐷
Hold W --- increase 𝐼𝐼𝐷𝐷 4 * 𝐼𝐼𝐷𝐷 2 * gm 4 * 𝐼𝐼𝐷𝐷
Parallel transistor (increase both W
2 * multiplier 2 * gm 2 * 𝐼𝐼𝐷𝐷
and 𝐼𝐼𝐷𝐷 )

7 Table 1 gm vs. W vs. Id

8 There are different drawback for these modifications.

9 1.. Increase W --- hold 𝑰𝑰𝑫𝑫 : this way will be the most power saving way to gain gm, but paid with larger area and
10 larger parasitic capacitance. The channel unity width current density is reduced in this case. The GBW will be
11 reduced if the load is dominate by transistor’s parasitic capacitor (see 3.3 Optimum unity width current density).
12 2.. Hold W --- increase 𝑰𝑰𝑫𝑫 : this method consume 4 times power to gain 2 times gm. The drawback is obvious –
13 higher power consumption, higher 𝑉𝑉𝑆𝑆𝑆𝑆𝑆𝑆 , higher channel / junction temperature. The benefits is – higher gm,
14 and (almost) no increase on transistor parasitic capacitors.
15 3.. Parallel transistor (increase both W and 𝑰𝑰𝑫𝑫 ): the output driving capacity is doubled, with two times power
16 consumption. GBW increase when the load is dominate by external capacitor (Cs).
17
18

10
 1 2.4 Open loop gain limitation - by 𝜇𝜇
2 The channel modulation has effect on the voltage gain of transistor. The limited channel length will result in
3 channel modulation. The effective amplification factor (𝜇𝜇) could below 10 for short channel device in sub-micron
4 process (e.g. UMC65nm L=60nm; Vgt=300mV; Vds=1.2V; 𝜇𝜇 = 8.4). The maximum voltage gain is limited by
5 channel modulation incase 𝑔𝑔𝑚𝑚 𝑍𝑍𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 ≫ 𝜇𝜇. The amplification factor 𝜇𝜇 describes the ratio of the drain current
6 controllability between 𝑣𝑣𝑔𝑔𝑔𝑔 and 𝑣𝑣𝑑𝑑𝑑𝑑 .The 𝜇𝜇 is defined as:

𝜕𝜕𝑖𝑖𝑑𝑑
𝜕𝜕𝑣𝑣𝑔𝑔𝑔𝑔 𝜕𝜕 𝑣𝑣𝑑𝑑𝑑𝑑
𝜇𝜇 = = = 𝑔𝑔𝑚𝑚 𝑟𝑟𝑑𝑑 Eq. 12
𝜕𝜕𝑖𝑖𝑑𝑑 𝜕𝜕 𝑣𝑣𝑔𝑔𝑔𝑔
𝜕𝜕𝑣𝑣𝑑𝑑𝑑𝑑

7 𝑟𝑟𝑑𝑑 = 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟

8 The simplified MOS transistor model including channel modulation is:

1 𝑊𝑊 2
𝑖𝑖𝑑𝑑 = 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺 (1 + 𝜆𝜆𝑉𝑉𝐷𝐷𝐷𝐷 ) Eq. 13
2 𝐿𝐿

9 With Eq. 12 Eq. 13, 𝜇𝜇 (in saturation region) is:

2(1 + 𝜆𝜆𝑉𝑉𝐷𝐷𝐷𝐷 )
𝜇𝜇 = Eq. 14
𝑉𝑉𝐺𝐺𝐺𝐺 𝜆𝜆

10 Clearly from Eq. 14 𝜇𝜇 is closely related with 𝜆𝜆. At the same time, a transistor operating with lower 𝑉𝑉𝐺𝐺𝐺𝐺 𝐼𝐼𝐷𝐷 and
11 higher 𝑉𝑉𝐷𝐷𝐷𝐷 should has higher 𝜇𝜇. (Eq. 13 Eq. 14)

12 Overall, the analysis shows two basic limitation for the voltage gain. First is the 𝑔𝑔𝑔𝑔 𝑧𝑧𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 product. Second is
13 the transistor amplification constant 𝜇𝜇. The voltage gain will be dominated by the 𝒈𝒈𝒈𝒈 𝒛𝒛𝒍𝒍𝒍𝒍𝒍𝒍𝒍𝒍 product when the
14 load impedance is relatively low. Or, dominate by amplification constant 𝝁𝝁 when the load impedance is high.

15

11
 1 2.5 The relation between distortion / trans-conductance / power consumption
2 The distortion in this section is modeled with a “quasi large signal” model (Figure 6) which makes the analytical
3 analysis possible. This model consist of a parameterized distortion generator and a small signal gain / feedback
4 block.

5 The distortion generator creates distortion according to the input signal. An increase of input signal amplitude
6 will increase distortion. Increase input bias voltage will decrease the distortion ( Eq. 17; Eq. 18; Eq. 19).

7 The feedback reduces distortion. Higher loop gain results in lower closed loop distortion (Eq. 15).

8 The model show in Figure 6 does not contain the true feedback loop. No input signal related loop gain
9 modulation happen, so, only 2nd harmonic exist in the system(Eq. 18). However, in a true circuit, the higher order
10 harmonic is weak compare to the 2nd order harmonic. The loss of higher order harmonic will not strongly affect
11 the THD value.

12

13 Figure 6 quasi large signal distortion model

14 The amplifier’s distortion will decrease with negative feedback. Sufficient amount of loop gain is required to
15 suppress the distortion under a certain level. The required open loop gain A is (see Appendix 5):

𝑇𝑇𝑇𝑇𝑇𝑇𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜
= 𝐴𝐴 + 1 Eq. 15
𝑇𝑇𝑇𝑇𝑇𝑇𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐

16

With Eq. 4 : 𝐴𝐴 = 𝑔𝑔𝑔𝑔𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 𝑍𝑍𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙

1
Eq. 5 : 𝑍𝑍𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 =
𝑗𝑗𝑗𝑗𝐶𝐶𝑠𝑠

𝑊𝑊
Eq. 10 : 𝑔𝑔𝑚𝑚 = �2𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝐼𝐼
𝐿𝐿 𝐷𝐷

17 The relation between 𝐼𝐼𝐷𝐷 and THD with normalized load is about:

12
 2
𝑇𝑇𝑇𝑇𝑇𝑇𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜
�� − 1� |𝑍𝑍𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 |−1 �
𝑇𝑇𝑇𝑇𝑇𝑇𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 Eq. 16
𝐼𝐼𝐷𝐷 =
𝑊𝑊
2𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜
𝐿𝐿

1 Eq. 16 assume the gm is dominated by the bias current (Eq. 10), the (large) signal has no effect to the gm. The
2 relation between the parameters in Eq. 16 are shown in

THD vs. power 2 * Open loop THD 4 * power

Transistor Width vs. power 2*W 0.5 * power
Table 2
3 From Eq. 16, clearly, with a certain closed loop THD need to be achieved, the bias current increases with higher
4 open loop distortion.

5 Increase transistor W supposed to increase the gm, so, lower bias current is required to keep the required gm.

6 Let’s see the open loop large signal (square law) model with Figure 5 :

7 The input signal is: 𝑉𝑉𝐴𝐴 sin 𝑥𝑥

8 Input bias voltage is: 𝑉𝑉𝑏𝑏

9 The normalized (real value) load is: 𝑍𝑍𝐿𝐿

10 The output voltage is:

𝑊𝑊
𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 0.5𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑍𝑍 (𝑉𝑉 + 𝑉𝑉𝐴𝐴 sin 𝑥𝑥)2 Eq. 17
𝐿𝐿 𝐿𝐿 𝑏𝑏

11 Evaluate Eq. 17:

𝑊𝑊 𝑉𝑉𝐴𝐴 2 − 𝑉𝑉𝐴𝐴 2 cos 2𝑥𝑥

𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 0.5𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑍𝑍𝐿𝐿 �𝑉𝑉𝑏𝑏 2 + 2𝑉𝑉𝑏𝑏 𝑉𝑉𝐴𝐴 sin 𝑥𝑥 + � Eq. 18
𝐿𝐿 2

12 Open loop THD (voltage ratio) to bias voltage is about :

𝑉𝑉𝐴𝐴
𝑇𝑇𝑇𝑇𝑇𝑇𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 = Eq. 19
4𝑉𝑉𝑏𝑏

13 The open loop THD (voltage ratio) to bias current is:

𝑉𝑉𝐴𝐴 𝑊𝑊 𝑉𝑉𝐴𝐴 2
𝑇𝑇𝑇𝑇𝑇𝑇𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 = = �𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 Eq. 20
2𝐼𝐼 𝐿𝐿 𝐿𝐿 32 𝐼𝐼𝑑𝑑,𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏
4 � 𝑑𝑑,𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏
𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑊𝑊

14 With Eq. 16 Eq. 19 and Eq. 20 the closed loop distortion and bias current has relation (Appendix 4):

1 𝑉𝑉𝐴𝐴 2 𝑉𝑉𝐴𝐴 1
𝐼𝐼𝑑𝑑 = ⎛ − + ⎞ Eq. 21
2 2
𝑍𝑍𝐿𝐿 64 𝑇𝑇𝑇𝑇𝑇𝑇𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 𝐼𝐼𝑑𝑑 𝑊𝑊 𝑊𝑊
4 𝑇𝑇𝑇𝑇𝑇𝑇𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 �2𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝐼𝐼𝑑𝑑 2𝑢𝑢 𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜
⎝ 𝐿𝐿 𝐿𝐿 ⎠

13
 1 With a known / fixed close loop THD requirement, the relation between transistor size and bias current can be
2 found.

3 Numerical solution has been used to solve this problem.

4 The equation residual error is defined as the absolute value of the numerical difference between left side and
5 right side of the equation.

6 The scale 10𝑥𝑥 has been use in 3D plot. Because it is difficult to accept describe transistor width in dB scale.

7 The scale 10𝑥𝑥 is defined as :

X=1 10𝑥𝑥 = 10
X=2 10𝑥𝑥 = 100
X=3 10𝑥𝑥 = 1000
And so on …

8 The equation has its solution when the “equation residual error” is sufficiently low. In other words, the equation
9 has its solution sets right under the “valley” of the plotted surface.

10

14
 1 2.5.1 Numerical solution – transistor width vs. bias current
2 With “numerical sweep solver”, Eq. 21 can be solved :

4 Figure 7 solving residual error vs. bias current vs. transistor width

5 The results shows, that under condition of a fixed closed loop THD (requirement), the bias current is weakly
6 influenced by the transistor width. In other words, hold the bias current and change transistor width, the closed
7 loop distortion remains almost unchanged (ignoring transistor parasitic, with simplified model).

8 The results shows above may looks strange at first look. In fact it is reasonable:

9 1.. With a larger transistor width and same bias voltage  bias current increase.

1 𝑊𝑊 ↑ 2
𝐼𝐼𝐷𝐷,𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏 ↑ = 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉 Eq. 22
2 𝐿𝐿 𝑏𝑏

10 2.. To keep the bias current unchanged  reduce bias voltage, but the input signal remaining unchanged 
11 open loop distortion increase (Eq. 19).

𝑉𝑉𝐴𝐴
𝑇𝑇𝐻𝐻𝐻𝐻𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 ↑ =
4𝑉𝑉𝑏𝑏 ↓

12 3.. Now, the transistor width increase and bias current unchanged  higher gm  higher loop gain (Eq. 10).

𝑊𝑊 ↑
𝑔𝑔𝑚𝑚 ↑ = �2𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝐼𝐼
𝐿𝐿 𝐷𝐷,𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏

15
 1 Over all, by increase transistor width and hold bias current, results higher loop gain and higher open loop
2 distortion. The closed loop distortion, by coincidence, remaining unchanged (with the simplified model, in case
3 the transistor parasitic effect are ignored) . For the circuit use actual transistors, the performance should
4 decrease due to the increased parasitic in a larger transistor (in case sufficient Vds is always present on transistor
5 ).

7 Figure 8 closed loop gain plot

8 The closed loop gain plot (Figure 8) indicates the useful operating region for different transistor width and bias
9 current setting. Clearly, a closed loop gain close to 1 is only available with sufficient transistor size and bias
10 current.
11 In case the transistor width does not affect the distortion a lot, the width should adjust to a larger value to give
12 a more stable closed loop gain.
13

16
 1 2.5.2 Numerical solution – load capacitor vs. bias current
2 By sweep the load capacitor higher, the bias current required to achieve certain closed loop distortion is clearly
3 increasing.

4 In Eq. 16

2
𝑇𝑇𝑇𝑇𝑇𝑇𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜
�� − 1� |𝑍𝑍𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 ↓ |−1 �
𝑇𝑇𝑇𝑇𝑇𝑇𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
𝐼𝐼𝐷𝐷 ↑ =
𝑊𝑊
2𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜
𝐿𝐿

5 In other word, heavier load require more power to drive it.

7 Figure 9 solving residual error vs. bias current vs. load capacitance

10

17
 1 2.6 Numerical evaluation of power consumption and distortion
2
3 Full numerical method has been used in this part to evaluate the performance of a unity gain buffer. This model
4 has not been simplified. The analytical results are not easy to interpret. However, the 3D plot will give some
5 useful information to the performance evaluation.

6
7 Figure 10 model circuit
8

9
10 Figure 11 amplifier equivalent circuit
11 𝑉𝑉𝑏𝑏 = 𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏 𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣
12 The circuit is modeled with Eq. 23.
⎧ 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 − 𝑉𝑉𝑖𝑖𝑖𝑖 𝑉𝑉𝑠𝑠𝑠𝑠𝑠𝑠 − 𝑉𝑉𝑖𝑖𝑖𝑖
⎪
⎪ + =0
𝑅𝑅 𝑅𝑅
Eq. 23
⎨ 𝑉𝑉𝑖𝑖𝑖𝑖 − 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 0 − 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜
⎪ 𝐾𝐾(𝑉𝑉𝑖𝑖𝑖𝑖 + 𝑉𝑉𝑏𝑏 )2 + + =0
⎪ 𝑅𝑅 𝑅𝑅 𝐿𝐿
⎩
13
14 Solve Eq. 23 (for 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 ) get:
𝑅𝑅𝐿𝐿2
2�𝑅𝑅𝑅𝑅𝐿𝐿 + 𝑅𝑅 2 + − 𝐾𝐾𝐾𝐾𝑅𝑅𝐿𝐿2 𝑉𝑉𝑏𝑏 − 2𝐾𝐾𝑅𝑅 2 𝑅𝑅𝐿𝐿 𝑉𝑉𝑏𝑏 − 𝐾𝐾𝐾𝐾𝑅𝑅𝐿𝐿2 𝑉𝑉𝑠𝑠𝑠𝑠𝑠𝑠 − 𝐾𝐾𝑅𝑅 2 𝑅𝑅𝐿𝐿 𝑉𝑉𝑠𝑠𝑠𝑠𝑠𝑠 − 𝑅𝑅𝐿𝐿 − 2𝑅𝑅 + 2𝐾𝐾𝐾𝐾𝑅𝑅𝐿𝐿 𝑉𝑉𝑏𝑏 + 𝐾𝐾𝐾𝐾𝑅𝑅𝐿𝐿 𝑉𝑉𝑠𝑠𝑠𝑠𝑠𝑠 Eq. 24
4
𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = −
𝐾𝐾𝐾𝐾𝑅𝑅𝐿𝐿

15
16 Three types sweep were made from Eq. 24. These results show the performance trends with different variation
17 on circuits parameter. The transistor parasitic effect are not count in this level’s model, but the transistor indeed
18 has a large signal model for its voltage to current transfer, so the distortion is purely created by the second order
19 transfer function of the MOSFET.
20 One issue of square law model is : it do not allow a “reversed current” (Figure 12). Because from Eq. 9:
21
1 𝑊𝑊 2
𝐼𝐼𝐷𝐷 = 𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝐺𝐺𝐺𝐺
2 𝐿𝐿
22 𝐼𝐼𝐷𝐷 can never be a negative number. This limited the using of this model only with a positive 𝑉𝑉𝐺𝐺𝐺𝐺 .
23

18
1
2 Figure 12 linear model vs. second order model
3
4 The second order model (Eq. 9) will not work properly when the signal amplitude larger than the bias voltage
5 𝑉𝑉𝑏𝑏 . Fortunately, such situation only happen when the open (also closed) loop gain is very low. An additional
6 closed loop gain plot has been added to identify whether the model is in the effective operating region.
7
8

19
 1 2.6.1 Distortion vs. bias current
2
3 Figure 13 shows the output spectrum plot. The higher order harmonic clearly roll off faster. The distortion is
4 mainly contribute by the 2nd harmonic. The distortion roll of at -15 dB per 10 times bias current (Figure 14).
5 Figure 15 shows the closed loop gain, the close loop gain is close to 1, which indicate the circuit operates
6 normally.
7 The simulation results shows, with a less linear open loop transfer function, higher loop gain (bias current) is
8 required to maintain the required closed loop gain.
9 E.g. assume use a class AB stage instead of class A stage increase large signal open loop distortion by 15dB, to
10 solve this problem, it require increase bias current 10 times to meet the (original) distortion requirement.
11

12
13 Figure 13 output power spectrum vs. bias current
14

20
1
2 Figure 14 distortion (2nd + 3rd harmonic to fundamental) vs. bias current
3

4
5 Figure 15 calculated closed loop gain vs. bias current
6
7

21
 1 2.6.2 Distortion vs. input signal voltage
2
3 The input signal amplitude has been sweep in this part, with fixed bias condition. In Figure 16, it clearly shows
4 an increasing of all harmonic power with higher input signal amplitude.
5 The total distortion (2nd + 3rd harmonic) increases about 20 dB for every 10x input signal amplitude. As the total
6 distortion is domain by the second order distortion.
7 Simulation shows the distortion can be much lower with lower signal voltage swing. The performance
8 improvement in here do not increase power consumption.

9
10 Figure 16 output power spectrum vs. input signal amplitude
11

12
13 Figure 17 output distortion vs. input signal amplitude
14

22
 1 2.6.3 Distortion vs. transistor width with fixed bias current
2
3 The transistor width has been sweep in this part, with a fixed bias current for all different transistor width. This
4 part is set to determine whether the re-size of a circuit with fixed power consumption will affect the
5 performance.
6 Figure 18 (surprised) shows the distortion increase with larger transistor width. However, the change is not
7 strong as those shows in previous two sweeps. The distortion increase 5 dB every 10x transistor width.
8 The results in here is a surprise, because increase transistor width will increase the loop gain (Figure 20) which,
9 naturally, will reduce the distortion. But, with a fixed power consumption or bias current, the bias voltage on
10 transistor gate will decrease:
𝑊𝑊 ↑ 2
𝐼𝐼𝑑𝑑,𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏 = 0.5𝜇𝜇𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜 𝑉𝑉𝑔𝑔𝑠𝑠,𝑏𝑏𝑏𝑏𝑏𝑏𝑠𝑠 ↓ Eq. 25
𝐿𝐿

11 The reduce on gate bias voltage will increase the gate voltage variation (ratio), which equivalent to increase the
12 input signal level. The loop gain variation is link to the gate voltage variation (ratio), and the variation on loop
13 gain generate distortion.
14

15
16 Figure 18 output power spectrum vs. transistor width - with constant bias current
17
18

23
1
2 Figure 19 output distortion vs. transistor width - with constant bias current
3
4

5
6 Figure 20 calculated closed loop gain vs. transistor width - with constant bias current
7
8
9

24
 1 2.6.4 conclusions
2 The relation between distortion and circuit parameters is show in Table 3.
3
Relation ratio
Distortion vs. Bias current -15 dB per 10 x Ib
Distortion vs. Input signal voltage -20 dB per 0.1 x Vin
Distortion vs. transistor Width with fixed bias current -5 dB per 0.1 x W

Table 3 performance cost

4

5 The results shows increase bias current and /or decrease input voltage is the most effective way to reduce
6 distortion. The drawback of these modification are obvious – higher power consumption and / or lower signal
7 to noise ratio due to limited signal swing.

8 The first solution – increase bias current is less possible to fit the requirements of a low power circuit. So, the
9 only solution left is to reduce the amplifier’s signal swing and in the same time – the signal swing on sampling
10 capacitor should remain unchanged (near rail to rail).

11

25
 1 2.7 Class A output stage Large signal settling time vs. bias current analysis with
2 Ideal linear amplifier
3 Two scenario have been evaluated in this part: amplifier settling with fixed slew rate, and amplifier settling with
4 fixed output impedance. The amplifier is ideal, with limited slew rate.

5 Sampling capacitor average charging current is known as:

�����������
𝐼𝐼𝑐𝑐ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎,𝐶𝐶𝐶𝐶 = 𝐶𝐶𝑠𝑠 𝑉𝑉𝑖𝑖𝑖𝑖,𝑝𝑝−𝑝𝑝 𝑓𝑓𝑖𝑖𝑖𝑖 Eq. 26

6 Note, the average charging current shown here is the worst case prediction which, the voltage on sampling
7 capacitor changing between𝑉𝑉𝑑𝑑𝑑𝑑 and 𝑔𝑔𝑔𝑔𝑔𝑔 .

8 In case the Class A output stage has constant current slewing, and class A amplifier has its bias current equal to
9 the maximum output current. The charging current known as:

𝑑𝑑 𝑉𝑉𝐶𝐶𝐶𝐶
𝐼𝐼𝑐𝑐ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 = 𝐶𝐶𝑠𝑠 Eq. 27
𝑑𝑑 𝑡𝑡

10 e.g. 𝐶𝐶𝑠𝑠 =1E-12; 𝑉𝑉𝐶𝐶𝐶𝐶 =2; 𝑡𝑡𝑐𝑐ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 =20E-9; the charging current is 1E-4. The bias current of Class A amplifier should
11 higher than 100uA.

12

13 In case the Class A output stage has constant output impedance. The sampling capacitor voltage settled
14 follows 1 − 𝑒𝑒 −𝑡𝑡/𝜏𝜏 . The settling residual is 𝑒𝑒 −𝑡𝑡/𝜏𝜏 . The residual voltage slew rate is:

𝑡𝑡
𝑑𝑑 𝑒𝑒 −𝑡𝑡/𝜏𝜏 𝑒𝑒 −𝜏𝜏 Eq. 28
=−
𝑑𝑑 𝑡𝑡 𝜏𝜏

1
15 The initial (t=0) residual voltage slew rate is − 𝑉𝑉𝑖𝑖𝑖𝑖 . The initial charging current is:
𝜏𝜏

1
𝐼𝐼𝑐𝑐ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎,𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 = 𝐶𝐶𝑠𝑠 𝑉𝑉𝑖𝑖𝑖𝑖 Eq. 29
𝜏𝜏

16 From the requirements, the final setting error should less than 0.5 LSB (the full scare of ADC = 1). So,

2−𝑁𝑁
≥ 1 𝑒𝑒 −𝑡𝑡/𝜏𝜏 Eq. 30
2

17 Overall, the initial current can be found as:

2−𝑁𝑁
𝑙𝑙𝑙𝑙 � � 𝐶𝐶𝑠𝑠 𝑉𝑉𝑖𝑖𝑖𝑖
2 Eq. 31
𝐼𝐼𝑐𝑐ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎,𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 =
−𝑡𝑡𝑐𝑐ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎

18 e.g. 𝐶𝐶𝑠𝑠 =1E-12; 𝑉𝑉𝐶𝐶𝐶𝐶 =2; 𝑡𝑡𝑐𝑐ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 =20E-9; N=11; Initial charge current 8.317E-4. In this case, the Class A amplifier
19 bias current should higher than 831.7uA.

20

21

26
 1 3 Two stage Operational Amplifier
2 A typical Operational amplifier consists 3 signal terminals : invert input (in-) / non-invert input (in+) / and output
3 (out). The operational amplifier sense the voltage difference between invert input and non-invert input, amplify
4 this difference, then show this difference by a voltage signal on output terminal. The relation between inputs
5 and output is shown in Eq. 32

Vout = Av (Vin+ − Vin− ) Eq. 32

6 An ideal operational amplifier should have the amplification or gain approaching to infinity.

8 3.1 Practical limitations of operational amplifier

9 There are many limitations on a practical operational amplifier. The major limitation are:

10 - Gain bandwidth product (GBW)

11 This limitation has been discussed in Eq. 6 and Eq. 42. Practically, transistor has limited gain and internal and
12 external capacitor load. These loads and practices limit the voltage gain of the amplifier. In many case, power
13 consumption cannot be reduced through scale down the transistor size because a large (dominated) external
14 load.

15 - Slew rate

16 This limitation has been discussed in Eq. 27 and Eq. 31 for class A output stage. The slew rate also limited by the
17 amplifiers bandwidth and input stage’s bias current.

18 - Input / output voltage swing range

19 Obvious, transistor could only operating in a certain voltage range. The higher transistor unit width current
20 density will give higher GBW and at same time give higher Vsat. The higher Vsat, the smaller drain voltage could
21 swing through. (see chapter 3.3)

22 - Input offset

23 Increase the size of input differential transistor pair will reduce mismatch. This will payed with higher transistor
24 parasitic capacitors.

25 - Noise

26 The MOSFET drain current noise is known as:

���
𝐼𝐼𝑛𝑛2 = 4𝑘𝑘𝑘𝑘𝑘𝑘𝑘𝑘𝑘𝑘 Eq. 33

27 And the drain signal current can be:

2 2
𝐼𝐼𝑠𝑠𝑠𝑠𝑠𝑠 = 𝑉𝑉𝑖𝑖𝑖𝑖 𝑔𝑔𝑚𝑚2 Eq. 34

28 From Eq. 33 Eq. 34, clearly, the signal power grow faster than noise power with higher gm. This indicates higher
29 signal to noise ratio can be achieved with high gm, and higher gm in many case means “burn” more power.

27
 1 3.2 Small signal stability analysis for typical 2-stage amplifier with miller
2 compensation
3

5 Figure 21 simplified 2-stage amplifier

6 Figure 21 shows a simplified 2- stage amplifier, one transistor for each stages. The output stage consists one
7 transistor (NM0) and a current source I1. The load 𝐶𝐶𝐿𝐿 here is the sampling capacitor (C0) only. All the gm have
8 positive value.

9 With KCL on net 𝑣𝑣𝑜𝑜𝑜𝑜𝑜𝑜 :

−𝑔𝑔𝑔𝑔1 𝑉𝑉𝑑𝑑1 + 𝑆𝑆𝐶𝐶𝑐𝑐 (𝑉𝑉𝑑𝑑1 − 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 ) + 𝑆𝑆𝐶𝐶𝐿𝐿 (0 − 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 ) = 0 Eq. 35

10 On net 𝑉𝑉𝑑𝑑1 :

−𝑔𝑔𝑔𝑔0 𝑉𝑉𝑖𝑖𝑖𝑖 + 𝑆𝑆𝐶𝐶𝑐𝑐 (𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 − 𝑉𝑉𝑑𝑑1 ) + 𝑆𝑆𝐶𝐶𝑔𝑔𝑔𝑔1 (0 − 𝑉𝑉𝑑𝑑1 ) = 0 Eq. 36

11 Solve Eq. 35 Eq. 36 get open loop transfer function:

𝑔𝑔𝑚𝑚1
𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 (−𝑔𝑔𝑚𝑚0 𝐶𝐶𝑐𝑐 ) �𝑆𝑆 − �
𝐶𝐶𝑐𝑐
=
𝑉𝑉𝑖𝑖𝑖𝑖
𝑔𝑔𝑚𝑚1 Eq. 37
�𝐶𝐶𝑐𝑐 𝐶𝐶𝐿𝐿 + 𝐶𝐶𝑔𝑔𝑔𝑔1 𝐶𝐶𝑐𝑐 + 𝐶𝐶𝑔𝑔𝑔𝑔1 𝐶𝐶𝐿𝐿 �(𝑆𝑆 + 0) �𝑆𝑆 + 𝐶𝐶 �
𝐶𝐶𝐿𝐿 + 𝐶𝐶𝑔𝑔𝑔𝑔1 + 𝐶𝐶𝑔𝑔𝑔𝑔1 𝐿𝐿
𝐶𝐶𝑐𝑐

12 Two poles and one zero is shown in Eq. 37 :

𝑃𝑃1 = 0 ,or low frequency, due to 𝜇𝜇 limitation show in Eq. 14 Eq. 38

13

𝑔𝑔𝑚𝑚1
𝑃𝑃2 = −
𝐶𝐶𝐿𝐿 Eq. 39
𝐶𝐶𝐿𝐿 + 𝐶𝐶𝑔𝑔𝑔𝑔1 + 𝐶𝐶𝑔𝑔𝑔𝑔1
𝐶𝐶𝑐𝑐

14

28
 𝑔𝑔𝑚𝑚1
𝑍𝑍1 = Eq. 40
𝐶𝐶𝑐𝑐

2 From Eq. 39 clearly, the second pole 𝑃𝑃2 move to higher frequency with larger compensation capacitor 𝐶𝐶𝑐𝑐 . The
3 drawback of increasing 𝐶𝐶𝑐𝑐 is reduction of the open loop gain bandwidth product. This problem can be solved by
4 increase 𝑔𝑔𝑔𝑔0 , and the first stage power consumption will increase.

5 Several facts have been observed with matlab simulation (Appendix ).

6 1.. negative feedback stability requirements. In case the second stage input capacitance (Cgs1) is very small,
7 increase output / input transistor size ratio (gm1/gm0) make loop more stable.

8 2.. the Cgs1 should well below the compensation capacitor Cc to keep Cc work properly.

9 3.. the compensation is dominate by ratio of 𝐶𝐶𝑐𝑐 /𝐶𝐶𝐿𝐿 , sizing M0 and M1 with same ratio do not affect stability a
10 lot. Only GBW increase with larger transistors.

11 4.. the reasonable value for Cc is 30% of CL, and reasonable value of M1 / M0 transistor width ratio is 3-6.

12

13

14

29
 1 3.3 Optimum unity width current density for highest small signal gain
2 The optimum transistor operating condition for the highest small signal gain is evaluated in this chapter.
3 Transistor’s parasitic effect has been take into count.

4 With Eq. 10

𝑊𝑊
5 𝑔𝑔𝑚𝑚 = �2𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝐼𝐼
𝐿𝐿 𝑑𝑑

6 And assume drain capacitance has linear relationship with transistor width:

𝐶𝐶𝑑𝑑 = 𝐾𝐾𝑐𝑐𝑐𝑐,𝑤𝑤 𝑊𝑊 Eq. 41

7

8 with Eq. 6, the small signal gain bandwidth Product (GBW) will be:

𝑔𝑔𝑔𝑔 �2𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝑊𝑊 𝐼𝐼𝑑𝑑 2𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝐼𝐼𝑑𝑑 2𝜇𝜇𝐶𝐶𝑜𝑜𝑜𝑜 𝐼𝐼

𝐿𝐿 Eq. 42
𝐺𝐺𝐺𝐺𝐺𝐺 = = =� 2 2 =� 2 2 � 𝑑𝑑
2𝜋𝜋𝜋𝜋𝑑𝑑 2𝜋𝜋𝐾𝐾𝑐𝑐𝑐𝑐,𝑤𝑤 𝑊𝑊 4𝜋𝜋 𝐾𝐾𝑐𝑐𝑐𝑐,𝑤𝑤 𝑊𝑊𝑊𝑊 4𝜋𝜋 𝐾𝐾𝑐𝑐𝑐𝑐,𝑤𝑤 𝐿𝐿 𝑊𝑊

9
Unity width current density
10
11 Clearly, a transistor load by a current source, its GBW increases with higher unity width current density. Such
12 relation will hold until the transistor operating into triode region. The small signal GBW curve of a transistor
13 biased at a fixed current can be found with simulation sweep.

14

15 Figure 22 simplified simulation circuit

16

30
 1

2 Figure 23 constant bias current / Vds, trans-conductance / bandwidth test circuit

3 The circuit shown in Figure 23 give transistor a fixed bias current, and regulated Vds. The transistor width is
4 sweep through different values by changing the multiplier during the simulation, and the drain voltage gain is
5 simulated by small signal AC simulation as:

6 Drain voltage gain 𝐺𝐺𝑑𝑑 or “gain” in Figure 24 :

𝑣𝑣𝑑𝑑𝑑𝑑
𝐺𝐺𝑑𝑑,𝑣𝑣 = Eq. 43
𝑣𝑣𝑔𝑔𝑔𝑔
7 The gain peaking is clearly visible in the simulation results (in Figure 24, 𝑉𝑉𝐷𝐷𝐷𝐷 = 1.2𝑉𝑉, 𝑉𝑉𝐺𝐺𝐺𝐺 = value in plot) .

Triode Triode
region region

9 Figure 24 maximum common source drain voltage gain vs. width at fixed bias current
10

31
1 For two stage amplifier, the first stage load is dominate by the 𝐶𝐶𝑔𝑔𝑔𝑔 of second stage. Typically, the optimum unity
2 width current density reduced when the load capacitance is dominated by external capacitor.

3 Note, when a transistor work at gain peak, and with a small load capacitance, the operating point of this
4 transistor will be very close to the triode region. The high 𝑉𝑉𝑠𝑠𝑎𝑎𝑡𝑡 (or large voltage headroom) made the rail to rail
5 operation of these transistors are not possible.

32
 1 4 circuit design
2 In previous chapters, the researches show several different factors will affect the circuit performance. The
3 performance priority are :
4 Low distortion > Maximize signal swing > Power consumption
5 Performance (distortion) cost is shown below:
6
Possible Modification Cost
Distortion vs. Bias current -15 dB per 10 x Ib
Distortion vs. Input signal voltage +20 dB per 10 x Vin
Distortion vs. transistor Width with fixed bias current +5 dB per 10 x W

Table 4 performance cost

7 From Table 4, reduce input signal level give best results on reduce distortion, and it do not increase power
8 consumption. The drawback of this method is obvious – either the maximum signal swing is reduced or, the
9 power supply voltage need to be increased. Clearly, both these problem cannot be easily solved with
10 conventional system structure.
11
12 4.1 Pre-charging circuit
13 The proposed solution is show in Figure 25 and Figure 26. The sampling capacitor Cs and offset capacitor has
14 been charged (with control) in phase 1, then linear amplifier taking the tracking process in phase 2.

15 Such configuration has improved the circuit performance on:

16 1. Extremely high initial slew rete.

17 2. Rail to rail voltage swing on sampling capacitor voltage.
18 3. Lower voltage swing on amplifier output voltage.
19 4. Fixed amplifier output initial voltage (initial condition) for tracking process.
20 5. Less power consumption compare to conventional implementation.

21

Figure 25 phase 1 --- Pre-charging Figure 26 phase 2 --- tracking

22

33
 1 4.2 Pre-charging control circuit
2 The pre-charging control circuit will determine:
3
4 - The charging polarity (charge or discharge).
5 - The moment to stop.
6
7 The functional diagram of the charging controller is shown in Figure 27. The first comparator Comp1 enable at
8 first, and will determine the charging polarity by compare the voltage in sampling capacitor Cs and input voltage.
9 The compare result will decide the Cs should be charge or discharge, and the comparator Comp2 cut off polarity.
10 The second comparator enabled after the output of first comparator is stable. It will determine the moment
11 that charging process should been stopped. The switch connect to XOR gate will cutoff at Comp2 zero crossing
12 point.
13

Polarity signal Start signal

Comp1
Vout

Output enable
Vin Cs

Stop signal
Comp2
XOR

Stop at posedge / negedge

Output enable
14
15
16 Figure 27 pre-charging / charge controller
17
18 4.3 Implementation of charge control
19 The charge controller consists two major parts. The first part is the charging polarity comparator (function as
20 Comp1). The second part is the stop trigger (function as Comp2).
21
22 4.4 Comparator
23 The comparator here will determine the charging polarity before the charging begin. The input signal is
24 continuously changing during this process. Minimize setting time of the comparator is critical to making the right
25 charge / discharge decisions.
26 The schematic is shown in Figure 30. This is a CMOS “push-pull” comparator. The CMOS pair has been connect
27 to Vdd and Gnd (via reset switch NM7). Such configuration enable supply high current to CMOS pair at
28 determine period, so the setting time is minimized.
29 The input differential pair are NM0 NM3. One noticeable problem for this configuration is the reverse leakage
30 through differential pair (see Figure 30). The leakage current at certain input voltage could high as 80% total
31 average operation current of the comparator. To solve this problem, diode connected NM12 NM13 (in Figure
32 30) is used to prevent the reverse current flow through transistor NM0 or NM3 (in Figure 30).
33 Noise and mismatch is not the major problem in this circuit, due to it served in a less precision pre-charge circuit.

34
 NM7

1
2 Figure 28 simplified comparator diagram
3

4
5 Figure 29 comparator output setting
6
7

35
1
2 Figure 30 charge control. comparator
3
4
5
6

36
 1 4.5 Stop trigger
2 The core of the trigger circuit is the negative resistor pair consists PM0 and NM2. The negative resistor generated
3 by these two transistors only exist when these transistors are biased, as their drain current higher than the leak
4 current source (PM3 PM2 / NM5 NM6). Once the transistor current over the critical point, both transistor will
5 fully turn on within 1~2 ns. The transistor pair PM0 NM2 practically equivalent to a tunnel diode, which widely
6 be used in oscilloscope trigger system before high performance MOSFET are available.

7 The differential amplifier / polarity switch in the left part is used to compare the IN+ and IN- voltage, and
8 generate proper (polarity) driving current to negative resistor pair. The polarity switch act as the XOR gate shown
9 in Figure 27.

10 The trigger is reset by cut off NM4. Transistor switch NM16 also been switch off to keep voltage on net “t_out_n”
11 at Vdd. (Figure 33)

12

13 Figure 31 simplified trigger diagram

14

15
16 Figure 32 trigger transient response
17

37
 NM16

2 Figure 33 charge control. stop trigger

3

38
 1 4.6 Charging control gate
2 The charging gate is use to switch on / off charging current. Typical gate involve only one switch and a control
3 logic (Figure 34). The problem of such configuration is, the control logic created a relatively large delay between
4 start / stop signal and switch. This delay results large charging error.
VDD

Charge polarity

start
stop

5 Propagation delay
6 Figure 34 gate with control logic
7 The circuit show in Figure 35 and Figure 36 has same function as the one in Figure 34. The difference is, it has
8 two gates, one connect to start signal, another to stop signal. Such configuration eliminates the requirement for
9 control logic, and minimize the propagation delay. Such two gate configuration has been used in many
10 mechanical cameras.

11
12 Figure 35 double gate function diagram
13

39
 1
2 Figure 36 charging gate
3
4 4.7 Gate delay compensation
5 Although the gate has been designed to minimize on / off delay, there still some delay exist (~1ns). Small mount
6 delay could results large charging error when the voltage rising / falling speed is very high on sampling capacitor.
7 Excessive overshoot / undershoot results oscillation (show in Figure 38, red trace).

Vdd or Gnd
RL
U1
input
delay Rc
Uc
ic Cs

8
9 Figure 37 simplified delay compensation schematic
10 The delay – overshoot problem can be solved by adding a resistor Rc between sampling capacitor Cs and charging
11 current limiter RL (show in Figure 37).
12 Assume the charging current 𝑖𝑖𝑐𝑐 is constant during the time �𝑡𝑡𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 − 𝑡𝑡𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 , 𝑡𝑡𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑓𝑓 �.
13 The voltage error on sampling capacitor is:
∆𝑞𝑞 𝑖𝑖𝑐𝑐 ∆𝑡𝑡
∆𝑢𝑢𝑐𝑐,𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 = = Eq. 44
𝐶𝐶𝑠𝑠 𝐶𝐶𝑠𝑠
14 With 𝑅𝑅𝑐𝑐 , the voltage at 𝑢𝑢1 will higher than 𝑢𝑢𝑐𝑐 . The compensate voltage is:
∆𝑢𝑢𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 = 𝑢𝑢1 − 𝑢𝑢𝑐𝑐 = 𝑖𝑖𝑐𝑐 𝑅𝑅𝑐𝑐 Eq. 45
15 The charge error will be canceled if:

40
 ∆𝑢𝑢𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 = ∆𝑢𝑢𝑐𝑐,𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒

𝑖𝑖𝑐𝑐 ∆𝑡𝑡
𝑖𝑖𝑐𝑐 𝑅𝑅𝑐𝑐 =
𝐶𝐶𝑠𝑠

∆𝑡𝑡
𝑅𝑅𝑐𝑐 =
𝐶𝐶𝑠𝑠 Eq. 46
1 The mathematic shows a fix relation between delay and compensation resistor 𝑅𝑅𝑐𝑐 .
2 The delay induced overshoot has been significantly reduced, after adding 𝑅𝑅𝑐𝑐 into circuit (show in Figure 38,
3 orange trace).
4

5
6 Figure 38 control delay compensation
7 red - without compensation / orange - with compensation
8
9
10 4.8 Pre-charge controller input offset control
11 The controller input offset control presets the input common mode voltage for the comparator and trigger
12 inputs. The differential voltage come from inputs and sampling capacitor connect to capacitor network.
13 Normally, the comparator / trigger inputs is balanced when input voltage equal to sampling capacitor voltage.
14 The stop trigger cutoff the charging current when the comparator / trigger inputs voltage cross zero.

41
1
2 Figure 39 simplified trigger / comparator input common mode bias circuit

42
 1
2 Figure 40 comparator / trigger input offset
3
4
5 4.9 Operational Amplifier
6 The operational amplifier will continuous the work done by pre-charging circuit. It will drive the sampling
7 capacitor to track the input voltage, and in the same time – give a much lower voltage error compare to pre-
8 charge circuit can do.
9 Use previous results, the amplifier’s open loop distortion should made as low as possible to minimum power
10 consumption. The low distortion require the amplifier has a constant open loop gain.
11 The opamp schematic (common mode voltage control not shown) is shown in Figure 43. This is a typical two
12 stage amplifier. The input stage is folded cascode. The output stage is biased in class A. The overall open loop
13 gain is very stable in the effective output swing range (about 800mv p-p). The output swing range is limited by
14 the minimum Vsat required by the output stage transistors, but such drawback is overcome by the pre-charge
15 process.

43
 1

2
3 Figure 41 simplified operational amplifier schematic
4 Figure 42 shows the full schematic of the operational amplifier. Two common mode voltage control is used to
5 regulating the output common mode voltage of first and second stage. Additional source followers have been
6 insert in the miller compensation loop in first stage’s common mode control circuit to reduce additional
7 capacitor loading on first stage’s output and stabilize the feedback loop.

8
9 Figure 42 full schematic operational amplifier
10 The Opamp consume current 216uA to satisfy the distortion requirements with SFDR = -63dB at input signal
11 frequency 2MHz; differential Vout = 600mVp-p; Vdd=1.2V; load capacitor 1+1pF; The amount of bias current is
12 essential to keep distortion low.
13

44
1
2 Figure 43 operational amplifier schematic

45
1 Figure 44 shows the opamp open loop small signal Gain-phase plot. The phase margin is about 51.48 degree.
2 The GBW is about 50MHz. under conditions Vdd=1.2V; load capacitor 1+1pF;

3
4 Figure 44 operational amplifier Gain-Phase plot
5 Figure 45 shows the large signal output power spectrum. The opamp has lower distortion (SFDR -63dB) at 800mV
6 output voltage swing, and much higher distortion (SFDR -45dB) at 1000mV output voltage swing, due to the
7 output transistors operating into triode region. The largest spur is identified as 3rd harmonic folded back.

8
9 Figure 45 operational amplifier THD plot
10

46
 1
2 4.10 operational amplifier in pre-charge configuration
3 The external circuit surround the operational amplifier includes the feedback capacitor Cfb, pre-charge capacitor
4 Cs and fine adjust capacitor Ca, and necessary switches for the operation configuration control.
5 The operation starts from connect only Φ1 switches. The differential voltage stored in capacitor Ca will be
6 discharged, and the Cs and Cfb will be connected in pre-charge mode. Next, connect Φ𝑐𝑐ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 switches and start
7 pre-charge process (Φ1 switches remain connected during this process). After the pre-charge done, disconnect
8 all switches and connect only Φ2 switches, and enable operational amplifier to finish the precision settling and
9 tracking process. Disconnect all switches to hold the voltage on net Out_n and Out_p.

10
11 Figure 46 amplifier with pre-charging configuration
12 Figure 47 (left) shows the power spectrum of sampled signal between out_n and out_p (Figure 46). The spur at
13 around 4.2 MHz is the fold-backed 3rd harmonic, and the 5th harmonic see around 0.2 MHz.
14 Figure 47 (right) is the time domain plot of the input and output signal. The initial fast setting and tracking
15 process is clearly seen.

16
17 Figure 47 output spectrum; transient voltage (red – input; yellow - output)
18

47
1 Figure 48 shows the input signal voltage (red), voltage at opamp output (green), and voltage at sampling
2 capacitor output (yellow). The voltage swing on opamp output is about 0.4Vp-p, and yet the voltage swing on
3 sampling capacitor is nearly rail to rail at 2Vp-p. The higher sampling frequency / input signal frequency ratio,
4 the lower opamp output swing is required to archive rail to rail output on sampling capacitor.

5
6 Figure 48 opamp output swing reduction at lower input frequency
7
8 Figure 49 shows the opamp input referred noise. The 1/f noise power density is clearly higher than the thermo-
9 noise. The total noise in the frequency span from 1Hz to 100MHz is about 0.57mVrms.

10
11 Figure 49 unit gain opamp buffer input referred noise vs. frequency
12

48
1 The overall simulated performance show in below:
2

𝑃𝑃𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 396 𝜇𝜇𝜇𝜇

𝐼𝐼𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 339 𝜇𝜇𝜇𝜇
𝑡𝑡𝑠𝑠𝑠𝑠𝑠𝑠 40 𝑛𝑛𝑛𝑛 Under conditions:

𝑡𝑡𝑠𝑠𝑠𝑠𝑠𝑠,90% 2 𝑛𝑛𝑛𝑛 UMC 65nm MOSFET process; C(load) = 1 + 1 pF;

Vout(differential, peak to peak) = 2 V; f(input)= 2 MHz;
𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 180 𝑉𝑉/𝜇𝜇𝜇𝜇 f(sample)= 10 MHz; Vdd= 1.2v
𝑇𝑇𝑇𝑇𝑇𝑇 + 𝑁𝑁 −59 𝑑𝑑𝑑𝑑 Noise integration span = 1Hz ~ 100MHz
𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 −65 𝑑𝑑𝑑𝑑 Offset in 1 sigma (standard deviation) by Promost
𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 0.57𝑚𝑚𝑚𝑚
𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 2.68𝑚𝑚𝑚𝑚
Table 5 overall performance
3

49
 1 5 future work
2 This project is intend to find out the performance and usability of new amplifier structure. The circuit
3 implementation is limited to give sufficient performance support only. Several modification could been
4 performed to give better overall system performance.
5 1.. The bias current of charge controller and amplifier can be switch off to save power during the hold period.
6 2.. The charging time is signal dependent during pre-charging process. The charging slow down when the voltage
7 on sampling capacitor close to Vdd or Gnd. This problem result uncertainty on the time gap between the end of
8 pre-charge and begin of fine settling. Such uncertainty made each fine settling process has different initial error.
9 Further, the time gap has to be longer to make sure all pre-charging process could end normally, this also larger
10 the fine settling initial error.
11 A different pre-charging circuit can be used to solve the problem. E.g. source follower combined with power
12 supply voltage boost. Such circuit enable sampling capacitor voltage to track the input signal voltage
13 continuously with a less precision compare to the fine settling amplifier. The price is higher power consumption.
14 3.. Better opamp (precision amplifier) can be used to get better performance.

50
 1 Appendix 1
2 % please aware some codes are wrapped ! Direct copy this code into matlab may not work.
3
4
5 %{
6 report 4th order equation solver
7
8 performance at certain required closed loop distotion level
9 %}
10
11
12
13 %close all;
14 clear;
15 clc;
16 %--------------------------parameters
17 log_id_begin = -50; % id sweep
18 log_id_end = -20;
19 log_id_points = 100;
20 log_id = log_id_begin : (log_id_end - log_id_begin)./log_id_points :
21 log_id_end;
22 id = 10.^(log_id./10); % calculate lin Id
23
24 sweep_length=100; % parameter sweep points
25 sweep_begin_log_W = -20;
26 sweep_end_log_W = 30;
27 sweep_step_size_W = (sweep_end_log_W - sweep_begin_log_W)./ sweep_length;
28
29 THD = 0.01; % required closed loop THD
30 un =1;
31 cox =3.33e-4; % umc65 N UnCox = 3.3e-4
32 W =10;
33 L =0.1;
34 w =5e6*2*pi; % signal frequency
35 cl = 1e-12; % load Cap
36 vin=0.5; % input signal amplitude
37 %----------------------------------------- init memory
38 save_log_id_idd = zeros(length(log_id),sweep_length);
39 save_W = zeros(1,sweep_length);
40 save_cl = zeros(1,sweep_length);
41 save_gain = zeros(length(log_id),sweep_length);
42
43 %-----------------------------------sweep loop start here
44 for sweep_index=1:sweep_length
45
46 %cl=10.^((sweep_index-20)./10) .*cl0;
47 W=10.^((sweep_begin_log_W + sweep_index .* sweep_step_size_W)./10);
48 A=2*un.*cox.*W./L;
49 idd =w.^2.*cl.^2.*(vin.^2./(64*THD.^2.*id)-
50 vin./(4*THD.*(A.*id).^0.5)+1./A)-id;
51 % the load has its absolute value use here
52
53 save_log_id_idd(:,sweep_index)=log10(abs(idd));
54 %save_cl(sweep_index) = log10(cl);
55 save_W(sweep_index) = log10(W);
56
57 gain_op= (2*un.*cox.*W./L.*id).^0.5 ./(w.*cl);
58 save_gain(:,sweep_index)= gain_op./(gain_op+1);

51
 1 end
2 %{
3 figure(1)
4 cla;
5 loglog(id,idd)
6 %axis([-1 1 -100 10])
7 %}
8
9 plot_sweep_index=1:sweep_length;
10 %---------------------------------- give the solution of id
11 figure(3)
12 cla;
13 surfc(save_W,log10(id),save_log_id_idd,... %power spectrum in db vs ib in
14 10^x
15 'FaceAlpha',0.5,'EdgeAlpha',0.3)
16
17 axis('vis3d');
18
19 %xlabel('transistor width in 10^x');
20 %xlabel('load capacitor in 10^x');
21 xlabel('W in 10^x');
22 ylabel('DC bias Current in 10^x');
23 zlabel('Equation Residual error in 10^x');
24 title('equation solver results - constant closed loop distotion');
25
26 %-------------------------------show the closed loop gain at certain id
27
28 figure(4)
29 cla;
30 surfc(save_W,log10(id),save_gain,... %power spectrum in db vs ib in 10^x
31 'FaceAlpha',0.5,'EdgeAlpha',0.3)
32
33 axis('vis3d');
34
35 %xlabel('transistor width in 10^x');
36 %xlabel('load capacitor in 10^x');
37 xlabel('W in 10^x');
38 ylabel('DC bias Current in 10^x');
39 zlabel('cose loop gain');
40 title('gain plot - effective oprating region');
41
42
43
44

52
 1 Appendix 2
2
3 % please aware some codes are wrapped ! Direct copy this code into matlab may not work.
4
5 %{
6 3D plot for the numerical solution
7
8 !!! Vin (in this program) = Vsig (in report) !!!
9
10 default input signal sampling points :
11 ph=0:0.1*pi:(40*pi-0.1*pi);
12 % modify input signal will affect hamonic calculation !!!
13 *fundmental = 21 **2nd Hamonic = 41 ***3rd Hamonic = 61 ...and so on.
14
15
16 %}
17 %close all;
18 clc;
19 clear;
20
21 %------------------------------- plot control /
22 % data capture at <plotATindex> sweepindex
23 plo_en = 1;
24 plotATindex = 50;
25
26
27 % -------------------- top sweep control
28 sweep_size=60;
29 spct_k=0.3;
30 % FFT plot frequency range from (0Hz) to (spct_k * full_span)
31
32 %------------------------------ vb sweep control
33 sweep_vb = 0; % ************** !!! sweep Bias Voltage !!!
34 vb_sweep_log_begin = -10;
35 vb_sweep_log_end = 20;
36 vb_sweep_log_step_size =...
37 (vb_sweep_log_end - vb_sweep_log_begin)/sweep_size;
38 vb = 1;
39
40 % ---------------------------- Vin sweep control
41 sweep_input_v = 0; % *********** !!! sweep Vsig amplitude !!! %
42 %1=sweep input amplitude; 0=fixed input
43 vin_sweep_log_begin = -40;
44 vin_sweep_log_end = 0;
45 vin_sweep_log_step_size =...
46 (vin_sweep_log_end - vin_sweep_log_begin)/sweep_size;
47 fix_Vin = 0.1;
48
49 % ---------------------------- W sweep control (with CONSTANT BIAS CURRENT)
50 sweep_W = 1; % ************* !!! sweep transistor Width !!!
51 W_sweep_log_begin = -20;
52 W_sweep_log_end = 30;
53 W_sweep_log_step_size =...
54 (W_sweep_log_end - W_sweep_log_begin)/sweep_size;
55 const_ib=-10e-3; % bias current; must be a negtive number !!!
56
57 %-------------------------------------------- constants Gen. Inital Memory
58 r=100e3; % feedback resistor

53
 1 rl=10e3; % output load resistor
2 %vb=1;
3 ucox=3.33e-4;
4 W= 10;
5 L= 0.1;
6 K=-0.5*ucox.*W./L; % transistor constant = 0.5 u0 Cox W/L
7
8 ph=0:0.1*pi:(40*pi-0.1*pi);
9 % modify input signal will affect hamonic calculation !!!
10 len_ph=length(ph);
11 %win=(flattopwin(len_ph)).';
12 win=(blackmanharris(len_ph)).';
13 %win=(chebwin(len_ph)).';
14 %win=1;
15
16 if sweep_input_v == 0
17 vs=fix_Vin *sin(ph); % fixed input signal
18 end
19
20 save_spectrum = zeros(sweep_size,len_ph*spct_k);
21 save_ib = zeros(sweep_size,1);
22 save_W = zeros(sweep_size,1);
23 save_gain = zeros(sweep_size,1);
24 save_vin = zeros(sweep_size,1);
25
26 indexx=(1:(len_ph*spct_k)).';
27 %----------------------------------------
28
29 for index = 1:sweep_size
30
31 if sweep_input_v == 1 % input signal amplitude log sweep
32 vs=10^(0.1*(vin_sweep_log_begin + vin_sweep_log_step_size*index)) *sin(ph);
33 end
34
35 if sweep_vb == 1
36 vb=10^(0.1*(vb_sweep_log_begin + vb_sweep_log_step_size*index));
37 %vb= 0.05*(index);
38 end
39
40 if sweep_W == 1
41 W= 10^(0.1*(W_sweep_log_begin + W_sweep_log_step_size*index));
42 K=-0.5*ucox.*W./L;
43 vb= (const_ib./K).^0.5;
44 end
45
46 %%{
47 vo=-(2*(r*rl + r.^2 + rl.^2/4 - K*r*rl.^2*vb - 2*K*r.^2*rl*vb...
48 - K*r*rl.^2*vs - K*r.^2*rl*vs).^(1/2) - rl - 2*r + 2*K*r*rl*vb...
49 + K*r*rl*vs)/(K*r*rl);
50
51 im= sum(abs(imag(vo)));
52 if im ~= 0
53 fprintf('out put voltage image part detected at index %d, W= %f, vb= %f
54 \n',index,K,vb);
55 end
56 %%}
57 %{
58 vo=(2*r + rl + 2*(r.*rl + r.^2 + rl.^2/4 - K.*r.*rl.^2.*vb -
59 2*K.*r.^2.*rl.*vb - K.*r.*rl.^2.*vs...

54
 1 - K.*r.^2.*rl.*vs).^(1/2) - 2*K.*r.*rl.*vb - K.*r.*rl.*vs)/(K.*r.*rl);
2 %}
3 vo_ac=-vo+mean(vo);
4
5 vo_no_neg= 0.5*(vo - abs(vo));
6 vo_no_neg_ac=vo_no_neg - mean(vo_no_neg);
7
8 if (plo_en ~= 0) && (index == plotATindex)
9 figure(1)
10 hold off;
11 cla;
12 plot(vs,'-r')
13 hold on;
14 plot(vo,'-b')
15 plot(vo_no_neg_ac,'-g')
16 str=sprintf('Plot at index = %d', index);
17 title({str ;'red = input';'blue = output with DC';'green = output AC'});
18 end
19
20 % choose FFT from normal <vo_ac>, or cliped (no reverse current on Id)
21 <vo_no_neg_ac>
22 vo_ft=abs(fft(vo_no_neg_ac.*win));
23
24 if (plo_en ~= 0) && (index == plotATindex)
25 figure(2)
26 hold off;
27 cla;
28 semilogy(vo_ft)
29 str=sprintf('Plot at index = %d', index);
30 title({str; 'output spectrum'});
31 end
32
33
34 save_spectrum (index , :) = 20*log10(vo_ft(1:(len_ph*spct_k))); % power
35 spectrum in dBV
36
37 save_ib(index) = K*(vb).^2;
38
39 save_vin(index) = 10^(0.1*(vin_sweep_log_begin +
40 vin_sweep_log_step_size*index));
41
42 save_W(index) = W;
43
44 gain_openloop = ucox.*W./L.*vb.*rl;
45 save_gain(index)= gain_openloop./(gain_openloop +1);
46 end
47
48 log_save_ib=log10(abs(save_ib));
49 log_save_W = log10(abs(save_W));
50 log_save_vin = log10(save_vin);
51
52
53 % ------------------------------------------------------- plot sweep Vb
54 if sweep_vb==1
55 figure(3)
56 surf(indexx,log_save_ib,save_spectrum,... %power spectrum in db vs ib in
57 10^x
58 'FaceAlpha',0.5,'EdgeAlpha',0.5)

55
 1
2 xlabel('frequency');
3 ylabel('DC bias current in 10^x');
4 zlabel('FFT power');
5 title('sweep bias current - Ib vs. output power spectrum');
6
7 %zoom on; % fix the figure window distotion for 3D plot
8 %zoom(0.8);
9 %zoom off;
10 axis('vis3d') % better way to fix the figure window distotion for 3D plot
11
12 figure(5)
13 distotion = (10.^save_spectrum(:,41)+ 10.^save_spectrum(:,61))./
14 (10.^save_spectrum(:,21));
15 plot(log_save_ib,log10(distotion)); % ib vs 2nd + 3rd hamonic power
16 xlabel('bias current in 10^x');
17 ylabel('power spectrum in dB');
18 title('sweep bias current - Ib vs. distotion (2nd + 3rd Hamonic Power)');
19
20 figure(6)
21 plot(log_save_ib,save_gain);
22 xlabel('bias current in 10^x');
23 ylabel('calculated closed loop gain');
24 title('sweep bias current - Ib vs. closed loop gain');
25 end
26
27
28 %---------------------------------------------------------plot sweep Vsig
29 if sweep_input_v==1
30 figure(3)
31 surf(indexx,log_save_vin,save_spectrum,... %power spectrum in db vs ib in
32 10^x
33 'FaceAlpha',0.5,'EdgeAlpha',0.5)
34
35 xlabel('frequency');
36 ylabel('input signal voltage in 10^x');
37 zlabel('FFT power');
38 title('sweep input signal voltage - Vsig vs. output power spectrum');
39
40 %zoom on; % fix the figure window distotion for 3D plot
41 %zoom(0.8);
42 %zoom off;
43 axis('vis3d') % better way to fix the figure window distotion for 3D plot
44
45 figure(5)
46 distotion = (10.^save_spectrum(:,41)+ 10.^save_spectrum(:,61))./
47 (10.^save_spectrum(:,21));
48 plot(log_save_vin,log10(distotion)); % ib vs 2nd hamonic power
49 xlabel('input voltage in 10^x');
50 ylabel('power spectrum in dB');
51 title('sweep input signal voltage - Vsig vs. distotion (2nd + 3rd Hamonic
52 Power)');
53
54 end
55
56 % ---------------------------------------------------- plot sweep W
57 if sweep_W==1
58 figure(3)

56
 1 surf(indexx,log_save_W,save_spectrum,... %power spectrum in db vs ib in
2 10^x
3 'FaceAlpha',0.5,'EdgeAlpha',0.5)
4
5 xlabel('frequency');
6 ylabel('transistor W in 10^x');
7 zlabel('FFT power');
8 % !!! this make a two line title !!! ---------v
9 title({'sweep transistor width - W vs. output power spectrum ';'with
10 constant bias current'});
11 %zoom on; % fix the figure window distotion for 3D plot
12 %zoom(0.8);
13 %zoom off;
14 axis('vis3d') % better way to fix the figure window distotion for 3D plot
15
16 figure(5)
17 distotion = (10.^save_spectrum(:,41)+ 10.^save_spectrum(:,61))./
18 (10.^save_spectrum(:,21));
19 plot(log_save_W,log10(distotion)); % ib vs 2nd + 3rd hamonic power
20 xlabel('transistor width in 10^x');
21 ylabel('power spectrum in dB');
22 title({'sweep transistor width - W vs. distotion (2nd + 3rd Hamonic
23 Power)';'with constant bias current'});
24
25 figure(6)
26 plot(log_save_W,save_gain);
27 xlabel('transistor width in 10^x');
28 ylabel('calculated closed loop gain');
29 title({'sweep transistor width - W vs. closed loop gain';'with constant
30 bias current'});
31 end
32
33
34
35
36
37 % figure(4)
38 % %plot(save_ib);
39 % semilogy(save_ib); % ib vs sweep index
40
41
42

57
 1 Appendix 3
2
3 % work on matlab 2013 and on wards
4 clc;
5 cla;
6
7 syms w;
8 gm0=1e-3;
9 gm1=10e-3;
10 cgs=0.02e-12;
11 cl=1e-12;
12 cc=0.3e-12;
13
14 PM(1:20)=0;
15 PMR(1:20)=0;
16 cc_rec(1:20)=0;
17
18 for index=1:20 %number of sweep points
19 NO_=index
20 cc=0.0e-12+0.01e-12.*index %calculate Cc
21 %{
22 s=solve(abs((gm0.*gm1.*cl+gm0.*gm1.*cgs+gm0.*gm1.*cgs.*cl./...
23 cc-gm0.*cc.*1i.*w.*cl-gm0.*cc.*1i.*w.*cgs-gm0.*cc.*1i.*w.*cgs.*cl./cc)...
24 ./ (-w.^2.*cc.*cl.^2-w.^2.*cc.*cl.*cgs-w.^2.*cc.*cl.*cgs.*cl./...
25 cc-w.^2.*cgs.*cc.*cl-w.^2.*cgs.*cc.*cgs-w.^2.*cgs.*cc.*cgs.*cl./...
26 cc-w.^2.*cgs.*cl.^2-w.^2.*cgs.*cl.*cgs-w.^2.*cgs.*cl.*cgs.*cl./...
27 cc+gm1.*1i.*w.*cc.*cl+gm1.*1i.*w.*cgs.*cc+gm1.*1i.*w.*cgs.*cl))==1,w);
28 % absolute gain vout/vin
29 %}
30
31 s=vpasolve(abs((-gm0.*cc).*(1i.*real(w)-
32 gm1./cc)./((cc.*cl+cgs.*cc+cgs.*cl).*...
33 1i.*real(w).*(1i.*real(w)+gm1./(cl+cgs+cgs.*cl./cc))))==1,w,1e9);
34
35 p2=gm1./(cl+cgs+cgs.*cl./cc) %calculate second pole
36 omiga=double(s)
37 omiga_abs=real(omiga)
38
39 % frequency difference between 0dB point and second Pole
40 w0dBToP2=p2-omiga_abs
41
42 % frequency marging ratio
43 w0dBToP2_ra=w0dBToP2./p2
44
45 PM(index)=w0dBToP2;
46 PMR(index)=w0dBToP2_ra;
47 cc_rec(index)=cc;
48
49 end
50
51 figure(1);
52 hold off;
53 cla;
54 plotyy(cc_rec,PM,cc_rec,PMR);
55 legend('frequency of (pole 2 - 0dB point)','frequency of (pole 2 - 0dB
56 point) / pole 2',2);
57 xlabel('frequency');
58

58
1 Appendix 4

2
3

59
 1 Appendix 5
2
3 Relation between open loop / closed loop distortion
4
5 With equation Eq. 17 Eq. 18 Eq. 19 we know:
𝑉𝑉𝐴𝐴
𝑇𝑇𝑇𝑇𝑇𝑇𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜 = Eq. 19
4𝑉𝑉𝑏𝑏
6
7 The open loop distortion is related to the input signal (𝑉𝑉𝐴𝐴 ) level. The distortion level depend on the transfer
8 function of the amplifier. Eq. 19 shows the relation between distortion and the input signal / bias voltage ratio,
9 for a single transistor common source class A amplifier.
10
11 Clearly, distortion reduced with lower input signal level.
12
13 For a unity gain buffer amplifier, the feedback gain is 1. The amplifier gain is A.
14

15
16
17 The Vin is:
1
𝑉𝑉𝑖𝑖𝑖𝑖 = 𝑉𝑉𝑠𝑠𝑠𝑠𝑠𝑠 Eq. 47
1 + 𝐴𝐴
18 With a fixed input signal 𝑉𝑉𝑠𝑠𝑠𝑠𝑠𝑠 and 𝑉𝑉𝐴𝐴 = 𝑉𝑉𝑖𝑖𝑖𝑖 , the relation between open loop distortion and closed loop distortion
19 is:
𝑇𝑇𝑇𝑇𝑇𝑇𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜
= 𝐴𝐴 + 1 Eq. 15
𝑇𝑇𝑇𝑇𝑇𝑇𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
20
21

60