Instruction Execution

The execution process typically follows a cycle known as the Instruction Cycle, which includes several stages:
1. Fetch:
The CPU retrieves the instruction from memory. The Program Counter (PC) holds the address of the next instruction.
The instruction is fetched from the memory address in the PC and loaded into the Instruction Register (IR).
2. Decode:
The fetched instruction is then decoded to determine what action needs to be performed.
The instruction's opcode (operation code) is analyzed, and the necessary signals are sent to the appropriate parts of the
CPU.
3. Fetch Operands (if needed):
If the instruction requires operands, they are fetched from registers or memory.
Depending on the addressing mode, this could involve additional memory accesses.
4. Execute:
The actual operation specified by the instruction is performed. This could involve arithmetic or logic operations, data
transfers, or control instructions.
For example, if it is an arithmetic operation like ADD, the values are added, and the result is stored.
5. Write Back:
The result of the execution is written back to the appropriate location (e.g., a register or memory).
6. Update Program Counter:
The PC is updated to point to the next instruction in the sequence, and the cycle begins again.
This entire process can be summarized as the Fetch-Decode-Execute cycle and occurs continuously until the program
execution is complete or an interrupt occurs.
 Example of Instruction Execution:

Consider an ADD instruction that adds the contents of two registers, say R1 and R2,
and stores the result in R3:

Fetch: The ADD instruction is fetched from memory.

Decode: The CPU decodes the instruction to understand it requires adding R1 and
R2.
Fetch Operands: Values from R1 and R2 are fetched.
Execute: The CPU performs the addition: R1 + R2.
Write Back: The result is stored in R3.
Update PC: The PC is updated to the next instruction.
This cycle continues for every instruction in the program.
 Machine State Register (MSR) and the Processor Status Register (PSR)

1. Machine State Register (MSR) in CAO

The Machine State Register (MSR) in CAO is a special-purpose register that holds critical information about the
current operating environment of the processor. It helps in managing various aspects of the processor’s
interaction with the system, particularly in relation to control over interrupts, memory management, and execution
privilege.
Key Functions of MSR in CAO:
Privilege Control: The MSR determines whether the processor is operating in kernel mode (privileged mode) or
user mode. This is crucial for protecting system resources and sensitive operations.
Interrupt Control: It includes bits that control whether interrupts are enabled or disabled. This is critical for allowing
the system to respond to external events or perform multitasking.
Memory Management: The MSR may control memory protection mechanisms, enabling the processor to access
different areas of memory or restrict access based on privilege level.
Execution Control: It may contain settings for processor-specific features such as virtual memory, cache control,
and floating-point unit (FPU) activation.
Typical Fields of MSR in CAO:
Interrupt Enable/Disable: Indicates whether interrupts are allowed.
Execution Mode: User mode or supervisor (privileged) mode.
Address Translation Control: Controls the mechanism for translating virtual addresses to physical addresses.
Power Management: Some MSRs may control power-saving features like sleep or idle states.
 Machine State Register (MSR) and the Processor Status Register (PSR)

2. Processor Status Register (PSR) in CAO

The Processor Status Register (PSR), also known as the Program Status Word (PSW) in many architectures, is a register
that holds information about the outcome of the last executed instruction and the current status of the processor. The
PSR plays an essential role in instruction execution flow and handling control operations like branching, interrupts, and
error management.
Key Functions of PSR in CAO:
Condition Codes: The PSR holds various condition flags that reflect the result of arithmetic or logical operations. These
flags are often used to determine the flow of execution, particularly for conditional branch instructions.
Interrupt Masking: It includes information on whether interrupts are currently enabled or disabled.
Processor Mode: The PSR indicates whether the processor is operating in user mode or privileged mode.
Instruction Control: It may indicate which instruction set (e.g., ARM, Thumb) the processor is currently executing in multi-
mode instruction set architectures.
Typical Fields of PSR in CAO:
Condition Flags:
Zero Flag (Z): Set if the result of an operation is zero.
Carry Flag (C): Set if there’s a carry out or borrow from an arithmetic operation.
Negative Flag (N): Set if the result of the operation is negative.
Overflow Flag (V): Set if an arithmetic overflow occurs.
Interrupt Flag: Indicates whether interrupts are enabled.
Execution State: Reflects the current execution state (user mode or kernel mode).
Instruction Set State: For architectures like ARM, it can indicate whether the processor is in ARM or Thumb mode.
Differences Between MSR and PSR :

MSR (Machine State Register):

Manages system-level control over the processor and influences how the processor interacts
with external devices, memory, and the operating system.
Contains fields that control execution modes, memory access, privilege levels, and interrupt
handling.
Primarily deals with the overall system's operational state and environment control.

PSR (Processor Status Register):

Reflects the outcome of instruction execution and holds status flags such as carry, zero, sign,
and overflow.
Primarily used for controlling the flow of execution based on the results of instructions and
handling processor-level tasks such as branching and interrupt handling.
More focused on the processor’s internal status during instruction execution rather than
system-level control.
 Introduction
What is Computer Architecture? Instruction Set Architecture (ISA)?
Computer architecture refers to the design of ISA serves as an interface between hardware and
computer systems, including their instruction sets, software.
memory hierarchy, and CPU organization. It defines set of instructions that a processor can
execute & how they are encoded.
ISA impacts the performance, power consumption, and
software compatibility of a processor.

CISC
Instruction Set Architecture (ISA)
RISC
Evolution of CISC and RISC Architectures
CISC (Complex Instruction Set Computer): Developed in the 1970s, CISC aimed to reduce the number of
Instruction needed per program, often including complex instructions that could perform multiple
operations.
RISC(Reduced Instruction Set Computer): Introduced in the 1980s, RISC focused on simplifying the
instruction set by using a smaller set of simple and efficient instructions, with the goal of improving
performance by executing instructions faster.
 Instruction Set Architecture (ISA) - for Computer
+ CISC (Complex Instruction Set Computer) A computer with a large number of instructions is
CISE have large number of instructions to classified as a Complex Instruction Set
Computer, or CISC. (Developed in 1970s)
write efficient programs
In the early 1980s, a number of computer
* RISC (Reduced Instruction Set Computer) designers recommended that computers use
RISC have small number of simple, frequently fewer instructions with simple constructs so they
used can be executed much faster within the CPU
without having to use memory as often. This
type of computer is classified as a Reduced
Instruction Set Computer or RISC.
 CISC (Complex Instruction Set Computer)
CISC is a computer architecture that emphasizes a large and complex instruction set.
CISC processors have many instructions that can perform multiple operations in a
single instruction.
CISC used in PC, desktop computers, laptops, Workstations

Goal of CISC architecture: To reduce the number of instructions a program needs to

execute, which can lead to faster program execution. i.e.
CISC tries to minimize the number of instructions per program but at the cost of
increasing the number of cycles per instruction.
CISE processors typically have more extensive hardware support for performing complex
instructions. This allows for more sophisticated operations to be performed in a single
instruction, which can lead to faster program execution. However, the increased
complexity can also lead to slower processing times.
 CISC Characteristics:
CISC supports a set of a large number of instructions (typically from 100 to 250
instructions).
CISC has some instructions which perform specialized tasks and are used infrequently.
CISC has a large variety of addressing modes (typically from 5 to 20 different modes).
CISC can have variable-length instruction formats.
CISC instructions occupy more than one word in memory.
It has instructions that manipulate operands in memory.
User fewer registers
Uses Microprogrammed control
Complex hardware required
Less Pipelining
CISC may take multiple clock cycle to execute the instruction.
CISC handles a wide range of data types.
CISC Examples:

Intel x86 Architecture: CISC processors include the x86 architecture used in most
desktop and laptop computers today. The x86 family of processors, including Intel's
Pentium, Core i7, and Xeon series, follows a CISC architecture. These processors
support a wide range of complex instructions, including arithmetic, memory access,
and string manipulation.
For instance, the ADD instruction can add two numbers, load data from memory,
and store the result-all in a single instruction.
Motorola 68k Series: The Motorola 68000 series is another classic example of CISC
architecture. These processors were widely used in early personal computers and
workstations. They featured complex instructions for handling various data types and
addressing modes.
 CISC
Advantages of CISC:

Ability to perform complex instructions

Programs require fewer instructions to execute
Greater hardware support for performing complex instructions

Disadvantages of CISC:

Increased complexity can lead to slower processing times

Larger chip size can lead to increased costs
 RISC (Reduced Instruction Set Computer)
RISC is a computer architecture that emphasizes a simple and efficient
instruction set. RISC processors have a smaller instruction set than CISC
processors, with each instruction performing a single operation.
RISC used in smartphones, tablets, and embedded systems, routers, TV
setup boxes.

Goal of RISC architecture: To reduce the amount of work the processor

needs to do for
each instruction, which leads to faster and more efficient processing. i.e.
RISC reduces the cycles per instruction at the cost of the number of
instructions per program.
RISC processors often use pipelining to achieve greater performance.
RISC Characteristics
A RISC processor has a relatively few instructions.
RISC processor has a relatively few addressing modes.
In the RISC processor, all operations are performed within the registers of the CPU.
Memory access is limited to LOAD and STORE instructions.
RISC has fixed-length instruction format.
RISC instructions fit within a single word.
RISC can be hardwired control rather than micro-programmed control.
Simple Hardware required, consume less power and are having high performance.
RISC has single-cycle instruction execution.
RISC has easily decodable instruction format.
Uses more registers
Highly pipelined
RISC supports fewer data types.
 RISC Examples
RISC processors include the ARM, MIPS, and PowerPC architectures.

ARM (Advance RISC Machines) architecture is used in many smartphones,

tablets, and embedded systems
MIPS (Microprocessor without Interlocked Pipeline Stages) architecture is
commonly used in embedded systems such as routers and TV set-top boxes.
MIPS processors are RISC-based.
PowerPC architecture was used in Apple's Power Macintosh computers
before they switched to Intel processors.
RISC

Advantages of RISC:

Simplified instruction set leads to faster processing

Pipelining can increase performance
Lower power consumption
Smaller chip size, which can lead to cost savings

Disadvantages of RISC:

Programs may require more instructions to complete a task than with

CISC
Limited ability to perform complex instructions.
 RISC vs CISC: A Comparison
While both RISC and CISC have their advantages and disadvantages,
the choice between them ultimately depends on the application. RISC is
ideal for applications that require fast and efficient processing, such as
mobile devices and embedded systems. CISC is better suited for
applications that require complex operations, such as video and image
processing.

Another factor to consider is the trend towards hybrid architectures,

which combine the benefits of RISC and CISC. These architectures use
RISC-like designs for the CPU core but incorporate CISC-like features to
support complex instructions. Examples of hybrid architectures include
Intel's x86-64 architecture and ARM's Cortex-A series.
 RISC vs CISC
CISC (Complex Instruction Set Computer) RISC (Reduced Instruction Set Computer)

It is original microprocessor ISA Redesigned ISA that emerged in the early 1980s
It uses a large number of instructions (typically from 100- It uses relatively few instructions.
250 instruction) It uses relatively few addressing modes typically from 3
It uses a large number of addressing modes typically to 5.
from 5 to 20 diffeent modes). It uses fixed length instruction format (typically 32 bit
It uses variable length instruction formats (typically 16 to format).
64 bit per instructions) Simple instructions taking single-clock cycles to execute.
Complex instructions taking multiple-clock cycles to It uses relatively large number of registers (from 32 to
execute. 192)
It uses fewer general purpose registers (ranging from 8 to Only LOAD and STORE instructions reference to
24) Memory
Any nstruction may reference to Memory It uses hardwired control unit.
It uses microprogrammed control unit. All the instructions available in RISC are executed
Not pipelined or less pipelined. Pipeline is difficult directly by the hardwired control.
CISC are relatively expensive and complex to design Highly pipelined. Pipeline is easy.
Examples: Intel and AMD architecture used in PC, RISC are inexpensive and easier to design
Laptop, Desktop Computers, Workstations Examples: ARM, MIPS, PowerPC architecture used in
Mobile, tablets, embedded systems, routers