Bias Stabilization

Lecture Ten - Page 1 of 5

Bias Stabilization

Basic Definitions:

The stability of system is a measure of sensitivity of a circuit to variations in its

parameters. In any amplifier employing a transistor the collector current IC is sensitive
to each of the following parameters:

W ICO (reverse saturation current): doubles in value for every 10oC increase in
temperature.
W |VBE| (base-to-emitter voltage): decrease about 7.5 mV per 1oC increase in
temperature.
W β (forward current gain): increase with increase in temperature.

Any or all of these factors can cause the bias point to drift from the design point of
operation.

Stability Factors, S(ICO), S(VBE), and S(β):

A stability factor, S, is defined for each of the parameters affecting bias stability as
listed below:

ΔI C ∂I
S ( I CO ) = = C [10.1a]
ΔI CO ∂I CO VBE , β =const .

ΔI C ∂I
S (VBE ) = = C [10.1b]
ΔVBE ∂VBE I CO , β =const .

ΔI C ∂I C
S (β ) = = [10.1c]
Δβ ∂β I CO ,VBE =const .

Generally, networks that are quite stable and relatively insensitive to temperature
variations have low stability factors. In some ways it would seem more appropriate to
consider the quantities defined by Eqs. [10.1a - 10.1c] to be sensitivity factors because:
the higher the stability factor, the more sensitive the network to variations in that
parameter.
The total effect on the collector current can be determined using the following
equation:

ΔI C = S ( I CO )ΔI CO + S (VBE )ΔVBE + S ( β )Δβ [10.2]

 Bias Stabilization
Lecture Ten - Page 2 of 5

Derivation of Stability Factors for Standard Bias Circuits:

For the voltage-divider bias circuit, the exact analysis (using Thevenin theorem) for the
input (base-emitter) loop will result in:

ETh − I B RTh − VBE − I E RE = 0 ,

and I E = I C + I B =>
I C RE + I B ( RE + RTh ) + VBE = ETh ,
and I C = βI B + ( β + 1) I CO ,
I β +1
or IB = C − I CO =>
β β

⎡ ( β + 1) RE + RTh ⎤ ⎡ ( β + 1)( RE + RTh ) ⎤

IC ⎢ ⎥ − I CO ⎢ ⎥ + VBE = ETh [10.3]
⎣ β ⎦ ⎣ β ⎦

The partial derivation of the Eq. [10.3] with respect to ICO will result:

∂I C ( β + 1) RE + RTh ( β + 1)( RE + RTh )

⋅ − =0
∂I CO β β

( β + 1)( RE + RTh )
S ( I CO ) = [10.4a]
( β + 1) RE + RTh

Also, the partial derivation of the Eq. [10.3] with respect to VBE will result:

∂I C ( β + 1) RE + RTh
⋅ +1 = 0
∂VBE β

−β
S (VBE ) = [10.4b]
( β + 1) RE + RTh

The mathematical development of the last stability factor S(β) is more complex than
encountered for S(ICO) and S(VBE). Thus, S(β) is suggested by the following equation:

( I C 1 / β1 )( RE + RTh )
S (β ) = [10.4c]
( β 2 + 1) RE + RTh
 Bias Stabilization
Lecture Ten - Page 3 of 5

For the emitter-stabilized bias circuit, the stability factors are the same as these
obtained above for the voltage-divider bias circuit except that RTh will replaced by RB.
These are:

( β + 1)( RE + RB )
S ( I CO ) = [10.5a]
( β + 1) RE + RB

−β
S (VBE ) = [10.5b]
( β + 1) RE + RB

( I C 1 / β1 )( RE + RB )
S (β ) = [10.5c]
( β 2 + 1) RE + RB

For the fixed-bias circuit, if we plug in RE = 0 the following equation will

result:

S ( I CO ) = β + 1 [10.6a]

β
S (VBE ) = − [10.6b]
RB

IC 1
S (β ) = [10.6c]
β1

Finally, for the case of the voltage-feedback bias circuit, the following equation
will result:

( β + 1)( RC + RE + RB )
S ( I CO ) = [10.7a]
( β + 1)( RC + RE ) + RB

−β
S (VBE ) = [10.7b]
( β + 1)( RC + RE ) + RB

( I C 1 / β1 )( RC + RE + RB )
S (β ) = [10.7c]
( β 2 + 1)( RC + RE ) + RB
 Bias Stabilization
Lecture Ten - Page 4 of 5

Example 10-1:

1. Design a voltage-divider bias circuit using a VCC supply of +18 V, and an npn silicon
transistor with β of 80. Choose RC = 5RE, and set IC at 1 mA and the stability factor
S(ICO) at 3.8.

2. For the circuit designed in part (1), determine the change in IC if a change in
operating conditions results in ICO increasing from 0.2 to 10 μA, VBE drops from
0.7 to 0.5 V, and β increases 25%.

3. Calculate the change in IC from 25o to 75oC for the same circuit designed in part (1),
if ICO = 0.2 μA and VBE = 0.7 V.

Solution:
VCC + 18V
Part 1:
VCE = VCC / 2 = 18 / 2 = 9V . RC 7.5kΩ
VCE = VCC − I C ( RC + RE ) , RC = 5 RE => R1 36kΩ Co
9 = 18 − (1m)(5RE + RE ) => RE = 1.5kΩ . vo
Ci
RC = 5(1.5k ) = 7.5kΩ . vi β = 80
I E ≅ I C = 1mA , VE = I E RE = (1m)(1.5k ) = 1.5V .
VB = VE + VBE = 1.5 + 0.7 = 2.2V . R2 5kΩ
RE 1.5kΩ
R2VCC R2 VB 2.2
VB = => = = [10.8a]
R1 + R2 R1 + R2 VCC 18
( β + 1)( RE + RTh )
S ( I CO ) = => Fig. 10-1
( β + 1) RE + RTh
(81)(1.5k + RTh )
3.8 = => RTh = 4.4kΩ .
(81)(1.5k ) + RTh
RR R2 R 4.4k
RTh = 1 2 => = Th = [10.8b]
R1 + R2 R1 + R 2 R1 R1
From Eqs. [10.8a] and [10.8b]:
4.4k 2.2
= => R1 = 36kΩ .
R1 18
From Eq. [10.8a]:
R2 2.2
= => R2 = 5kΩ .
36k + R2 18
Fig. 10-1 shows the final circuit.
 Bias Stabilization
Lecture Ten - Page 5 of 5

Part 2:
S ( I CO ) = 3.8 ,
ΔI CO = 10 μ − 0.2 μ = 9.8μA .
−β − 80
S (VBE ) = = = −0.635mS ,
( β + 1) RE + RTh (81)(1.5k ) + 4.4k
ΔVBE = 0.5 − 0.7 = −0.2V .
β 2 = β1 (1 + 25 / 100) = 1.25β1 = 1.25(80) = 100 ,
( I C 1 / β1 )( RE + RTh ) (1m / 80)(1.5k + 4.4k )
S (β ) = = = 0.473μA ,
( β 2 + 1) RE + RTh (101)(1.5k ) + 4.4k
Δβ = 100 − 80 = 20 .
ΔI C = S ( I CO )ΔI CO + S (VBE )ΔVBE + S ( β )Δβ
= (3.8)(9.8μ ) + (−0.635m)(−0.2) + (0.473μ )(20) = 0.174mA .

Part 3:
Since ICO, doubles in value for every 10oC increase in temperature.
ΔT 75 − 25
Thus N = = = 5 , I CO (75 o C ) = 2 N ⋅ I CO (25 o C ) = (2 5 )(0.2 μ ) = 6.4 μA .
10 10
ΔI CO = 6.4 μ − 0.2 μ = 6.2 μA .
Since VBE, decreases about 7.5 mV per 1oC increase in temperature.
Thus ΔT = 75 − 25 = 50 o C , VBE (25o C ) = 0.7V =>
VBE (75o C ) = 0.7 − 50(7.5m) = 0.325V .
ΔI C = S ( I CO )ΔI CO + S (VBE )ΔVBE
= (3.8)(6.2 μ ) + (−0.635m)(−0.375) = 0.262mA .

Exercises:

1. Derive a mathematical expression to determine the stability factor

S (VCC ) = ΔI C ΔVCC for the emitter-stabilized bias circuit.

2. Discuss and compare (by equations) between the relative levels of stability for the
following biasing circuits:
i. the fixed-bias circuit,
ii. the emitter-stabilized bias circuit,
iii. the voltage-divider bias circuit, and
iv. the voltage-feedback circuit.
 BJT Switching Circuits
Lecture Eleven - Page 1 of 3

BJT Switching Circuits

Basic Concepts:
The application of transistors is not limited solely to the amplification of signals.
Through proper design it can be used as a switch for computer and control applications.
The circuit of Fig. 11-1a can be employed as an inverter in computer logic circuitry.
Note that the output voltage VC is opposite to that applied to the base or input terminal.
In addition, note the absence of a dc supply connected to the base circuit. The only dc
source is connected to the collector or output side and for computer applications is
typically equal to the magnitude of the "high" side of the applied signal-in this case 5V.
VCC + 5V

RC
VC + 5V
0V
+ 5V RB +
0V Vi VCE
+
−
VBE
−
(a) (b)
Fig. 11-1

Proper design for the inversion process requires that the operating point switch
from cutoff to saturation along the load line depicted in Fig. 11-1b. For our purposes
we will assume that I C = I CEO ≈ 0 mA when I B = 0 μA (an excellent approximation
in light of improving construction techniques), as shown in Fig. 11-1b. In addition, we
will assume that VCE = VCE ( sat ) ≈ 0 V rather than the typical 0.1 to 0.3 V level.
When Vi = 5 V, the transistor will be "on" and the design must ensure that the
circuit is heavily saturated by a level of IB greater than that associated with the IB
curve appearing near the saturation level.
The base current IB for the circuit of Fig. 11-1a is determined by
V − VBE
IB = i [11.1]
RB
The saturation level for collector current IC(sat) for the same circuit is defined by
V
I C ( sat ) = CC [11.2]
RC
The level of IB in the active region just before saturation results can be approximated
by the following equation:
I C ( sat )
I B (max) ≅ [11.3]
β
For the saturation level we must therefore ensure that the following is satisfied:
I B > I B (max) [11.4]
 BJT Switching Circuits
Lecture Eleven - Page 2 of 3

Example 11-1:

Verify that the circuit shown in Fig. 11-2 behaves like an inverter when the input
switches between 0 V and +10 V. Assume that the transistor is silicon and that β = 50.

Solution: VCC + 10V

It is only necessary to verify that the transistor is
saturated when Vi = +10 V. RC 6.2kΩ
V − VBE 10 − 0.7
IB = i = = 42.3μA . Vo
RB 220k RB
I C ( sat ) VCC 10 Vi β = 50
I B (max) = = = = 32.3μA . 220kΩ
β βRC (50)(6.2k )
Thus, we have I B > I B (max) , therefore the transistor is
saturated, and the circuit is inverter. Fig. 11-2

Example 11-2:

Verify that the circuit shown in Fig. 11-3 is an inverter when the input switches
between 0 V and -5 V. What minimum value of β is required? Assume that the
transistor is silicon.

Solution:
(4)(5k ) VCC − 20V
When Vi = 0V , VB = = 0.8V , hence the
20k + 5k
RC 1.6kΩ
transistor is at cutoff, so that D1 and D2 are on and D1 D2
Vo = −4 − 0.7 − 0.3 = −5V . − 4V Vo
When Vi = −5V , RTh = 5k 20k = 4kΩ , Si Ge
R1
(+4)(5k ) (−5)(20k ) Vi
ETh = + = −3.2V , 5kΩ
20k + 5k 20k + 5k
R2 20kΩ
E − VBE 3.2 − 0.7
I B = Th = = 625μA .
RTh 4k + 4V
We assume the transistor is at saturation, Vo = 0V , Fig. 11-3
so that D1 and D2 are off and
V 20
I C ( sat ) = CC = = 12.5mA ,
RC 1.6k
I B (max) = I C ( sat ) / β = 12.5mA / β .
For the transistor to be in saturation,
I C ( sat ) 12.5m
I B > I B (max) => β > = = 20 .
IB 625μ
 BJT Switching Circuits
Lecture Eleven - Page 3 of 3

Exercise:

1. Design the transistor inverter of Fig. 11-4 to operate with a saturation current of
8 mA using a transistor with a beta of 100. Use a level of IB equal to 120% of
IB(max) and standard resistor values.

VCC + 5V

RC
Vi Vo
5 RB
Vi β = 100
0 t

Fig. 11-4

2. Verify that the circuit shown in Fig. 11-5 is a positive NAND when the input
switches between 0 V and +12 V. Neglect source impedance and junction saturation
voltages and diode voltages in forward direction. Find the minimum value of β.

VCC + 12V

+ 12V RC 2.2kΩ
Vo
R1 15kΩ
D1 R2
VA
D2 15kΩ
VB
R3 100kΩ

− 12V

Fig. 11-5