IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

Implementation of Speech Encryption and

Decryption using Advanced Encryption Standard
Lokireddi Phani Kumar, A. K. Gupta

Abstract—With the rapid increase in computing and simulation results are discussed in section IV. The paper is
communication devices the need for security services has become concluded in section V.
crucial in information transfer. Protecting the digital information
against security attacks is extremely important. Encipherment is II. ADVANCED ENCRYPTION STANDARD
the security mechanism that provides authenticity and
confidentiality. In this paper a highly secured design for offline A. Cryptography
speech communication is presented. The proposed design uses Cryptography is a practice and study of techniques for
Advanced Encryption Standard, a sophisticated cryptographic secure communication. The basic elements of a cryptographic
algorithm, which ensures that the transmitted data is protected algorithm are plaintext, key and cipher text. The data which is
from unauthorized disclosure. This design is implemented on present in its natural format is known as plaintext. A key is the
Field Programmable Gate Array for real time application of
sequence that controls the behavior of the algorithm. Cipher
offline speech encryption and decryption.
text is the data which is unreadable by anyone expect the
Keywords— Advanced Encryption Standard (AES), Field
intended recipients. Modern field of cryptography includes
Programmable Gate Array (FPGA), Universal Asynchronous symmetric key and asymmetric key cryptographic algorithms
Receiver Transmitter (UART). [2].
Symmetric key algorithms use same key for both
I. INTRODUCTION
encryption of plain text and decryption of cipher text. Across
Speech encryption has always been a very important part of the years, various comprehensive data encryption techniques
secured communication [1]. Digital transmission is much more have been developed. Some popular examples of symmetric
efficient than analog transmission and it is much easier for key algorithms include RC4 (Rivest Cipher 4), DES (Data
digital encryption techniques to achieve high degree of Encryption Standard), AES and triple DES [2]. AES cipher
security. Modern cryptographic algorithms have potential to also known as Rijndael cipher is the most advanced
provide security services like data confidentiality, data cryptographic algorithm approved by National Institute of
integrity, authentication, non-repudiation and access control. Standards and Technology (NIST) of the United States in
With the advent of reconfigurable devices like FPGAs, 2001 [3].
hardware implementation of complex algorithms has become B. AES Algorithm
quite easy which makes it possible to achieve significant
AES is a symmetric key block cipher existing in various
improvement in speed. AES is a cryptographic algorithm
key lengths of 128-bit, 192-bit and 256-bit. A block cipher
which needs large number of byte level and bit level
usually consists of two paired algorithms, one for encryption
operations. In the present work, the AES encryption/
at sender side and other for decryption at receiver side. As
decryption algorithm has been hardware implemented on
AES is a symmetric key cipher both sender and receiver share
FPGA for speech signal. For testing the hardware implemented
the same key which is also known as private key.
encryption/decryption engine, the sample speech was acquired
With the message P and the key K as input, the encryption
using a computer and MATLAB. The acquired speech file was
algorithm forms the cipher text C as mentioned in (1).
encrypted on a FPGA. The encrypted file was transmitted to
C = EK(P) (1)
another FPGA where it was decrypted and transferred to a
The notation as represented in (1) indicates that the cipher
computer where original speech was recovered using
text C is produced by using encryption algorithm E, as a
MATLAB.
function of the plaintext P, with the specific function
This paper is organized as follows. Section II gives a brief
determined by the value of the key K [4]. The intended
introduction AES algorithm. Section III describes the design
receiver in possession of the key is able to invert the
aspects of the AES hardware and serial communication
transformation and retrieve the plain text.
interface. The implementation of the design on FPGA and the
The inverse transformation that is performed using
Lokireddi Phani Kumar, School of VLSI Design and Embedded Systems, NIT decryption algorithm D as a function of the cipher text C [4] is
Kurukshetra, Kurukshetra, India ([email protected]) represented in (2).
P = DK(C) (2)
A. K. Gupta, School of VLSI Design and Embedded Systems, NIT
AES is an iterative cipher comprising computational
Kurukshetra, Kurukshetra, India ([email protected])
rounds for both encryption and decryption. For every
additional 32 bits in cipher key the number of rounds is
increased by one [5]. The number of rounds for various

978-1-5090-0774-5/16/$31.00 © 2016 IEEE

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 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

lengths of AES ciphers are given in Table I. AES 128-bit 3) Mixing: In this transformation a bitwise XOR operation
cipher has been used in the proposed design. is applied between the neighboring bytes of the 128-bit block.
The mixing transformation is not performed in the last round.
TABLE I. AES STRUCTURE
4) Add-Round key: The most important transformation of
Classification Rounds the round is Add-Round key transformation. This
AES-128 10
transformation is a bitwise XOR operation between the
AES-192 12
AES-256 14 corresponding round key generated from key expansion
process and the 128-bit output of previous stage.

III. PROPOSED DESIGN

In this section, we present offline speech encryption and
decryption hardware architecture and its functional blocks.
A. Algorithm Implementation
For encryption module the input is plaintext and the output
is cipher text whereas for decryption module the input is
cipher text and output is plaintext. The conceptual scheme of
AES is shown in the Fig. 1. Cipher key which is shared
between end users is kept secret.

Fig 1. Conceptual Scheme of AES

The implementation of AES algorithm is a step by step

Fig 2. Encryption process flow
procedure. At first, in encryption module, 128-bit plain text
undergoes pre-round transformation. Pre-round transformation To create round key for each round, AES uses a key
is bitwise XOR operation between the input 128-bit plain text expansion process in which all round keys are generated from
and 128-bit cipher key. The output of pre-round single 128-bit cipher key [5]. The keys that are generated are
transformation is transferred to next stages for further round of 128-bit length each. Basically all rounds are symmetric in
transformations. nature and key expansion process plays an important role in
Each round has four distinct uniform transformations the elimination of symmetry by having round dependent round
namely substitution, shifting, mixing and add-round key. constants. The non-linearity of the key expansion practically
These transformations are applied to the 128-bit (16-bytes) eliminates possibility of equivalent keys. In the final round of
data block in encryption process. The complete process flow encryption there is no mixing transformation [5]. The output
of encryption is shown in the Fig. 2. of the last round of encryption module is 128-bit cipher text.
The cipher text is the input to the decryption module.
1) Byte substitution: Substitution operation is a nonlinear
Decryption is the inverse process of encryption in which
byte substitution that operates independently on each byte of inverse round transformations are applied to cipher text to get
the 128-bit data block and hence there are 16 individual byte- back the original data [5]. The entire decryption process is
to-byte transformations[5]. Substitution byte operation is shown in the Fig. 3. First stage of any round transformation in
implemented by using precomputed values stored in look up decryption process is Add-Round key transformation. In the
tables (LUTs) and is responsible for confusion. first round of decryption there is no inverse mixing
2) Shifting: Shifting transformation is implemented after transformation. In decryption process inverse substitution
substitution transformation. In this transformation permutation operation is performed after performing inverse mixing and
function is applied to the bytes of the data block in which the inverse shifting operations. Inverse substitution lookup table
order of the bytes is changed and the order of the bits in the values which are used in this process are different from those
that are used at encryption side. After 10 rounds of decryption
byte is left unchanged.

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process, the final stage is the post-round transformation. Post- transmit module, baud rate generator, receive data register and
round transformation is bitwise XOR operation between the transmit data register as shown in Fig.6.
cipher key and the output of the tenth round.
In asynchronous serial communication the receiving
device will not have any knowledge about the clock of the
source device. In general UART baud rates are much lower
than FPGA system clock. The internal clock frequency of
Spartan 3E FPGA system is 50 MHz and hence the baud rate
generator is used to divide the on board clock frequency into
lower rates to generate baud clock. The generated baud clock
is utilized to recover the received data as well as time the data
that is to be transmitted [7].
The voice which is recorded in computer using MATLAB
is shown in Fig.5. The voice is sampled at the rate of 8000
samples per second. The recorded voice is of one second
duration and so the total number of samples is 8000. The
amplitude level of each sample is digitized and is of 8-bit
length.

Fig 5. Recorded Voice Signal

Fig 3. Decryption process flow

B. Serial Interface Design These digital values are transmitted using hyper-terminal
application of a host computer to FPGA board-1 for
Encryption and decryption process continues till the end of encryption via RS232 serial cable.
data transmission. The end to end data transfer is shown in
Fig.3.

Fig 4. Block Diagram of end to end Data transfer Fig 6. Block Diagram Architecture of Encryption System

UART (Universal Asynchronous Receiver Transmitter) As the transmission is asynchronous each data frame (8-
system was used for serial data transfer from computer to bit) is sent with start and stop bits. Receive module mainly
FPGA, FPGA to FPGA and FPGA to computer [6]. RS232 a consists of 8-bit serial in parallel out register. When the start
serial communication standard has been used for data transfer. bit is detected receive module synchronizes its baud clock
The speed of the RS232 link is determined by its baud rate. such that the edges align with the rate of the incoming data
The baud rate is the bit rate of the communication link in bits stream [7] and when the stop bit is detected the entire 8-bit
per second (bps) [9]. Both transmitting and receiving FPGA data frame is sent to receive data register. Receive data
boards must communicate at same baud rate [6]. The UART register which is of 128-bit length stores the data coming from
control module that is designed contains receive module, the receive module. When the receive data register is full, the

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entire 128-bit data block is sent to encryption module for data

encryption. The output of encryption module which is 128-bit
cipher text is sent to transmit data register. Transmit data
register sends the 128-bit cipher byte-by-byte to transmit
module. The transmit module mainly consists of parallel in
serial out register which gives serial cipher as output. This
output cipher is sent to FPGA board-2 for decryption. The
complete encryption system which is implemented on FPGA
board-1 is represented in Fig. 6.

Fig 8. Simulation Results of Encryption module

Fig 7. Block Diagram Architecture of Decryption System

The UART control module used at decryption side is the

same as the one that is used at encryption side. The decrypted
text coming from decryption system is transmitted to the
receiving computer hyper terminal via RS232 serial cable. Fig 9. Simulation Results of Decryption module
When all the digital samples are received, voice signal is
reconstructed from those samples using MATLAB. The entire TABLE II. DEVICE UTILIZATION OF XIINX SPARTAN 3E EVALUATION
PLATFORM FPGA BOARD-1
decryption system which has been implemented on FPGA
board-2 is shown in Fig. 7. Logic Utilization Used Available Utilization
Number of Slice Flip Flops 1115 9312 11%
IV. RESULTS Number of 4 input LUTs 1955 9312 20%
The proposed architecture is synthesized using Verilog Number of bonded IOBs 3 232 1%
HDL (Hardware Description Language) in Xilinx ISE Design
Suite. The proposed design has been implemented on Spartan
3E FPGA (XC3S500E) boards. MATLAB is used for TABLE III. DEVICE UTILIZATION OF XIINX SPARTAN 3E EVALUATION
PLATFORM FPGA BOARD-2
translation between voice signal and digital data. The real time
secured offline voice communication between two computers Logic Utilization Used Available Utilization
Number of Slice Flip Flops 2536 9312 27%
which is the most fascinating part of this design has been Number of 4 input LUTs 2611 9312 28%
successfully implemented. Number of bonded IOBs 3 232 1%
Simulation results of encryption module and decryption
module are shown in Fig. 8 and Fig. 9 respectively.
The resource utilization details of FPGA by encryption TABLE IV. XILINX POWER ESTIMATOR REPORT OF SPARTAN 3E FPGA
system and decryption system are mentioned in Table II and Specification Encryption Process Decryption Process
Table III respectively. Xilinx Power Estimator (XPE 14.3) tool On-Chip power 0.083 0.085
has been used to calculate on-chip power consumption of both (watts)
encryption and decryption modules, and the values are
tabulated in Table IV.
The proposed system is highly resistant to security attacks.
Security margin of the system is high because of the increased
number of rounds and using different keys for various rounds.
Resource sharing technique has been used to implement the

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round transformations in order to reduce the critical path delay [3] “ADVANCED ENCRYPTION STANDARD,” Federal Information
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[5] Joan Daemen and Vincent Rijman, AES proposal document, september
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techniques used in implementation of AES are very simple but [7] Serial Communications document, Silicon Labs, Austin.
the algorithm is virtually indecipherable. Further optimization [8] Jan Axelson, “Serial port complete,” in Networks, 1998.
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[10] Spartan-3E FPGA Family Data Sheet, Xilinx, july 19, 2013.
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