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Module 2- Hazards, Reliable Design and Fault Diagnosis

Contents: Hazard: Static Hazard, Design of Hazard free switching circuits, Fault Detection in
Combinational Circuits: The faults. The fault table, covering the fault table, Fault Location Experiments:
Preset Experiments, Adaptive Experiments, Designing adaptive Experiments, Boolean Differences:
Properties of Boolean differences, Further applications, Fault detection by Path sensitizing: Path
sensitizing, Limitations of the method, Detection of multiple faults, experiments for two level AND-OR
networks, Systematic generation of minimal fault detection experiments for two-level networks, Fault
tolerant Design, Quadded Logic

Text book 1: Switching and Finite Automata Theory”, ZviKohavi, 2nd Edition. Tata McGraw Hill
Edition, 1979, Chapter 8.1-8.8

Hazards:
*circuits have been assumed to respond instantaneously to input signals and signal propagation
time has been assumed to zero.

* the delays associated with switching components cause non instantaneous changes of states
which leads to hazard.

Consider a function whose map is as shown below.

Gate network

Fig(c)Contact network

Fig: network containing static hazards

To remove static hazard form an other gate network taking

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Fig(d) : hazard free network

Design of hazard free switching circuits
Eg: Consider

Fig: illustration of a hazard due to sub cubes formed by ‘0’ cells.

is a hazard free network.

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Hence hazard is eliminated by adding to the exp of

Hence

Fault detection in combination in combination circuits.

Circuit to be tested is

Inputs Outputs in presence of faults

ABC
000 1 1 1 1 0 1 1 1 1
001 0 0 0 0 0 0 0 1 1
010 1 1 1 1 0 1 1 1 1
011 0 0 0 0 0 1 0 1 1
100 1 1 1 1 0 1 1 1 1
101 0 0 0 0 0 0 1 1 1
110 1 1 1 1 1 1 1 1 1
111 1 0 0 0 1 1 1 1

where is fault free output.

means fault ouptput when

means fault ouptput when

means fault ouptput when

means fault ouptput when

means fault ouptput when

means fault ouptput when

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means fault ouptput when

means fault ouptput when

Now perform EXOR operation between each fault output and fault free output and then tabulate the
results.

Inputs Possible faults

ABC
000 1
001 1
010 1
011 1 1
100 1
101 1 1
110
111 1

Now check for single 1’s columnwise.

Reduced table is

Inputs Possible faults

ABC
000 1
011 1 1
101 1 1
111 1

Therefore, 3 essential tests 011,101,111 are required to detect all faults except to detect test 000 is
performed.

Fault location identification.

There are 2 types.

1) Preset expt –in this type, entire tests are determined by the circuit response.
2) Adaptive expt-in this type, the test to be presently applied depends on the response of the circuit
to the preceding tests.

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Preset experiment
Eg: let be faults.
Let and be tests.

FAULT LOCATION TABLE

T faults

1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1

Check for single 1’s column wise.

Hence are essential tests. Remove essential tests and draw reduced table.

1 1 1
1 1 1 1
1 1
1 1 1

and are same .so eliminate .

is dominated by .so eliminate .
is dominated by .

Hence reduced table is as shown below.

1 1
1 1
1 1
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Hence to detect all faults we can choose any two tests. Choosing , we get { } as essential
tests.

Find FAULT DICTIONARY for PRESET expts.

T faults Output of fault free

circuit(
1 1 0
1 1 1 1
1 1 0
1 1 1
1 1 0
1 1 1 1

Considering only essential tests .

If is 1,change 1 to 0 and 0 to 1.If is 0 then retain it as it is. Hence we get the table as shown below.

Faults Output of fault

free circuit(

1 0 1 1
0 0 1 0
1 0 0 1
0 0 0 0
1 1 1 1
0 1 1 1
1 0 1 0

Chapter: 2 ADAPTIVE EXPERIMENTS

• They are also known as sequential decision procedure.
• The selection of next test to be applied is determined by the circuit response to the
previous tests.
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• Adaptive experiments are determined by adaptive tree.

Designing Adaptive Tree

Faults
Tests Output of fault free ckt
T1 1 1 0
T2 1 1 1 1
T3 1 1 0
T4 1 1 1
T5 1 0
T6 1 1 1 1

Select that test has more number of 1’s.

Hence, select T2 and T6 as essential tests.

Construct adaptive tree

. four level adaptive tree

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Three level adaptive tree

Exercise: 8-11 Given the fault table as shown below, where Z denotes fault-free output for
the corresponding test.

a) Find a minimal set of tests to detect all single faults.

b) Find a preset set of tests to locate all single faults and shown= the corresponding fault
dictionary.
c) Find a minimal adaptive fault –location experiment.

Faults
Tests Output of fault free ckt (Z)
T1 1 1 1 0
T2 1 1 1
T3 1 1 1
T4 1 0
T5 1 1

Solution:

a) To find minimal tests that are required to detect all faults.

T1 1 1 1 1 1 1 1 1 1
T2 1 1 1 1 1 1 1 1
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T3 1 1 1 1 1 1 1 1
T4 1 1 1 1 1
T5 1 1 1 1 1
Check for column wise single 1’s and mark it as shown above. Hence tests T1 and T2 are
essential tests. Leaving the columns of faults that can be detected by tests T1 and T2 we get
reduced table as shown below.

Reduced table

T3 1 1
T4 1
T5 1 1

Check for column wise 1’s in reduced table and mark them as shown above.hence tests T3,
T4 and T5 are essential.

Hence all tests are essential.

b) Fault dictionary

Tests
faults
T1 T2 T3 T4 T5
Z 0 1 1 0 1
0 0 1 0 1
0 0 1 1 1
1 1 1 0 1
1 1 0 0 1
1 1 0 0 1
1 1 0 0 0

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C) 3 level adaptive tree for test T1.

BOOLEAN DIFFERENCE
• Consider a combinational circuit which realizes the function
• To test input for s-a-0 (stuck at zero), the logical value that must take is
complement to the fault that we want to detect i.e., 1.
• The values assigned to the remaining variables are
will be different from
and therefore the value of will determine
the value and the fault will be determined.
• Definition: Boolean difference of a function wrt one of its
variables is defined as

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If then

If , then any change in the value of ,regardless of

the values of remaining variables.

• In general , will be the function of some or all variables.

• Find the values for which .

• In order to find the set ,which detects faults s-a-0 is given by 3

• Similarly for s-a-1, Which detects faults 4

The Boolean difference wrt is determined as

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Test for detecting s-a-0 for

These are the tests to detect s-a-0 fault at .

Test for detecting s-a-1 for

These are the tests to detect s-a-1 fault at .

Properties of Boolean differences

• For complex circuits,a significant amount of algebraic manipulations may be required for
the determination of the Boolean differences.

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• Thie problem can be simplified by using any of the following properties.

1) 5

2) 6

3) 7

4) 8

5) 9

6) 10

If is indepent of ,then

7) 11

8) 12

Chain rule

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fig: illustration of chain rule

are inputs to the circuit.

h and g are wires.

The chain rule is .

If ,then is independent of .

If ,then is independent of .

Then,

Let and then

Further applications
It can be applied to detect faults on internal wires.

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The output equation is

at s-a-0,

at s-a-1,

Chain rule for input

Chain rule can now be applied to find tests for faults on input interms of already known
Boolean difference wrt

Wkt,

s-a-0 test for

s-a-1 test for

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Example :

Fig: A NOR logic circuit

where

Let, where and

From property (8),

s-a-0 test for

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test for s-a-0 is (0,0,0,0).

s-a-1 test for

test for s-a-1 is

Fault detection by path sensitizing

Fig : a portion of a circuit describing a sensitized path

To find s-a-1 for input A.

To find faults,there are 3 steps.

1) At the site of fault assign a logical value complementary to the fault being tested,
i.e., to test for s-aa-0 assign and to test s-a-1 assign
2) select the path from the circuit input through the site of fault to a circuit output.
The path is said to be sensitized if the inputs to the gates along the path are assigned
values so as to propagate to the path output any fault on the wires along the path. This
is called forward drive phase of the method.

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3) Determine the primary inputs that will produce all necessary signal values specified in
the previous steps.
This is obtained by tracing the signals backward from each of the gates along the path to
the primary inputs. This is called the backward trace phase of the method.

Example

Fig: path sensitizing

s-a-1 for
Backward Trace Phase for s-a-1 in path (1) as shown above

Therefore, X= {1,0,0,1,1,}
Backward Trace Phase for s-a-0 in path (1) as shown above

Therefore, X= {1,0,0,0,1,}
Backward Trace Phase for s-a-1 in path (2) as shown below

Therefore, X= {1,0,0,0,1,}

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Backward Trace Phase for s-a-0 in path (2) as shown below

Therefore, X= {1,0,0,0,0,}

Limitations of path sanitizing method

Let X={1,0,0,1,1}
Here
Here
Example:

Fig: A NOR logic circuit

Consider the fault s-a-0,here we show that it is impossible to find a test for this fault
by sensitizing a single path.
Let us choose to sensitize the path .
This requires,
.
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Since cannot be 1 and 1,it fails to detect fault.

Detection of multiple faults
• Boolean difference and path sensitizing methods can detect only one fault.
Example :

For a-test (s-a-0)

Indicates the
checkmarked onces

For ,select either 0 or 4.

For select 9.

For select either 0 or 14.

For select 15.

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s-a-0 fault tests are

for b- test (s-a-0)

Indicates the b-tests

Combining {a} and {b} we get ,{0 or 4,2 or 10,6 or 14,7,9,11,12,15} are the minimal set of tests
for network.

Test equalivalent circuit:

THEOREM: Every two level OR- AND (AND – OR) network N1 has two level AND –OR (OR-AND)
test equalivalent network N1 such that the inputs of N2 are complements of the inputs of N1.

PROOF:

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Add an inverter to the network output as shown.

Example:

OR- AND LOGIC AND-OR LOGIC(converted circuit)

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Indicates the
checkmarked onces

Map for a test:

Indicates the b-tests

Map test for b:

Minimal set of tests for networks is

Systematic generation of minimal fault detection experiments fro 2-level

networks
Generating the a-test

Step 1) construct a covering matrix E whose column headings are the prime implicants realized
by the AND gates and row headings are the minterms covered by function.

Step 2)delete all rows in E which contains two or more 1’s.

Step 3)choose arbitrarily ,for every in E one minterm such that where

= 1, if

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0, if

Generating the b-tests

Step 1) list all for all

Where is number of prime implicants and = number of literals in the prime

implicant.

Step 2) for every ,then delete from the list.

Step 3) finds all pair wise intersections of the terms that are contained in the list. Whenever an
intersection is non empty and contains a minterm for which , checkmark the two
interested terms.

Step 4) repeat step 3 until no new terms is generated.

Step 5) from the list of prime intersections constructed a list of prime tests by selecting from
each intersection an input combination for which the value of function is ‘0’.

Step 6) construct a prime test chart whose column headings are the terms of the list found
in step 2 and row headings of the prime test of step 5.

Step 7) select a set of prime tests that checks each of the terms i.e., find a cover fro the
prime test chart.

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Example :

Consider the network shown in fig, which realizes the function

Level 1 Level 2

a-tests
E matrix is

_11_ _ _001_ 11_ _1 01_00

(2) 00010 0 1 0 0
(3) 00011 0 1 0 0
(8) 01000 0 0 0 1
(12) 01100 1 0 0 1
(13) 01101 1 0 0 0
(14) 01110 1 0 0 0
(15) 01111 1 0 0 0
(18) 10010 0 1 0 0

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(19) 10011 0 1 0 0
(25) 11001 0 0 1 0
(27) 11011 0 0 1 0
(28) 11100 1 0 0 0
(29) 11101 1 0 1 0
(30) 11110 1 0 0 0
(31) 11111 1 0 1 0

Delete the rows containing more than one 1’s.( highlighted ones)

Thus ,the set of a tests are given by,

= 13
14
15
28
30

b-test
step 1)

step 2)

step 3)

step 4)

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Step 2) find the matching’s in * list

, , ,

Delete all the first minterms we get,

_1 0 0 _

_0 1 1 _

_0 0 0 _

1 0_ _ 1

11_00

00_00

01_10

01_00

Step 3) _1 0 1 _ has a non empty intersection only with 01010.

_0 1 1 _ has a non empty intersection only with 10111.

_ 0 0 0 _ has a non empty intersection only with 00000.

_ 0 0 0 _ has a non empty intersection only with 10001.

Step 4) the prime intersections are 1 1 _ 0 0 and 0 1 _ 0 0, 01010, 10111, 10001, 00000.

Step 5) find prime test.

1 1 _ 0 0 can be 11000 ( because its not present in E matrix).

1 1 _ 0 0 can be 11100 ( because it is present in E matrix).

0 1 _ 0 1 can be 01001 ( because its not present in E matrix).

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0 1 _ 0 1 can be 01101 ( because it is present in E matrix).

Delete all minterms.

Therefore, list of prime tests are 11000, 01001, 01010,10111,10001,00000.

Step 6) prime test chart

Reference is step 2 for row wise.

Reference is step 5 for column wise.

_ 101_ _011_ _000_ 10_ _1 11_00 00_00 01_10 01_01

(24) 11000 x
(9) 01001 x
(10) 01010 x x
(23) 10111 x x
(17)10001 x x
(0) 00000 x x

Check for column wise one x.

Step 7)

Therefore ,the complete fault detection experiment for the network of fig. consists of 9 tests as
follows.

13
14 2
15 3
28 18 25
24, 9, 10, 23, 0, 30, 19, 27, 8

Failure tolerant design

1) Critical errors: An error occurring on one of the redundant input’s to a specific gate is
said to be critical if it causes an incorrect gate output.
2) Sub critical errors: Occurrence at one of the redundant input’s to a gate does not cause
a fault in the gate output.

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Error classification in logic gates

Function Logic symbol Subcritical Critical Output as a
Redundancy =3 input error result of
Error critical
input error
AND 0 to 1 1 to 0 1 to 0

OR 1 to 0 0 to 1 0 to 1

NAND 0 to 1 1 to 0 0 to 1

NOR 1 to 0 0 to 1 1 to 0

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Quadded logic
Basic structure:

Fig : basic alternating AND –OR quadded structure

Fig : basic alternating NAND –NOR quadded structure

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Construct the quadded realized circuit for the circuit shown below.

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Fig: quadded realized circuit

General quadded design procedure

Fig :illustration of danger in incorrect connection patters

Example:

Fig: original redundant circuit

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Inured to convert the above circuit into quadded logic, add inverters near inputs of the
gates which are placed before inverter in the above circuit.

Fig: converted circuit

Fig : quadded form of converted circuit.

Exercise problem 8.9

In the gate network shown below, only wires q may become either s-a-0 or s-a-
1,while the remaining wires are considered safe.
a) Construct fault table
b) Find minimal cover of the table and use it to determine the minimum fault detection
experiment.
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c) Find the preset fault location experiments and show its fault dictionary.

Solution:

FAULT TABLE

Inputs Outputs Output in presence of faults

0000 0 0 0 0 0 1 1 1 1

0001 0 0 0 0 0 1 1 1 1

0010 0 0 0 0 0 1 1 1 1

0011 1 1 0 1 0 0 1 1 1

0100 0 0 0 0 0 1 1 1 1

0101 0 0 0 0 0 1 1 1 1

0110 0 0 0 0 0 1 1 1 1

0111 1 1 0 1 0 0 1 1 1

1000 0 0 0 0 0 1 1 1 1

1001 0 0 0 0 0 1 1 1 1

1010 0 0 0 0 0 1 1 1 1

1011 1 1 0 1 0 0 1 1 1
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1100 1 0 1 0 1 1 0 1 1

1101 1 0 1 0 1 1 0 1 1

1110 1 0 1 0 1 1 0 1 1

1111 0 1 1 0 0 0 0 1 1

Inputs Outputs Output in presence of faults

0000 0 1 1 1

0001 0 1 1 1

0010 0 1 1 1

0011 1 1 1 1

0100 0 1 1 1

0101 0 1 1 1

0110 0 1 1 1

0111 1 1 1 1

1000 0 1 1 1

1001 0 1 1 1

1010 0 1 1 1

1011 1 1 1 1

1100 1 1 1 1

1101 1 1 1 1

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1110 1 1 1 1

1111 0 1 1 1

Hence, there are four essential tests. {0000, 0011, 1100, 1111}.

Fault dictionary

Exercise problem 8.21:

Show a quadded realization of the circuit shown below. Indicate the correction of longest
propagated error.

Fig : original irredundant circuit

To obtain the converted circuit, put not gates before AND and convert AND to OR.

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Fig: converted circuit

Form the quadded form of converted circuit.

Fig: quadded form of original circuit

Fig: Error propagation

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