EEE-4131: Thermal Oxidation of Silicon Lecture-05

©ADNAN AMIN SIDDIQUEE 1

 CONTENTS
01 Oxide Layers

02 Production Methods

03 Thermal Oxidation Process

04 Oxide Growth Geometry

05 Silicon Oxidation Model

06 Defects in Oxide Layer

2
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 Oxide Layers

Thin dielectric layer between the wafer and channel. (Gate Oxide)
High-quality electrical insulator to isolate devices (Field Oxide/LOCOS, STI)
Surface passivation. (Protects from scratch and tear)
Protects Junction from moisture and atmospheric contaminant.
Diffusion/implantation barrier.
A thin native oxide layer is always present on silicon due to atmospheric oxidation.

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 Production Methods
Oxidation Processes

Thermal Oxidation

Vapor Phase Oxidation

Plasma Oxidation

Anodic Oxidation

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 Thermal Oxidation Process
Clean the wafer and furnace.
Put wafers in the boat.
Load the wafer boat to the furnace with N2 gas flow.
Ramp up the temperature up to the process temperature.
Dry O2 or H2O flow until the oxidation is complete.
Stop oxidation by the flow of N2 gas.
Ramp down the temperature.
Unload the wafer boat.
Thermally grown oxides are pure, stable, good insulator
and have excellent Si-SiO2 interface with low electrical
defects.

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 Thermal Oxidation Process
Dry Oxidation Wet Oxidation
Silicon is oxidized with oxygen gas. Silicon is oxidized with steam or water vapor.
Chemical Reaction: Chemical Reaction:
𝑆𝑖 + 𝑂2 → 𝑆𝑖𝑂2 𝑆𝑖 + 2𝐻2𝑂 → 𝑆𝑖𝑂2+2𝐻2
Oxidizes at a lower rate. Oxidizes at a much higher rate.
High quality dense and uniform films are obtained. Low quality porous films are obtained.
Typically used to grow thin films. Typically used to grow thick films.
Low charge trap. Pitting effect due to H20 formation.

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 Oxide Growth Geometry

▪ When oxide is grown, the resulting oxide expands.

▪ The final oxide layer is approximately 54% above and 46% below the original surface.

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 Silicon Oxidation Model (Deal and Grove’s Model)
Bruce Deal and Andy Grove developed a simple kinetic mechanism/model for oxide growth.
The model assumes there is a finite(thin) oxide layer, before thermal oxidation starts.
When a silicon substrate comes into contact with an oxidant, following three mechanisms occurs-
▪ Oxygen diffuses through the gas to the wafer.
▪ Oxygen molecules diffuse through the existing SiO2 layer at high temperatures.
▪ Oxygen molecules arriving at the silicon surface enter into a chemical reaction and form SiO2.

Limitations:
▪ One dimensional model
▪ Not accurate for heavily doped silicon.
▪ Not accurate for thin oxides.

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 Silicon Oxidation Model (Deal and Grove’s Model)
In the presence of a thin oxide layer, the kinetics of oxide growth on silicon can be described in three steps
The oxygen species transport from the bulk of the gas phase to the gas-oxide
interface with flux (𝐽1 )
𝜕𝑁
𝐽1 = −𝐷𝐺 𝑁𝐺 = 𝑜𝑥𝑖𝑑𝑎𝑛𝑡 𝑐𝑜𝑛𝑐. 𝑖𝑛 𝑡ℎ𝑒 𝑏𝑢𝑙𝑘 𝑜𝑓 𝑜𝑓 𝑡ℎ𝑒 𝑔𝑎𝑠
𝜕𝑥
𝑁 −𝑁 𝑁𝑆 = 𝑜𝑥𝑖𝑑𝑎𝑛𝑡 𝑐𝑜𝑛𝑐. 𝑎𝑡 𝑔𝑎𝑠 − 𝑆𝑖𝑂2 𝑖𝑛𝑡𝑒𝑟𝑓𝑎𝑐𝑒 𝑖𝑛 𝑔𝑎𝑠 𝑝ℎ𝑎𝑠𝑒
⇒𝐽1 = −𝐷𝐺 𝑆 𝐺
𝑡 ℎ𝑔 = 𝑀𝑎𝑠𝑠 𝑡𝑟𝑎𝑛𝑠𝑝𝑜𝑟𝑡 𝑐𝑜𝑒𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑡
𝑁𝐺 − 𝑁𝑠 𝑃𝑠 = 𝑃𝑎𝑟𝑡𝑖𝑎𝑙 𝑝𝑟𝑒𝑠𝑠𝑢𝑟𝑒 𝑜𝑓 𝑡ℎ𝑒 𝑔𝑎𝑠 𝑗𝑢𝑠𝑡 𝑎𝑏𝑜𝑣𝑒 𝑠𝑜𝑙𝑖𝑑 𝑆𝑖𝑂2
⇒𝐽1 ≈𝐷𝐺
𝑡 𝑃𝐺 = 𝑃𝑎𝑟𝑡𝑖𝑎𝑙 𝑝𝑟𝑒𝑠𝑠𝑢𝑟𝑒 𝑜𝑓 𝑡ℎ𝑒 𝑔𝑎𝑠 𝑖𝑛 𝑡ℎ𝑒 𝑏𝑢𝑙𝑘
⇒𝐽1 ≈ ℎ𝑔 (𝑁𝐺 − 𝑁𝑠)
𝑃 𝑃
𝐵𝑢𝑡, 𝑁𝐺 = 𝐺 and 𝑁𝑠 = 𝑆 ; 𝑇ℎ𝑢𝑠, 𝐽1 = ℎ(𝑃𝐺 − 𝑃𝑠)
𝐾𝑇 𝐾𝑇
Oxidant reaches the Oxide surface with concentration 𝑁0 and diffuses through the
𝑆𝑖𝑂2 layer with flux (𝐽2 ) 𝑁0 = 𝑜𝑥𝑖𝑑𝑎𝑛𝑡 𝑐𝑜𝑛𝑐. 𝑎𝑡 𝑔𝑎𝑠 − 𝑆𝑖𝑂2 𝑖𝑛𝑡𝑒𝑟𝑓𝑎𝑐𝑒
𝜕𝑁 𝐷(𝑁𝑖 −𝑁0) 𝑖𝑛 𝑠𝑜𝑙𝑖𝑑 𝑝ℎ𝑎𝑠𝑒
𝐽2 = −𝐷 =− … … … (i) 𝑁𝑖 = 𝑜𝑥𝑖𝑑𝑎𝑛𝑡 𝑐𝑜𝑛𝑐. 𝑎𝑡 𝑡ℎ𝑒 𝑆𝑖𝑂2 − 𝑆𝑖 𝑖𝑛𝑡𝑒𝑟𝑓𝑎𝑐𝑒
𝜕𝑥 𝑋0
𝑋0 = Thickness of SiO2
𝑤ℎ𝑒𝑟𝑒, 𝑁0 = 𝐻𝑃𝑠 = 𝐻𝑁𝑆 𝐾𝑇 𝐻 = 𝐻𝑒𝑛𝑟𝑦 ′ 𝑠 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡
Oxidant reaches at 𝑆𝑖𝑂2 − 𝑆𝑖 interface and then reacts with 𝑆𝑖 with flux (𝐽3 ).
According to rate law It is assumed that flux at the 𝑆𝑖𝑂2 − 𝑆𝑖 interface is
𝐽 = 𝑁𝑜. 𝑜𝑓 𝑜𝑥𝑦𝑔𝑒𝑛 𝑚𝑜𝑙𝑒𝑐𝑢𝑙𝑒𝑠 𝑡ℎ𝑎𝑡 𝑐𝑟𝑜𝑠𝑠𝑒𝑠 𝑎 𝑝𝑙𝑎𝑛𝑒 𝑜𝑓 proportional to 𝑁𝑖 𝐽 ∝𝑁 3 𝑖
𝑐𝑒𝑟𝑡𝑎𝑡𝑖𝑛 𝑎𝑟𝑒𝑎 𝑖𝑛 𝑐𝑒𝑟𝑡𝑎𝑖𝑛 𝑡𝑖𝑚𝑒 𝐽3 = 𝐾𝑠 𝑁𝑖 … … … (ii) 𝑘𝑠 = 𝑅𝑒𝑎𝑐𝑡𝑖𝑜𝑛 𝑅𝑎𝑡𝑒 𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡

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 Silicon Oxidation Model (Deal and Grove’s Model)
At equilibrium (steady state), 𝐽1 = 𝐽2 = 𝐽3 = 𝐽
The rate of change of oxide thickness of the oxide layer,
𝐷(𝑁𝑖 −𝑁0) 𝐷
From equation (i), 𝐽2 = 𝐽 = − 𝑋0
=
𝑋0
(𝑁𝑖 − 𝑁0)
From equation (ii) 𝑑𝑥0 𝐽 𝑫𝑵𝟎 𝐷𝑁0
⇒ 𝐽=
𝐷 𝐽
− 𝑋 (𝐾 − 𝑁0) 𝐽3 = 𝐽 = 𝐾𝑠 𝑁𝑖 ⇒ = = [ Using equation (iii) 𝐽 = ]
𝑑𝑡 𝑁 𝑵(𝑿𝟎+ 𝑫 ) (𝑋0+ 𝐷 )
0 𝑠 𝐽 𝑲𝒔 𝐾𝑠
⇒ 𝑁𝑖 = 𝐾 [ Here, N = number of oxygen molecules per unit volume ]
𝑠
𝐷 𝐽 𝐷 𝐷 𝐷𝑁0
⇒𝐽 =− + 𝑁0 ⇒ 𝑋0 + 𝑑𝑥0 = 𝑑𝑡
𝑋0 𝐾𝑠 𝑋0 𝐾𝑠 𝑁

𝐷𝑁0
𝐷 𝐽 𝐷 ⇒‫𝑋 ׬‬0 + 𝐷 𝑑𝑥0 = ‫׬‬ 𝑑𝑡 [integrating both sides]
⇒𝐽+ = 𝑁0 𝐾𝑠 𝑁
𝑋0 𝐾𝑠 𝑋0
𝑋02 𝐷𝑁0 [ C = integration constant ]
𝐷 1 𝐷𝑁0 ⇒ + 𝐷𝑋0 = 𝑡+𝐶
⇒𝐽 1+ = 2 𝐾𝑠 𝑁
𝑋0 𝐾𝑠 𝑋0
2𝑋02 2𝐷𝑁0
𝑋0𝐾𝑠 + 𝐷 𝐷𝑁0
⇒ + 2𝐷𝑋0 − 𝑡=𝐶
2 𝐾𝑠 𝑁
⇒ 𝐽( )=
𝑋0𝐾𝑠 𝑋0
2𝐷𝑁0
⇒𝑋02 + 2𝐷𝑋0 − 𝑡=𝐶
𝐷𝑁0 𝑋0𝐾𝑠 𝐾𝑠 𝑁
⇒𝐽 = ∗( )
𝑋0 𝑋0𝐾𝑠 + 𝐷 2𝐷𝑁0
⇒𝑋02 + 𝐴𝑋0 − 𝐵𝑡 = 𝐶 … … … (iv) [ Let, 𝐴 = 2𝐷 𝑎𝑛𝑑 𝐵 = ]
𝐾𝑠 𝑁
𝐷𝑁0 𝐾𝑠
⇒𝐽 =
𝐾𝑠 (𝑋0 + 𝐷 ) Applying the boundary condition 𝑋0(𝑡 = 0) = 𝑋𝑖 in equation (iv)
𝐾𝑠
𝑫𝑵𝟎 ⇒C = 𝑋𝑖2 + 𝐴𝑋𝑖 … … … (v) [ Xi = Initial thickness of oxide on the wafer]
⇒𝑱=
(𝑿𝟎 + 𝑫 )
𝑲𝒔
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 Silicon Oxidation Model (Deal and Grove’s Model)
Substituting the value of C in equation (iv),
⇒ 𝑋02 + 𝐴𝑋0 − 𝐵𝑡 = 𝑋𝑖2 + 𝐴𝑋𝑖

⇒ 𝑋02 + 𝐴𝑋0 − 𝐵𝑡 − (𝑋𝑖2 + 𝐴𝑋𝑖 ) = 0

𝑋𝑖2 𝐴
⇒ 𝑋02 + 𝐴𝑋0 − B(𝑡 + + 𝑋𝑖 ) = 0 𝑋𝑖2 𝐴
𝐵 𝐵
𝐿𝑒𝑡, 𝜏 = + 𝑋
𝐵 𝐵 𝑖
⇒ 𝑋02 + 𝐴𝑋0 − B(𝑡 + 𝜏) = 0 ℎ𝑒𝑟𝑒, 𝜏 =time required to grow the initial oxide

−𝐴 ± 𝐴2 − 4𝐵 {−(𝑡 + 𝜏)}
⇒𝑋0 =
2

1 𝐵 𝑡+𝜏
⇒𝑋0 = −𝐴 ± 𝐴2 + 4 𝐴2
2 𝐴2

1 4𝐵
⇒𝑋0 = 𝐴 −1 ± 1 + 𝑡+𝜏
2 𝐴2

Considering the positive value of 𝑋0

𝐴 4𝐵 𝐴 𝑡+𝜏 2𝐷𝑁0
⇒𝑋0 = 1+ 2 𝑡+𝜏 −1 = 1+ 𝐴2 − 1 … … … (vi) [ Where, 𝐴 = 2𝐷 𝑎𝑛𝑑 𝐵 = ]
2 𝐴 2 𝐾𝑠 𝑁
4𝐵

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 Silicon Oxidation Model (Deal and Grove’s Model)
𝑨𝟐
For small oxidation time, i.e. early stage of the oxide growth, [ 𝒕 + 𝝉 ≪ ],
𝟒𝑩

𝐴 𝑡+𝜏
from the equation (vi) , 𝑋0 = 1+ 𝐴2 −1
2
4𝐵

𝑛(𝑛−1) 𝑛(𝑛−1)(𝑛−2)
𝐴 1 𝑡+𝜏 [Using Binomial expansion: (1 ± 𝑥)𝑛 = 1 ± 𝑛𝑥 + 𝑥2 ± 𝑥3 + ⋯ ]
⇒𝑋0 ≈ 1+ ∗ +⋯ −1 2! 3!
2 2 𝐴2
4𝐵 [for small values of 𝑡 + 𝜏 we exclude the powers of 𝑡 from the binomial expansion]
𝐵 𝐵 𝑁0𝐾𝑠
⇒𝑋0 ≈ 𝑡+𝜏 [Here, = = 𝑙𝑖𝑛𝑒𝑎𝑟 𝑟𝑎𝑡𝑒 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡]
𝐴 𝐴 𝑁

So, Oxide thickness is linear to time for sufficiently thin oxide.

Initial oxide growth is controlled by the reaction rate of oxidant and silicon as the amount of oxidant reaching the interface is large in amount.
𝑨𝟐
For larger oxidation time i.e. later stage of the oxide growth [𝒕 ≫ 𝝉 and 𝒕 + 𝝉 ≫ ]
𝟒𝑩
𝐴 𝑡+𝜏
from the equation (vi), 𝑋0 = 1+ 𝐴2 −1
2
4𝐵

𝐴 4𝐵 𝑡
⇒𝑋0 ≈ −1
2 𝐴2
𝐴 4𝐵 𝑡 𝐴
⇒𝑋0 ≈ 2 −
2 𝐴 2
2𝐷𝑁0
⇒ 𝑋0 ≈ 𝐵 𝑡 [Here, 𝐵 = = 𝑃𝑎𝑟𝑎𝑏𝑜𝑙𝑖𝑐 𝑟𝑎𝑡𝑒 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡]
𝑁
So, Oxide thickness is parabolic to time for sufficiently thick oxide
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 Defects in Oxide Layer
Fixed Oxide Charge
▪ Si diffuses to oxide layer.
▪ Causes stacking faults.
▪ Annealing in N2 and halogenic oxidation can reduce it.
Interface Trapped Charge
▪ Occurs due to dangling bonds
▪ Causes hot electron effect, leakage current, and short
lifetime of the device, shifts the n/p behavior of a
transistor.
▪ H-anneal at low temperature can reduce it.

Oxide Trapped Charge

• Occurs due to broken Si-0 bonds in Si.
• H-anneal at low temperature can reduce it.

Mobile Ionic Charge

▪ During handling Na and K ion can get into the oxide.
▪ Occurs due to impurity diffusion in the existing SiO2 layer.
▪ Halogenic oxidation can reduce it.

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 Mathematical Problem
A Silicon wafer is oxidized in dry O2 at 1200o C for 1 hour. Using the limiting conditions of Deals and Grove’s model,
a) Estimate the thickness of the oxide grown?
b) The wafer is put back in the furnace in wet O2 at 1200o C. How long it will take to grow an additional 0.1 µm of oxide?
c) How much silicon is consumed?
The values of constants at the operating temperature are as follows:

Process A (µm) B (µm2/h) 𝜏 (h)

Wet Oxidation 0.05 0.72 -

Dry Oxidation 0.04 0.045 0.027

A bare Silicon wafer is oxidized for 1.5 hours at 1000o C in steam. Then some portion of the grown oxide is etched due to the presence of
hollow oxide. After that, the wafer is put back into the steam at 920o C for reoxidation. If 0.45 µm of oxide is etched prior to
reoxidation, estimate the time required to grow overall 5000 Å oxide in the final step.
The values of constants at the operating temperature are as follows:
Process Temp A (µm) B (µm2/h)
920o C 0. 50 0.203

1000o C 0.226 0.287

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 References
VLSI Fabrication Principles by Sorab K Ghandhi.
VLSI Technology by S. M. SZE.
The Science and Engineering of Microelectronic Fabrication by Stephen A. Campbell.
Silicon VLSI Technology by Plummer, Deal, and Griffin

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 Any
QUESTIONS

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 EEE-4131: Deposition Lecture-06
©ADNAN AMIN SIDDIQUEE 1
 CONTENTS
01 What is Deposition?

02 Purpose of Deposition

03 PVD Process

04 Metal Interconnection

05 CVD Process

06 Features for Better Deposition

2
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 What is Deposition?

Transfers a layer of materials on the surface of a wafer from a source by maintaining uniform thickness.
The deposited layers are not fully dense, and that is why they are referred to as thin films.
The films are either epilayers, metals, metal-silicide, polymer and dielectrics (SiO2, SiNx).
Purpose of deposition
▪ Insulation
▪ Protective cover
▪ Mask/Pattern design
▪ Self-aligned gate design
▪ Contact formation
▪ Device Interconnection
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 Deposition Techniques
Deposition

Physical Deposition Chemical Deposition

(metallization/PVD) (CVD)

Atmospheric Plasma-Enhanced
Low Pressure CVD
Vacuum Evaporation Sputtering Pressure CVD CVD
(LPCVD)
(APCVD) (PECVD)

• PVD=Physical vapor deposition

• CVD=Chemical vapor deposition

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 PVD (Evaporation)
Evaporation is performed in high vacuum chamber.
The source material is placed in a crucible and heated until it melts and
reaches the evaporation temperature.
The evaporated material is transported to the target substrate.
The vaporized source molecules hits the cold substrate surface
Molecules will transfer their energy to the substrate, lower their
temperature, sticks and condense.
The deposition rate depends on the evaporation rate, the angle, and the
distance between the source and the substrate.
Suitable for deposition of metallic thin films.
Compounds, alloys, and polysilicon don’t deposit well.
Step coverage is not very good because the vapor flows ballistically.
Resistive heating or RF heating or E-beam guns can be used for
Vacuum Evaporation System
evaporating the material.

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 PVD (Sputtering)
(-)Cathode The process is carried out in a vacuum chamber.
Noble gas such as Argon is used as a sputtering gas due to low reactivity.
Ar+ RF power is used to create plasma from the sputtering gas.
6
Low-pressure Ar+ ion is generated in a glow discharge (plasma).
The target is clamped on the cathode and the substrate is on the anode.
Ar+ ions bombard the target and cause the transport of sputtered atoms
on the substrate.

Anode(+)
Sputtering rate can be enhanced by using DC bias/magnetic field.
Sputtered atoms condense on the substrate.
Better film quality and step coverage than evaporation.
Sputtering System The substrate may damage due to bombardment.

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 Metal Interconnection

Multilevel Interconnect Structure

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 Metal Interconnection

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 Chemical Vapor Deposition (CVD)
CVD is used to deposit most dielectrics, silicon, epitaxial films and some metals.
It is performed in a furnace.
Reactants are in gas phase and they are pumped into the furnace.
Reactants gas can be activated by heat or plasma pressure.
Reactants transports(through diffusion) to wafer surface
Then absorbs on the surface of wafer.
The reaction occurs on the wafer surface of wafer and deposition occurs.
Byproducts desorption occurs.
Byproducts are then transported into the gas stream and pumped away.
It has high growth rate, better film quality, more conformal step coverage and good reproducibility.
Can deposit materials which are hard to evaporate and can grow epitaxial films.
Complex process, high process temperature and gases can be toxic and corrosive.

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 Atmospheric Pressure CVD

The cold wall system Conveyer belt system

Atmospheric cold wall system is used for deposition.

High deposition rate than LPCVD.
Film thickness is non-uniform and step coverage is poor.
No reaction on the side wall.
Difficult to control the temperature
Used for deposition of epitaxial silicon and thick oxide(field oxide).
450o C
Chemical Reactions 𝑆𝑖𝐻4 + 02 𝑆𝑖𝑂2 + 2𝐻2
650-750o C Silane Based
TEOS 𝑆𝑖 𝐶2𝐻50 450o C
4 + 1202 𝑆𝑖𝑂2 + 8𝐶𝑂2 + 10𝐻20
𝑆𝑖𝐻4 + 2𝑁20 𝑆𝑖𝑂2 + 2𝑁2 + 2𝐻2

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 Low Pressure CVD

The hot wall system

Low pressure hot wall system is used.
Requires vacuum.
Lower deposition rate than APCVD.
Excellent purity, uniformity and step coverage.
Used for deposition of polycrystalline and amorphous films such as polysilicon and silicon dioxide.
Contamination is high and requires periodic cleanup.
Chemical Reactions
575 - 650o C
𝑆𝑖𝐻4 𝑆𝑖 + 2𝐻2 Pyrolyzing reaction
Silane

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 Features for Better Deposition
Growth Habit
▪ High surface mobility and low nucleation is required for polycrystalline film growth(polysilicon).
▪ Low surface mobility and high nucleation rate for amorphous film growth (oxide and nitride films).
▪ Desired composition with low contamination.

Film Uniformity
▪ Across wafer uniformity.
▪ Run to run uniformity.
Adhesion
▪ A clean Environment is required for good adhesion.
▪ Sometimes additional materials are used for a better “glue” process. (chromium and titanium)
Mechanical Properties
▪ Films are stressed due to mismatch in coefficient of thermal expansion.
▪ Stress is measured as a change in the wafer bow before and after deposition.
▪ Less mechanical stress is desired for better deposition.

Good electrical properties of films are desired.

Metal interconnects should have low resistivity and high current density.

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 Features for Better Deposition
Step Coverage
▪ In conformal step coverage, the deposited layer thickness is uniform on both horizontal and vertical surfaces.
▪ In non-conformal step coverage, the sidewall shadow causes uneven thickness on horizontal and vertical surfaces.
▪ Conformal step coverage is good for electrical connection.

Electromigration
▪ Transport of mass due to high current density in metals causes damage like pilling up and void formation.
▪ Better electromigration resistance is desired.

Process should not contaminate the wafer.

Process should be compatible to other processes in IC fabrication.
©ADNAN AMIN SIDDIQUEE 13
 References
VLSI Fabrication Principles by Sorab K Ghandhi.
VLSI Technology by S. M. SZE.
The Science and Engineering of Microelectronic Fabrication by Stephen A. Campbell.
Silicon VLSI Technology by Plummer, Deal, and Griffin
Introduction to Microelectronic Fabrication by Richard C. Jaeger

©ADNAN AMIN SIDDIQUEE 14

 Any
QUESTIONS

©ADNAN AMIN SIDDIQUEE 15

 EEE-4131: Epitaxy Lecture-07
©ADNAN AMIN SIDDIQUEE 1
 CONTENTS

01 What is Epitaxy?

02 Types of Epitaxy

03 Methods of Epitaxy

04 Epitaxial Defects

2
©ADNAN AMIN SIDDIQUEE 2
 What is Epitaxy?
The term epitaxy comes from the Greek words epi (upon) and taxis (an ordered manner).
Epitaxy is the process of depositing pure single-layer crystal film.
Lower temperature process compared to diffusion.
Temperature and substrate type determines the physical structure of deposited films.
Provides a clean, flat layer on top of the less ideal Silicon substrate.
Higher purity films on top of the lower quality substrate can be deposited. (e.g. SiC)
The top Silicon layer of SOI and SOS structure is formed through epitaxy.
The buried layer of a bipolar transistor is produced through epitaxy.
Optical coatings and protective coating are made through epitaxy.
Can combine Silicon substrate with compound semiconductor films. (e.g. HEMTs ,HBTs)

©ADNAN AMIN SIDDIQUEE 3

 Types of Epitaxy
Epitaxy

Homo Epitaxy Hetero Epitaxy

©ADNAN AMIN SIDDIQUEE 4

 Methods of Epitaxy
Methods for Epitaxial Deposition

Liquid Phase Epitaxy(LPE)

Vapor Phase Epitaxy(VPE)

Molecular Beam Epitaxy (MBE)

Solid Phase Epitaxy (SPE)

©ADNAN AMIN SIDDIQUEE 5

 Liquid Phase Epitaxy (LPE)
Tipping Technique Direct Immersion

Sliding Boat Technique

©ADNAN AMIN SIDDIQUEE 6

 Liquid Phase Epitaxy (LPE)

Grows epilayer via the direct precipitation of epi material onto the substrate from super saturated solvent.
The substrate is dissolved in the melt of another material.
Temperature is increased until a phase transition occurs and then reduced for precipitation.
Layer growth can be controlled by controlling the cooling rate.
By controlling cooling rates the kinetics of layer growth can be controlled.
It is a low-cost method yielding films of controlled composition, thickness, and lower dislocation density.
Used for growing GaAs and other III-V compounds.
©ADNAN AMIN SIDDIQUEE 7
 Vapor Phase Epitaxy (VPE)
VPE is a specific form of chemical vapor deposition.
In VPE epitaxial layer deposition takes place in reactors.
Materials of epitaxial film are transported to the deposition region in the form of gas.
Liquid with very high pressure may also be used.
The gas molecules absorbs at the surface.
Then the surface reaction occurs and there will be deposition.
There can be reaction byproduct which is transported away from the deposition region.
Process can be carried out in atmospheric pressure.
It can handle several wafers.
Growth rate is high.

©ADNAN AMIN SIDDIQUEE 8

 Silicon Deposition Using VPE

The wafer is etched, cleaned, and degreased before transferring it to the reactor.
H2 Carrier gas purges the reactor air.
Reactor is heated to 1150-1200oC for a few minutes and then reduced to growth temperature.
HCL gas is flown to clean the native oxide of wafer.
The source material for Silicon deposition is introduced with hydrogen carrier gas.
For Silicon deposition Silane (SiH4), Silicon Tetrachloride (SiCl4), Trichlorosilane (SiHCl3) can be used as source gas.
Once the growth is complete the source flows are eliminated usually by shutting power off.
As the reactor cools to ambient temperature the H2 gas is replace with N2 so that rector can be operated safely.
Overall reaction at 12000 C : SiCl4 (g) +2H2 (g) ⇋ Si (s) + 4HCl (g)

©ADNAN AMIN SIDDIQUEE 9

 VPE Reactor Configuration: Horizontal
RF

Gas inlet vent

Horizontal Reactor

Atmospheric pressure cold wall system is used for depositing epi layer.
The wafers are placed on a tilted susceptor.
RF heating coil heats the susceptor only.
The deposition rate is high but cant achieve uniform thickness.
Throughput is low.
Low-cost construction.
©ADNAN AMIN SIDDIQUEE 10
 VPE Reactor Configuration: Radiant Barrel
Gas inlet

Radiant
Heaters

Barrel Reactor

Wafer slices are held(by gravity) in a slightly sloping vertical wall of a large cylindrical carrier.
Radiant heating is used to maintain the process temperature of the reactor.
Gas flow is parallel to the wafer slices.
Better quality of deposition than the horizontal reactor.
Suitable for large batch production(High Throughput).
©ADNAN AMIN SIDDIQUEE 11
 VPE Reactor Configuration: Vertical(Pancake)

vent
Gas inlet

Vertical (Pancake) Reactor

Wafers are placed on a rotating holder.
RF heating is used to maintain the process temperature.
Gas flows at the right angle to the surface.
Throughput is low.
Complex mechanical design.
©ADNAN AMIN SIDDIQUEE 12
 Molecular Beam Epitaxy (MBE)
The environment is highly controlled (Ultra High Vacuum).
The substrate is mounted on a molybdenum heating block.
In-situ cleaning is done before the process starts.
MBE materials are introduced from effusion cells.
Effusion (Kunudsen) cells generates evaporated beams of materials.
Several beams(sources) impinges on a heated substrate.
The molecules from beam reaches the surface of substrate then condense on the
substrate and may react with each other.
Computer controlled mechanical shutters of each effusion cells allows precise
control of thickness, flow rate, chemical composition, and doping.
Capable of in-situ characterization.
[Reflected high energy electron diffraction (RHEED), Mass Spectrometer, X-ray
Photoelectron Spectroscopy(XPS)]
High quality extremely thin films can be fabricated in very precise and
controlled way.

©ADNAN AMIN SIDDIQUEE 13

 Epitaxial Defects

Shift in Pattern
▪ A lightly doped epi-layer is introduced in a heavily doped wafer to reduce parasitic resistance.
▪ Transistors are formed in the epi-layer and the heavily doped wafer is a buried layer.
▪ It is necessary to align the upper layers with the buried layers that’s why before growing epilayer alignment mark is etched.
▪ Alignment marks shifts if the growth rate is non uniform.
▪ Due to growth rate and chlorine content precursors pattern shift occurs.
©ADNAN AMIN SIDDIQUEE 14
 Epitaxial Defects

Selective Epitaxial Growth(SEG)

▪ Epi-layer is grown in some regions of the wafer and not deposited in other regions.
▪ SEG applications are device isolation, trench isolation filling, formation of elevated source/drain structure of MOS.
▪ Problems with selective growth include faceting and thickness variations.
▪ Faceting is a nonplanar of the surface due to a lower growth rate along the various crystal planes.

©ADNAN AMIN SIDDIQUEE 15

 References
VLSI Fabrication Principles by Sorab K Ghandhi.
VLSI Technology by S. M. SZE.
The Science and Engineering of Microelectronic Fabrication by Stephen A. Campbell.
Silicon VLSI Technology by Plummer, Deal, and Griffin
Introduction to Microelectronic Fabrication by Richard C. Jaeger

©ADNAN AMIN SIDDIQUEE 16

 Any
QUESTIONS

©ADNAN AMIN SIDDIQUEE 17

 EEE-4131: LATCH-UP IN CMOS Lecture-7B
©ADNAN AMIN SIDDIQUEE 1
 CONTENTS

01 Latch-up in CMOS

02 Latch-up Prevention Techniques

2
©ADNAN AMIN SIDDIQUEE 2
 Latch-up in CMOS
Input

G Output G
VDD
Vss S D D S
oxide oxide
n+ n+ p+ p+
Q1 Rwell

Q2 n-well
Rsubstrate

p-substrate

©ADNAN AMIN SIDDIQUEE 3

 Latch-up in CMOS
If Voutput > VDD
▪ The PMOS drain(p+) and N-Well junction will be forward biased. p+
▪ Holes will be injected from the Darin region to PMOS.
▪ The current due to hole injection will flow from the PMOS drain to Vss.
▪ The current will turn on the Q1 parasitic transistor.
▪ The base current of Q1 is the collector current of the Q2 parasitic transistor.
▪ This will turn on the Q2 transistor.
If Voutput < VSS
▪ The NMOS drain(n+) and p-substrate junction will be forward biased.
▪ Electrons will be injected from the drain(n+) region to p-substrate.
▪ The injected electron will flow from NMOS drain to VDD
▪ The current due to electron injection will turn on the Q2 parasitic transistor.
▪ The base current of Q2 is the collector current of the Q1 parasitic transistor.
▪ This will turn on the Q1 transistor. Latchup equivalent circuit

From the above conditions, we can say that if any of the parasitic transistors operate, it turn-ons another transistor. Thus the current gain
increases. This current will cause device failure.
To prevent this current flow we have to stop the injected minority electrons to flow from the p-substrate to VDD and minority holes from the N-
well region to the ground(VSS).

©ADNAN AMIN SIDDIQUEE 4

 Latch-Up Prevention
Tap Cell/ Substrate Contact
▪ Add “Well” and “Substrate Contacts” of the appropriate type to reduce the substrate resistance and well resistance.
▪ Place substrate contact as close as possible to the source connection of the substrate.
▪ Substrate contact should be connected to metal to a supply pad.

Guard Rings CMOS with substrate contact

▪ PMOS encircles n+ guard ring connected to VDD to collect the minority carriers.
▪ NMOS encircles p+ guard ring connected to VSS or GND to collect the minority carriers.

©ADNAN AMIN SIDDIQUEE 5

 Latch-Up Prevention
Epitaxial Layer
▪ P- epitaxial layer in P+ substrate.
▪ Using retrograde well doping.

P- epilayer on P+ substrate Retrograde well

Use of epitaxial substrate with retrograde well doping configuration.

©ADNAN AMIN SIDDIQUEE 6

 Latch-Up Prevention
Isolation
▪ Increase the separation between MOS devices.
▪ Trench technology. (isolates well from the substrate with deep trenches of polysilicon).

Trench isolation

CMOS with trench isolation and P- epiplayer on P+ substrate

Use of SOI structure.

The use of gold impurities in the substrate will minimize the lifetime of the minority carrier.

©ADNAN AMIN SIDDIQUEE 7

 Any
QUESTIONS

©ADNAN AMIN SIDDIQUEE 8

 EEE-4131: Lithography Lecture-09
©ADNAN AMIN SIDDIQUEE 1
 CONTENTS
01 What is Lithography?

02 Mask and Photoresist

03 Photolithography Process

04 Effect of Photoresist

05 Problem Areas in Photolithography

06 Electron Beam Lithography

2
©ADNAN AMIN SIDDIQUEE 2
 Lithography
Lithography comes from the Greek words lithos (means stone) and graphein (means write) which means “writing a pattern
in the stone”.
It is a method that transforms complex circuit patterns to wafer.
The lithography process decides the miniaturization of device manufacturing
A large number of lithography step is needed for IC fabrication.
Accounts for one-third of the total IC fabrication cost.
Lithography is the workhorse of the semiconductor industry.
Lithography is a process by which pattern transfer and precise positioning of various layers such as,
▪ Base emitter in BJT
▪ Drain and source in MOSFET
▪ Gate in MOSFET
▪ Ohmic contact.
▪ Metallization
▪ Buried layer of BJT
▪ Isolation Wall

©ADNAN AMIN SIDDIQUEE 3

 Mask
Mask
▪ High precision plates containing microscopic images of IC.
▪ Each layer of an IC has its own mask.
▪ It is a darker(opaque) plate with holes or transparencies so that
light/energy can pass.
▪ Pattern from a mask transferred to a photoresist.

Reticle Mask
▪ Circuit or device designer produces reticle mask.
▪ Reticle mask is referred as master template.

Working Mask
▪ Printed mask of a specific layer
▪ Designers’ information is transferred to fabrication by the photomask.
▪ Each photomask is used for thousand of wafer preparation.

©ADNAN AMIN SIDDIQUEE 4

 Types of Lithography Process
Lithography Processes

Photolithography

Electron Beam Lithography

X-Ray Lithography

Ion Beam Lithography

©ADNAN AMIN SIDDIQUEE 5

 Photolithography Process (Techniques)

Contact Proximity Projection

▪ Resist coated silicon wafer is brought ▪ Same as contact method except for a ▪ The mask is physically separated from the
into physical contact with the photomask. small gap of 10 to 25u to minimize the wafer and an optical system is used to
▪ Hard contact between the mask and the mask damage. project an image of the mask on the wafer.
resist layer on the wafer damages or ▪ The resolution degrades due to the ▪ projection of the mask can be scaled
contaminates the mask and limits the diffraction. ▪ Avoids mask damage entirely.
number of times the mask can be used.

©ADNAN AMIN SIDDIQUEE 6

 Photoresist
Photosensitive polymer imprinted photomask pattern on the wafer.
Upon exposure to light the property of the photoresist changes.
Used for precise pattern formation.
Protects substrate from chemical attack.

Photoresist

Positive Photoresist Negative Photoresist

©ADNAN AMIN SIDDIQUEE 7

 Photolithography Process (pattern transfer)
Mask Glass

Photoresist
Film Film Film
Soft Bake
substrate substrate substrate substrate

Surface Preparation Deposition of Film Photoresist by Spin Mask Alignment

UV

Mask Glass

Remove Mask
Film Hard Bake Film
Developer Solution
substrate substrate substrate substrate

Strip Photoresist Etching Development Expose to light

©ADNAN AMIN SIDDIQUEE 8
 Effect of Photoresist

©ADNAN AMIN SIDDIQUEE 9

 Photolithography Process (pattern transfer)
Surface Preparation
▪ Ensure the wafer surface is clean and dry
▪ Prime wafer using HMDS(Hexamethyldisilazane)
Deposition of Film
▪ Using a suitable process grow the layer which will be shaped over the surface .
Photoresist Application
▪ Wafer is placed into a vacuum chuck
▪ Light-sensitive polymer is applied to the wafer while spinning(100-6000 rpm) the wafer.
▪ Coupling agents needed to be applied for adhesion.
Soft Bake
▪ Typically backed for 20-30 mins at 90-100o C temperature
▪ Drives off most of the solvent in the photoresist.
▪ Promotes photoresist uniformity and improves adhesion to wafer.
Mask Alignment
▪ Mask containing the patterns brought in close proximity to the wafer.
▪ Baked of slightly to produce airgap and adjust the alignment.

©ADNAN AMIN SIDDIQUEE 10

 Photolithography Process (pattern transfer)
Exposure
▪ The combination of mask and wafer is now exposed to light(UV).
▪ The light activates the photosensitive components of the photoresist.
▪ Where the mask is transparent, the photoresist becomes soluble. (for positive photoresist)
Hard Bake
▪ Bake at 100-120o C to make the hard resist.
▪ Improves dissolution rate, improves adhesion, and prevents undercut.
Development
▪ Soluble areas of photoresist are dissolved by developer chemical.
▪ Visible patterns appear on wafer.
Etching
▪ Material is selectively removed from areas of the wafer that are not covered by the photoresist.
▪ Different types of acid, base, and caustic solutions are used to remove and form windows in the film.
Resist Stripping
▪ High-temperature plasma is used to selectively remove the remaining photoresist without damaging
device layers
Inspection
▪ Automated process to identify quality problems. (defects)
©ADNAN AMIN SIDDIQUEE 11
 Photolithography Process (Problem Areas)
Mask Defects
▪ Visual type
i. Includes Pinhole, Spot, Intrusion, Protrusion.
ii. Voids and scratches are hard to repair.
▪ Dimensional error
i. Occurs during mask making.
ii. Determined by line width and run-out measurement.
Pattern Transfer Defects
▪ Undercutting of the resist
i. Enlarges the window during the etching process if the resist adheres poorly. [capillary action of wet etching]
ii. Changes device parameters after diffusion.
iii. Short circuits the adjacent regions.
▪ Dimensional variations
i. Changes effective area of the masked region.
ii. Leads to breaks when very narrow cuts are required for metallization.
iii. Photoresist are less susceptible to this problem

©ADNAN AMIN SIDDIQUEE 12

 Photolithography Process (Problem Areas)
▪ Lack of registration
i. Occurs due to mask alignment error.
ii. It can lead to altered device configuration.
▪ Pinholes
i. Inadvertent opening of small window.
ii. Effect depends on specific location of pinhole.
▪ Dust particles
i. Presence of opaque dust particles on the clear field of a mask prevents the exposure of the underlying photoresist.
ii. Transparent dust particles cases diffraction effects.
iii. Good clean room technique can minimize the above problem.

▪ Scratches-Tears
i. Caused by rough handling during fabrication process.
ii. Scratches increases current density and forms hot spots and cause electromigration.
▪ Step coverage
i. Failure of the thin resist during the etching process of a step in an oxide.
ii. Occurs with negative resist.

©ADNAN AMIN SIDDIQUEE 13

 Electron Beam Lithography (pattern transfer)
Electron Beam

Electron Beam Resist

substrate substrate substrate substrate

Silicon Substrate Spin on positive EBR E-Beam Exposure

Develop
Clean and Dry

metal

substrate substrate substrate substrate

Patterned metal over Silicon Lift-off Metal Deposition Development

©ADNAN AMIN SIDDIQUEE 14

 Electron Beam Lithography
▪ In this process narrow electron beam scans and writes the pattern directly on the wafer.
▪ At first thin electron beam resist is coated over the wafer using a spin coater.
▪ After that load the substrate into the EBL instrument.
▪ Electron source (Tungsten) emits a stream(beam) of electrons when high voltage bias is applied.
▪ The lens system focuses the beam of electrons in small spot size.
▪ The beam deflector controls the position of the electron beam according to the pattern given
through the CAD program and writes the pattern to the substrate
▪ Remove the substrate from the EBL instrument and submerge it in the developer solution.
▪ The developer solution will dissolve the resist material exposed to the electron beam.
▪ Then rinse with isopropyl alcohol and dry with pressurized N2 gas
▪ Deposit the metal layer on top of the substrate.
▪ Next the substrate is put in Acetone which dissolves the resist.
▪ Also the metal on the resist floats off.
▪ Only the metal directly on the silicon wafer stays.
▪ This process has higher resolutions than photolithography but is slow and expensive.
▪ Applications: Nanopatterning, Nanowires, Micro Ring Resonator, etc.

Positive Resist: Long molecular chains are broken by energized electrons into short chain (chain secession).
Negative Resist: Initial short chain molecules are joined upon exposure to form long chains (cross-linking), so become insoluble in developer.

©ADNAN AMIN SIDDIQUEE 15

 References
VLSI Fabrication Principles by Sorab K Ghandhi.
VLSI Technology by S. M. SZE.
The Science and Engineering of Microelectronic Fabrication by Stephen A. Campbell.
Silicon VLSI Technology by Plummer, Deal, and Griffin

©ADNAN AMIN SIDDIQUEE 16

 Any
QUESTIONS

©ADNAN AMIN SIDDIQUEE 17

 EEE-4131: Device Isolation Lecture-10
©ADNAN AMIN SIDDIQUEE 1
 CONTENTS

Why Device Isolation?

01

02 Junction Isolation

03 Local Oxidation of Silicon

04 Trench Isolation

2
©ADNAN AMIN SIDDIQUEE 2
 Why Device Isolation?

In the same substrate transistors located close to each other will be electrically connected via the substrate.
To prevent separate transistors from interconnecting with each other through the substrate.
To prevent undesired conducting path.
To avoid the creation of an inversion layer outside the channel.
To prevent leakage of current.
To fabricate monolithic ICs.
©ADNAN AMIN SIDDIQUEE 3
 Device Isolation Techniques
Isolation Techniques

Junction Isolation

Mesa Isolation

Oxide Isolation

Local Oxidation of Silicon

Trench Isolation

©ADNAN AMIN SIDDIQUEE 4

 Junction Isolation
The method of isolation is most compatible with the IC processing.
Basically the method involves producing regions of n- type material surrounded by p-type material.
Components are then fabricated in different n-type wells.
The p-type material surrounding the wells is given the most negative potential with respect to all parts of the wafer, thus
each well and hence component is electrically isolated from the others by back-to-back diodes.
Isolation between two adjacent transistors in CMOS circuits is necessary to isolate n channel and p channel transistors in
order to avoid the undesirable parasitic currents between the transistors.
However, the time required for such isolation technique is considerably longer due to diffusion time taken, which is longer
than any of other diffusions.
Isolation diffusion takes an area of the wafer surface which is significant portion of the chip area. From component
density consideration, this area is wasted.
Junction isolation method introduces significant parasitic capacitance which degrades circuit performance.

©ADNAN AMIN SIDDIQUEE 5

 Junction Isolation
p-substrate
p-substrate p-substrate

n n n n epilayer
p-substrate
p-substrate p-substrate

p p
n n p p p p pn p p p p p
p-substrate
p-substrate p-substrate

n+ n+ p p pn 6u p p p 5-15 u
p p 15 u
n n
p-substrate p-substrate p-substrate

Triply diffused Two-sided Process Double Diffused Epitaxial Process

©ADNAN AMIN SIDDIQUEE 6

 Oxide Isolation

oxide oxide

©ADNAN AMIN SIDDIQUEE 7

 Local Oxidation of Silicon (LOCOS)
Local Oxidation of Silicon (LOCOS) is the traditional isolation technique.
In the first step, a very thin SiO2 layer is thermally grown on the wafer (called pad or buffer oxide).
Subsequentially Silicon Nitride (Si3N4) is deposited on top of the pad oxide which acts as an oxide barrier.
Si3N4 causes the Kooi effect or white ribbon effect by forming oxynitride at the surface of silicon.
Pad oxide reduces the defects occurred due to stress.
Then the pattern transfer is performed by photolithography.
After photolithography, the pattern is etched into the nitride, and the photoresist is removed. Now the active regions are
covered and open areas where field oxide will be formed.
Next field oxide is thermally grown where there is no masking nitride.
If the thermal oxidation is done for a longer time a lateral extension of the field oxide at the nitride edges
occurs. This caused the nitride edges to lift. Because of the shape, this structure is called birds beak.
In the last step, the nitride layer is stripped off.
The advantages of LOCOS fabrication are the simple process flow and the high oxide quality because the whole LOCOS
structure is thermally grown.

©ADNAN AMIN SIDDIQUEE 8

 Local Oxidation of Silicon (LOCOS)
3. Photolithography process

2. Deposit Silicon Nitride layer 4. Pattern transfer in photoresist

1. Grow Pad Oxide

7. Thermal Oxidation
5. Pattern Etched into Nitride layer
Bird’s beak effect 6. Exposed areas to form field oxide
8. Strip Nitride Layer

©ADNAN AMIN SIDDIQUEE 9

 Trench Isolation
In trench isolation, a trench is cut in the semiconductor and then the trench is filled with non conducting material that
prevents electric current leakage between adjacent semiconductor device components.
At first, a thin layer of oxide is grown by the thermal process.
Subsequently, a thin layer of silicon nitride is deposited.
Next using photolithography and etching wherever electrical isolation is needed a trench is made in silicon.
After under etching of the pad oxide, a thermal oxide in the trench is grown, the so-called liner oxide.
But unlike with LOCOS, the thermal oxidation process is stopped after the formation of a thin oxide layer, and the rest of
the trench is filled with deposited oxide.
Next, the excessive oxide is removed with chemical mechanical polishing.
At last, the nitride mask is removed.
It completely avoids the bird's beak shape characteristic.
It increases the packaging density tremendously.

©ADNAN AMIN SIDDIQUEE 10

 Trench Isolation

©ADNAN AMIN SIDDIQUEE 11

 References
VLSI Fabrication Principles by Sorab K Ghandhi.
VLSI Technology by S. M. SZE.
The Science and Engineering of Microelectronic Fabrication by Stephen A. Campbell.
Silicon VLSI Technology by Plummer, Deal, and Griffin

©ADNAN AMIN SIDDIQUEE 12

 Any
QUESTIONS

©ADNAN AMIN SIDDIQUEE 13

 EEE-4131: Packaging Lecture-11
©ADNAN AMIN SIDDIQUEE 1
 CONTENTS

01 What is Packaging?

02 Packaging Types: Through-hole mounting, Surface Mounting

03 Process Sequence

04 Advanced Packaging Technology

05 Packaging Design Consideration

2
©ADNAN AMIN SIDDIQUEE 2
 Packaging

DIE
Wafer

©ADNAN AMIN SIDDIQUEE 3

 Packaging
Molding Compound

Bond Wires

Spot plate
Lead Frame Die Die Support

The IC package is the interface between the chip/die and the outer world.
Provides a suitable operating environment for the die/chip.
Establishes electrical interconnections. (distributes signal and power)
Provides physical support.
Protects from environment/handling.
Removes heat generated by the circuits.
Affects the overall cost performance and reliability of the packaged die.

©ADNAN AMIN SIDDIQUEE 4

 Packaging: Process Sequence
Cu
LEAD FRAME

Inked DIEs after Testing DIE Separation DIE Attachment

Wafer

Pin-1

TIE BAR

Packaged IC Electroplated Molding Wire Bonding

©ADNAN AMIN SIDDIQUEE 5
 Packaging: Process Sequence
Testing
DIE Encapsulation, Sealing, and Molding
▪ Computer-controlled tests are performed on each die on the wafer.
▪ Die is sealed from the external interface.
▪ Checks whether the basic process is within the specification or not.
▪ Molding material should have better heat
▪ Tests the functionality of each die.
dissipation capability.
▪ Defected dies are marked with a drop of ink.
▪ Plastic or Ceramic is used for molding.
DIE Separation ▪ Protects from environmental contamination and
▪ IC dies are scribed using an automated diamond-tipped scribing tool. external damage during handling.
▪ A roller applies pressure to the wafer to fracture along the scribe lines ▪ IC information is printed and pin-1 is marked
▪ Individual IC dies are separated using a diamond saw. over the mold.
▪ Damaged and inked dies are discarded. ▪ Finally TIE bar of the frame is removed to form
DIE Sorting the leads.
▪ Visual inspection is used to sort out the damaged dies.
▪ Damaged and inked dies are discarded.
DIE Attachment/Die Bonding
▪ Back of the die is mechanically attached to an appropriate mount media.(lead frame or Package PCB )
▪ The die attachment sometimes enables electrical connections to be made to the back of the die
▪ Two commonly used die attachment methods are Eutectic or hard solder and Epoxy.
DIE Interconnection
▪ Bond pads on the circuit side of the chip are electrically interconnected to the package PCB or lead frame.
▪ Common interconnection schemes: wire bonding, flip chip solder bonding, tape automated bonding.

©ADNAN AMIN SIDDIQUEE 6

 Package Types: Through Hole Mounting
Pins are extended in the vertical direction so that they can be inserted through holes in the circuit board.

SIP (Single Inline Package) ZIP (Zig-zag Inline Package):

SIP is a package where the pins ZIP is a package where the pins are
are arranged in a single row. arranged in a zig-zag form.

PGA (Pin Grid Array): PGA is a

DIP (Dual Inline Package): package with the square or
DIP is a package where the pins are rectangular shape, in which the pins
arranged in two rows. are arranged in a regular array on
the underside of the package.

©ADNAN AMIN SIDDIQUEE 7

 Package Types: Surface Mounting
Pins are extended in the horizontal direction so that they can be mounted on the surface in the circuit board

Gull Wing Surface Mount J-lead Surface Mount

©ADNAN AMIN SIDDIQUEE 8

 Package Types: Surface Mounting

Small Outline Transistor (SOT) Small Outline Integrated Circuit (SOIC) Thin Small Outline Package(TSOP)

Quad Flat Pack(QFP) Small Outline J-leaded(SOJ) Quad J-leaded Pack(QJP)

©ADNAN AMIN SIDDIQUEE 9

 Packaging: Gold Wire Bonding

SEM image of wire bonds connecting package leads to die bonding pads

©ADNAN AMIN SIDDIQUEE 10

 Advanced Packaging Technology

Flip Chip
▪ Mounts the active side of a chip toward the substrate.
▪ It uses bump technology (solder bumps) to form the BGA (Ball Grid Array)
interconnection between the chip and substrate. Uses a ceramic or plastic substrate with an area array
▪ An epoxy underfill is used around the area-array of of solder balls to connect the substrate to the circuit
bumps to improve reliability. board.

©ADNAN AMIN SIDDIQUEE 11

 Advanced Packaging Technology
MCM (Multi-Chip Modules)
several die assembled onto one
substrate. This permits a higher
density of chips.

COB (Chip on Board)

Mounts IC chips directly to the substrate,
alongside other components.

LGA (Land Grid Array)

It is a packaging technology with a
CSP (Chip Scale Packaging)
square grid of contacts on the
Same size as the silicon chip
underside of a package. The
Provides for a lower cost.
contacts are to be connected to a
Lower weight and lower
grid of pin contacts on the PCB.
thickness.

©ADNAN AMIN SIDDIQUEE 12

 Packaging Design Consideration
VLSI Design Rules
▪ Good design rules for achieving high yields in the VLSI package.
▪ Each package should have a particular type of design.
▪ Bonding pad size and spacing should be reduced to accommodate a higher number of I/O counts.

Thermal Design Considerations

▪ The operating junction temperature of a silicon die should be kept low enough to prevent the failure rate.

Electrical Considerations
▪ Low ground resistance.
▪ Short signal leads.
▪ Noise reduction.
▪ Impedance matching.

Mechanical Considerations
▪ TCE(thermal coefficient expansion) of the die and packaging material should be same.
▪ During packaging the die attachment materials like solder, alloy or adhesive should not melt.

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 References
VLSI Fabrication Principles by Sorab K Ghandhi.
VLSI Technology by S. M. SZE.
Introduction to Microelectronic Fabrication by Richard C. Jaeger
www2.austin.cc.tx.us/HongXiao/Book.html
https://news.skhynix.com/light-thin-short-and-small-the-development-of-semiconductor-packages/
https://www.eng.biu.ac.il/temanad/digital-vlsi-design/
Video Links:
https://www.youtube.com/watch?v=J1rBzmV1phY

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 Any
QUESTIONS

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