MIT-WPU

School of Mechanical Engineering (R&A)

S.Y. B. Tech (Semester IV)
Microcontroller and Applications
ECE2PM07A
 Unit-II

CIP-51 Architecture
CIP-51 Architecture
• Reset sources
• Oscillator options
• Port structure
• Timers
• Timer programming
• Interrupt handler
• Power management modes
Microcontroller Components
Typical Structure diagram of C8051F34X Family
On-Chip Memory Map for 64 KB C8051F34x MCUs
 C8051F34X MEMORY
There are two separate memory spaces: program memory (ROM or FLASH) and data memory (RAM).

Program Memory
The C8051F340 CPU has a 64 KB FLASH memory in system programming. The C8051F340
implements 64k of this program memory space as in-system, re-programmable Flash memory. Note
that on the 64k versions of the C8051F340/2/4/6, addresses above 0xFBFF are reserved.

Data Memory
The C8051F34X CPU includes 256 of internal RAM mapped into the data memory space from 0x00 through
0xFF. The lower 128 bytes of data memory are used for general purpose registers (SFR) and temporary storage.
Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide
registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations
accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same
address space as the SFR, but is physically separate from the SFR space. The addressing mode used by an
instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of
data memory space or the SFRs. Instructions that use direct addressing will access the SFR space.
Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory.
C8051F34X MEMORY
Special Function Registers (SFR)
The direct addressing memory spaces from 80H to FFH constitute SFRs; The SFRs
provide control of the resources and peripherals of the C8051F34X family of single-
chip microcomputer.
In addition to the 21 SFR in standard 8051, the C8051F34X family adds some SFR
to configure and access proprietary subsystems.
Use of Flash for programming
• All modern microcontrollers have volatile (SRAM) memory and non-volatile, reprogrammable flash
memory. The flash memory contains the code, so no external integrated circuits are needed.
• The flash memory can be reprogrammed by special programming devices using a few (from 2 to 6-
8) pins of the microcontroller (in-circuit programming, JTAG) or can even be overwritten by the
microcontroller itself in some cases.
• Additional separate flash or EEPROM may also be integrated to support non-volatile data storage
(configuration data, calibration data, statistical data, etc.).
• The flash memory can be rewritten about 100000 times, and the typical data retention time is
longer than 20 years. The flash memory can be protected, i.e., the code can be prevented from being
read by the user.
 Processor Support Peripherals
• Power on reset (POR) generator. After switching the power on, the supply voltage may rise a bit
slowly due to the fact that the supply decoupling and filtering capacitors must be charged and the
supply current is limited. At the same time, the digital circuitry needs a certain minimum supply
voltage for proper operation, so the start-up of the microcontroller must be delayed until the supply
voltage reaches the safe operating level. Having detected the crossing of this level, the POR
generates an additional short delay
• Power supply monitor (Brown-out detector). In some cases, the supply voltage may go below the
safe operating level even during operation (for example, when sudden heavy current loading
occurs). This may result in erroneous code execution, therefore the supply monitor circuit will
generate a reset in this case.
• Watchdog timer (WDT). Even properly powered processors can fall into infinite loops or get
disturbed by electromagnetic or conducted interference (for example, in the case of lightning or
power line transients), which may cause serious problems in several applications (motor control,
heating control, healthcare devices, etc.).
• The watchdog timer refresh register needs to be written within a certain amount of time (that can be
typically programmed from tens of milliseconds to several seconds); otherwise, a reset will be
generated.
• Oscillator, PLL. All processors need a clock signal to schedule instruction execution. Modern
microcontrollers have on-chip oscillators but also support the use of external quartz crystals or
external clock signals. Optional phase-locked loop (PLL) clock multipliers often combined with clock
dividers allow the generation of a wide range of higher processor clock frequencies.
C8051C340 Reset Sources
Reset sources
Reset circuitry allows the controller to be easily placed in a
predefined default condition. On entry to this reset state, the
following occur:
❖ CIP-51 halts program execution
❖ Special Function Registers (SFRs) are initialized to their defined
reset values
❖External Port pins are forced to a known state(Ports=0xFF)
❖ Interrupts and timers are disabled
❖Contents of internal data memory are unaffected
 Reset sources
• Power-On Reset (POR)
• Power-Fail Reset / VDD Monitor
• External Reset
• Missing Clock Detector Reset
• Comparator0 Reset
• PCA Watchdog Timer Reset
• Flash Error Reset
• Software Reset
• USB Reset

Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by
the user in software.
The WDT may be permanently enabled in software after a power-on reset during MCU
initialization.
Reset sources
SFR: RSTSRC- Reset Source Register

Appropriate Flag can be read to detect

source of reset
Clock Sources and Oscillator Section of C8051F340
System Oscillator
•The C8051F340 typically has an internal oscillator circuit known as the system oscillator. This oscillator generates the
primary clock signal for the microcontroller.
•The system oscillator can operate in different modes, such as low-power modes and high-frequency modes, depending
on the specific requirements of the application.
Clock Sources:
•The oscillator subsystem may offer multiple clock sources. The C8051F340 can use an internal oscillator, an external
crystal oscillator, or an external clock source as the primary clock reference.

•The choice of the clock source is often configured through the device configuration registers.

Frequency Control:
•The oscillator subsystem allows you to control the frequency of the clock signal. This can be crucial for power
management and adjusting the performance of the microcontroller to meet the application's requirements.
•Frequency control may involve setting the oscillator to run at a specific frequency or configuring it to change
dynamically based on the system's needs.
Crystal Oscillator:
The C8051F340 supports an external crystal oscillator for more accurate and stable clock generation. This is commonly
used when precise timing is required in applications.
The crystal oscillator is connected to the microcontroller's crystal pins, and its frequency is typically specified by the
crystal used.
Low-Frequency Oscillator (LFO):
Some microcontrollers, including the C8051F340, may include a low-frequency oscillator for low-power modes. This
oscillator provides a clock source during low-power states to keep certain functions active while the main oscillator is
turned off.
PLL (Phase-Locked Loop):
The C8051F340 may include a PLL for frequency multiplication. The PLL can be used to generate higher-frequency clock
signals from a lower-frequency reference, providing flexibility in achieving desired operating frequencies.
Clock Divider:
The oscillator subsystem may also include a clock divider that allows you to further divide the clock frequency to achieve
specific timing requirements or to reduce power consumption.
Oscillator Fail-Safe: Some microcontrollers, including the C8051F340, may incorporate features such as oscillator fail-safe
mechanisms. These features ensure that the microcontroller can detect and respond to issues with the oscillator to
prevent system malfunctions.
Oscillator options
Four Oscillator options

• Programmable internal high-frequency oscillator

• Programmable internal low-frequency oscillator

• External oscillator drive circuit

• 4x Clock Multiplier.
Oscillator Diagram
Task of oscillator subsystem is to
generate stable clock signal

There are two main clocks in the

system

• System Clock

• USB Clock
 Oscillator Registers
Register Name Short form Function
Programmable Internal High OSCICN Default value after reset 12MHz/8 bit.,
Frequency Oscillator control
Register (Internal H-F The internal oscillator period can be programmed
Oscillator Control) via the OSCICL register
Internal High Frequency OSCICL Decides Oscillator Period. Setting OSCCAL bits to
Oscillator Calibration 00000b oscillator operates at its fastest setting.
When set to 11111b the oscillator operates at
slowest setting. The contents of this register are
factory calibrated to produce 12MHz internal
oscillator frequency.
Programmable Internal Low OSCLCN Operates at nominal frequency of 80 KHz can be
Frequency (L-F) Oscillator Control divided by 1,2,4,8
Register
System Clock Selection Register CLKSEL First three bits select system clock source
SFR: CLKSEL - Clock Select(Bit 7-Bit 4)

SFR Definition 14.6. CLKSEL: Clock Select

SFR: CLKSEL - Clock Select
Oscillator options
• The internal high-frequency and low-frequency oscillators can be
enabled/disabled and adjusted using the special function registers OSCICN &
OSCLCN

• The high-speed internal oscillator is factory calibrated to 12 MHz ±1.5%.

• The system clock (SYSCLK) can be derived from either of the internal
oscillators, the external oscillator circuit, or the 4x Clock Multiplier divided
by 2.

• The USB clock (USBCLK) can be derived from the internal oscillator,
external oscillator, or 4x Clock Multiplier.
SFR: OSCICN - Internal H-F Oscillator Control
SFR: OSCLCN- Internal L-F Oscillator Control
Oscillator Programming Setting high frequency clock to 12MHz

• OSCICN - Internal H-F Oscillator Control

• OSCICN=0x83

IOSCEN 0 0 0 0 0 IFCN 1 IFCN 0

1 1 1
C8051C340 Port Structure
 Port structure of C8051F340
Ports are represented by registers inside the microcontroller, and
allow the program (firmware) to control the state of the pins, or
conversely, read the state of the pins if they are configured as
inputs. There is a one-to-one correspondence between the pins on
the microcontroller and the bits in its registers.
• Five ports - P0 to P4 (8 bit each) – 40 Pins GPIO

• Each of the Port pins can be defined as

• Digital I/O- general-purpose I/O (GPIO)

• Analog input
• Port pins P0.0-P3.7 can be assigned to one of the internal digital resources
Block Diagram of C8051F340 – with highlighted ports
Priority Cross bar decoder assigns Digital Peripherals and Latches to port pins
The Priority Crossbar Decoder
• After reset, the ports are not connected to the core and all peripherals are idle.
Port pins can be associated with the port latches or with the enabled peripherals,
which can output or input signals.
• The priority crossbar provides a flexible way to connect the internal peripherals
and port latches to the port pins.
• If it is enabled, the port pins are accessible. If a peripheral is used, its signals are
associated with port pins. Peripherals are numbered and the port pins are
associated in this order with the enabled peripherals.
For example, if peripheral #1 is enabled with two signals and
peripheral #5 is enabled with three signals, peripheral #1 will be
connected to the first two pins (P0.0 and P0.1), while peripheral #5 will
be associated with the next three pins (P0.2, P0.3 and P0.4).
The state of these pins cannot be modified by writing to the port latches but their
state can be monitored by reading the corresponding port bit.
The push-pull or open-drain settings can still be set by firmware.
Sr. PORT 0 PORT 1 PORT 2 PORT 3 PORT 4
No GPIO Registers
1 P0 P1 P2 P3 P4
Port0 latch Register Port1 latch Register Port2 latch Register Port 3 latch Port 4 latch Register
Register

2 P0MDIN P1MDIN P2MDIN P3MDIN P4MDIN

Port 0 input mode Port 1 input mode Port 2 input mode Port 3 input mode Port 4
register register register register input mode register

3 P0MDOUT P1MDOUT P2MDOUT P3MDOUT P4MDOUT

Port 0 output mode Port 1 output mode Port 2 output mode Port 3 output mode Port 4 output mode
register register register register register

4 P0SKIP P1SKIP P2SKIP P3SKIP - Port 4 is not

Port 0 Skip Register Port 1 Skip Register Port 2 Skip Register Port 3 Skip Register connected through
- Crossbar so skip
register not
required

5 XBR0 XBR1 XBR2

Port I/O Crossbar Port I/O Crossbar Port I/O Crossbar
register 0 register 1 register 2
 Purpose of the priority crossbar Decoder

• The crossbar is a multiplexer that routes digital peripherals to

port pins. It must be properly enabled and configured when using
peripherals.
• Using Crossbar, internal digital signals are mapped to port pins.
• Basically, it gives the designer the flexibility to route desired
peripheral to port pin.

Ex. If we want a UART devices that needs to connect to pins

P0.4 and P0.5. The crossbar allows you to bring that signal out to
that pin or a different supported pin in another design.
 Purpose of the priority crossbar Decoder
• Problem: Many peripherals/functions are available inside the MCU
• There are limited number of pins available to connect the peripherals to the outside world

• Solution: Pick and choose the peripherals that are necessary for an application, and assign only
those to external pins
• This is the function of the crossbar
• Based on the application, the system designer makes the decision as to which peripherals are
enabled, and which pins are used

• The C8051F340 has a rich set of digital resources like UARTs, system management bus (SMBus),
timer control inputs and interrupts
• These peripherals do not have dedicated pins through which they may be accessed
• They are available through the four lower I/O ports (P0, P1, P2 and P3)
• Each of the pins on P0, P1, P2 and P3 can be defined as a general purpose input/output
(GPIO) pin or can be assigned to a digital peripheral
• Lower ports have dual functionalities
• This flexibility makes the MCU very versatile
 Crossbar Pin Assignment and Allocation of Priority
• The crossbar has a priority order in which peripherals are assigned to pins
• UART0 has the highest priority and UART1 has the lowest priority
• There are three configuration registers, XBR0, XBR1 and XBR2, which are
programmed to accomplish the pin allocations
• If the corresponding enable bits of the peripheral are set to a logic 1 in the crossbar registers,
then the port pins are assigned to that peripheral
• Pin assignments to associated functions are done in groups
• For example, TX0 and RX0 for UART0 are assigned together

• Example: If the UART0EN bit (XBR0.0) is set to logic 1, the TX0 and RX0 pins will be
mapped to the port pins P0.4 and P0.5, respectively.
• Since UART0 has the highest priority, its pins will always be mapped to P0.4 and
P0.5 when UART0EN is set to logic 1 and will have precedence over any other
peripheral allocation
• Registers XBR0 and XBR1
must be loaded with the
appropriate values to
select the digital I/O
functions required by the
design.

• Setting the XBARE bit in

XBR1 to ‘1’ enables the
Crossbar.

• Until the Crossbar is

enabled, the external pins
remain as standard Port
I/O (in input mode),
regardless of the XBRn
Register settings.
XBR0, XBR1, XBR2
XBR0 (Crossbar Register 0)
XBR1 (Crossbar Register 1)
XBR2 (Crossbar Register 2)
Select port pins that are to be skipped by cross
bar decoder
 Port I/O Initialization

• All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its
weak pull-up, digital driver, and digital receiver are disabled.

• To configure a Port pin for digital input, write ‘0’ to the corresponding bit in register PnMDOUT, and write
‘1’ to the corresponding Port latch (register Pn).

• Until the Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of
the XBRn Register settings.
 Port I/O Initialization
Port I/O initialization consists of the following steps:
Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register
(PnMDIN).
Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode
register (PnMDOUT).
Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
Step 4. Assign Port pins to desired peripherals (XBR0, XBR1).
Step 5. Enable the Crossbar (XBARE = ‘1’).
General Purpose Port I/O
• Port pins that remain unassigned by the Crossbar and are not used by
analog peripherals can be used for general purpose I/O. Ports 3-0 are
accessed through corresponding special function registers (SFRs) that are
both byte addressable and bit addressable.

• Port 4 uses an SFR which is byte-addressable. When writing to a Port, the

value written to the SFR is latched to maintain the output data value at each
pin. When reading, the logic levels of the Port's input pins are returned
regardless of the XBRn settings (i.e., even when the pin is assigned to
another signal by the Crossbar, the Port register can always read its
corresponding Port I/O pin).
SFR P0 (Port 0 Latch) List of GPIO Registers
1. P0: Port0 latch Register
2. P0MDIN: Port 0 input mode
register
3. P0MDOUT: Port 0 output mode
register
4. P0Skip: Port0 skip register
5. P1: Port1 latch Register
6. P1MDIN: Port 0 input mode
register
7. P1MDOUT: Port 0 output mode
register
8. P1Skip: Port0 skip register
If Port I/O Cells are in PUSH-PULL Mode

Push pull mode connection diagarm Phases of Push Pull Mode

• Push phase – When the Internal Signal connected to the
gates of the transistors (see the figure above) is set to a
low logic level (logic 0), the PMOS transistor is activated
and current flows through it from the VDD to the output
pin. NMOS transistor is inactive (open) and not
conducting.
• Pull phase – When the Internal Signal connected to the
gates of the transistors is set to a high logic level (logic
1), the NMOS transistor is activated (closed) and current
starts to flow through it from the output pin to the GND.
At the same time, the PMOS transistor is inactive (open)
and is not conducting current.
• This type of output doesn’t allow connecting multiple
devices together in a bus configuration, like the open
drain output. Push-pull configuration is most commonly
used in interfaces that have unidirectional lines
(transmission on the line is only in a single direction –
SPI, UART etc.).
 Open Drain
• In open drain configuration, the logic behind the pin can drive it
only to ground (logic 0). The other possible state is high
impedance (Hi-Z). The implementation involves the use of a
single transistor. If its drain terminal is open (the device is off)
the pin is left floating to Hi-Z state. Driving it to high logic level
requires the use of an additional circuit or component. In most
cases, an external pull-up resistor is used (there are
microcontrollers that provide internal pull-up resistors for open
drain configurations).
If Port I/O Cells are in Open Drain Mode
• Open drain outputs are most commonly used in communication interfaces where
multiple devices are connected on the same line (e.g I2C, One-Wire etc.).

• When all of the outputs of the devices connected to the line are in Hi-Z state,
the line is driven to a default logic 1 level by a pull-up.

• Any device can pull the line to logic 0 using its open drain output and all devices
can see this level.
Port structure
• Designer has complete control over which functions are assigned, limited only by
the number of physical I/O pins.
• The Digital Crossbar allows mapping of internal digital system resources to Port
I/O pins. On-chip counter/timers, serial buses, HW interrupts, comparator
outputs, and other digital signals in the controller can be configured to appear on
the Port I/O pins specified in the Crossbar Control registers. This allows the user
to select the exact mix of general purpose Port I/O and digital resources needed for
the end application.
• This resource assignment flexibility is achieved through the use of a Priority
Crossbar Decoder.
• State of a Port I/O pin can always be read in the corresponding Port latch,
regardless of the Crossbar settings.
• The Crossbar assigns the selected internal digital resources to the I/O pins based
on the Priority Decoder
• The registers XBR0, XBR1, and XBR2 defined in SFR definition
• These SFRs used to select internal digital functions
Port I/O -Functional block diagram
Priority Crossbar Decoder
• The Priority Crossbar Decoder assigns a priority to each I/O function, starting at
the top with UART0. When a digital resource is selected, the least-significant
unassigned Port pin is assigned to that resource (excluding UART0, which is
always at pins 4 and 5).
• If a Port pin is assigned, the Crossbar skips that pin when assigning the next
selected resource. Additionally, the Crossbar will skip Port pins whose associated
bits in the PnSKIP registers are set.
• The PnSKIP registers allow software to skip Port pins that are to be used for
analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral
without use of the Crossbar, its corresponding PnSKIP bit should be set.
The Crossbar must be enabled to use Ports P0, P1, P2, and P3 as standard Port I/O
in output mode. These Port output drivers are disabled while the Crossbar is
disabled.
Port 4 always functions as standard GPIO.
 Port I/O Initialization
• Port I/O initialization consists of the following steps:

Step 1. Select the input mode (analog or digital) for all Port pins,
using the Port Input Mode register (PnMDIN).
Step 2. Select the output mode (open-drain or push-pull) for all Port
pins, using the Port Output Mode register (PnMDOUT).
Step 3. Select any pins to be skipped by the I/O Crossbar using the
Port Skip registers (PnSKIP).
Step 4. Assign Port pins to desired peripherals (XBR0, XBR1).
Step 5. Enable the Crossbar (XBARE = ‘1’).
Important points to configure the crossbar

• All pins have been properly set in the PxMDOUT registers to be

configured to digital input or output
• Pins set to be ADC inputs are skipped by the crossbar using
the PxSKIP register and configured to be analog inputs in
the PxMDIN register. Also, a '1' should be written into the pin's
corresponding bit in the Px register
• If using SPI, on certain devices there is a 3-wire mode
option. Check that the peripheral is set to 3- or 4- wire mode
before configuring the crossbar, since 3-wire mode will yield a
different pin assignment than 4-wire mode for peripherals of lower
priority than SPI
Port pins must be configured as either analog or digital inputs

• Analog Input-
Any pins to be used as Comparator or ADC inputs should be configured as an analog
inputs. When a pin is configured as an analog input, its weak pull-up, digital driver,
and digital receiver are disabled. This process saves power and reduces noise on the
analog input.
Additionally, all analog input pins should be configured to be skipped by the Crossbar
(accomplished by setting the associated bits in PnSKIP).

• Digital input-
Port input mode is set in the PnMDIN register, where a ‘1’ indicates a digital input,
and a ‘0’ indicates an analog input.
All pins default to digital inputs on reset.
General Purpose Port I/O
• Port pins that remain unassigned by the Crossbar and are not used by
analog peripherals can be used for general purpose I/O.
• Ports 3-0 are accessed through corresponding special function registers
(SFRs) that are both byte addressable and bit addressable.
• Port 4 uses an SFR which is byte-addressable.
• When writing to a Port, the value written to the SFR is latched to
maintain the output data value at each pin.
• When reading, the logic levels of the Port's input pins are returned
regardless of the XBRn settings
Port0 Latch
Port0 Input Mode
Port0 Output Mode
Port0 Skip
 Port SFRs
• Port 0 to Port 3
Portx Latch
Portx Input Mode
Portx Output Mode
Portx Skip

• Port 4 (Not assigned to crossbar)

Port4 Latch
Port4 Input Mode
Port4 Output Mode
GPIO Programs
Expt2 Warm up Expt.: Interfacing of LED to C8051F340
Expt 2 Warm up Exp.: Interfacing of LED to C8051F340

• P4 - Output port -- P4MDOUT = 0xFF

LED’s ON - Logic 0 ------ Common Anode
OFF - Logic 1
Write an embedded C program to flash the LEDs connected to Port P4 continuously
#include "c8051F340.h"
void DelayMs(unsigned int Ms);
#define LED P4 void DelayMs(unsigned int Ms)
void main()
{ {
P4MDOUT = 0xFF; /* All P4 pins configured as Output*/ unsigned int n;
unsigned int i;
while(1) for (n=0; n < Ms; n++)
{ {
LED=0X00; /* LEDs ON*/
for (i=0; i < 65; i++);
DelayMs(100);
}
LED=0xFF; /* LEDs OFF*/
}
DelayMs (100);
}

}
Interfacing of LED, Relay, Buzzer, Switch
Interfacing Diagram
Hardware board connections for LED , Relay, Buzzer

EPB 340 ASK 25

1 &2 PL3
PL3 Switch & relay
PC
IDE C8051F340
Simplicity Studio
.hex PL8 LED& Buzzer
3 &4 PL6
With LED, Relay
Buzzer & Switches
Interfacing of LED, Buzzer, Relay and Switch with C8051F340

• LED: LED is an output device. 8 LED’s are connected to 8 port pins.

The LED’s are connected in common anode configuration. Thus, to
turn ON the LED logic ‘0’ must be given and to turn OFF the LED
logic ‘1’ must be given.
• Buzzer: Buzzer is an output device. The buzzer is turned ON when
logic ‘1’ is applied to the port pin and turned OFF when logic ‘0’ is
applied to port pin.
• Relay: Relay is an output device. The relay is turned ON when logic
‘0’ is applied to port pin and turned OFF when logic ‘1’ is applied to
the port pin.
• Switch/button: Switch is an input device. Push button switches are
used. When the switch is released the port pin has logic ‘1’ and when
the switch is pushed the port pin has logic ‘0’.
sbit
The sbit type defines a bit within a special function register (SFR). It is used in one of the following ways:
sbit name = sfr-name ^ bit-position; sbit name = sfr-address ^ bit-position; sbit name = sbit-address;
• P1.0 &P1.1 --- Digital Input Pins- P1MDIN = 0xFF or 0X03
Key1 & Key2 – Logic 0- Key Pressed
Logic 1 –Key Released

• P1.4---- Output Pin- P1MDOUT = 0x10

Relay ---- ON - Logic 0 ----- Internally PNP
Transistor as driver
OFF- Logic 1

• P3.3---- Output Pin- P3MDOUT = 0x08;

Buzzer ON - Logic 1
OFF - Logic 0

• P4 - Output port -- P4MDOUT = 0xFF

LED’s ON - Logic 0 ------ Common Anode
OFF - Logic 1
Program
#include "c8051F340.h"
#define LED P4
sbit KEY1 = P1^0;
sbit KEY2 = P1^1;
sbit RELAY = P1^4;
sbit BUZZER = P3^3;
void main()
{
XBR1 = 0x40; /* Enable Crossbar*/
P1MDIN = 0x03; /* P1.0 &P1.1 pins configured as Digital Inputs*/
P1MDOUT = 0x10; /* P1.4 pins configured as Output*/

P4MDOUT = 0xFF; /* All P4 pins configured as Output */

P3MDOUT = 0x08; /* P3.3 pins configured as Output*/

Program….
while(1)
{
if(KEY1 == 0) /* Key1 pressed*/
{
while(1)
{
LED = 0x00; /* LED, Relay, Buzzer ON */
RELAY = 0;
BUZZER = 1;

if(KEY2 == 0)
{
break;
}
Program….
while(1)
{
if(KEY2 == 0) /* Key2 pressed*/
{
while(1)
{
LED = 0xFF;
RELAY = 1; /* LED, Relay, Buzzer OFF */
BUZZER = 0;

if(KEY1 == 1)
{
break;
}
}
}
 LCD Interfacing

• Liquid Crystal Displays (LCDs)

• Cheap and easy way to display text
• Integrated controller
• The display has two register
• Command register
• Data register
• By Register Select(RS) you can select register for commands or
data
• Data lines (DB7-DB0) used to transfer data and commands
 "Understanding 16x2 Character LCD"
Each character is formed by
5×7 dots

First row first character

has address 80

Second row first character

has address C0
 Basic structure OF LCD
RS (Register Select)
A 16X2 LCD has two registers, namely, command and data. The register
select is used to switch from one register to other. RS=0 for the
command register, whereas RS=1 for the data register.
Command Register: The command register stores the command
instructions given to the LCD. A command is an instruction given to an
LCD to do a predefined tasks like:
• initializing it
• clearing its screen
• setting the cursor position
• controlling display etc.
• Processing for commands happens in the command register.
Data Register: The data register stores the data to be displayed on the
LCD. The data is the ASCII value of the character to be displayed on the
LCD. When we send data to LCD, it goes to the data register and is
processed there. When RS=1, the data register is selected.
Pin Description Pin No: Name Function
1 VSS This pin must be connected to the ground
2 VCC Positive supply voltage pin (5V DC)
3 VEE Contrast adjustment
4 RS Register selection
5 R/W Read or write
6 E Enable
7 DB0 Data
8 DB1 Data
9 DB2 Data
10 DB3 Data
11 DB4 Data
12 DB5 Data
13 DB6 Data
14 DB7 Data
15 LED+ Back light LED+
16 LED- Back light LED-
 Alphanumeric LCD Interfacing
• Pinout
• 8 data pins D7:D0
• RS: Data or Command Register Select
• R/W: Read or Write
• E: Enable (Latch data)
• RS – Register Select
• RS = 0 → Command Register
• RS = 1 → Data Register

• R/W = 0 → Write , R/W = 1 → Read

• E – Enable
• Used to latch the data present on the data pins. A High to low pulse is required on Enable line

• D0 – D7
• Bi-directional data/command pins.
• Alphanumeric characters are sent in ASCII format.

• After writing to the LCD, it takes some time for it to complete its internal operations. During this time, it will
not accept any new commands or data.
• We need to insert time delay between any two commands or data sent to LCD
Command Codes
Interfacing Diagram

E communications
Microcontroller bus
R/W
RS

DB7–DB0

8
LCD
controller

LCD Module
Interfacing Diagram
Program for LCD (8-bit mode)

#include "c8051F340.h" Write_Command_Lcd(0x01); /* Call Command routine*/

void DelayMs(unsigned int Ms); DelayMs(50); /* Delay routine*/
void Write_Command_Lcd(unsigned char Command); Write_Command_Lcd(0x38); /* 2 lines 5×7 Matrix
void Write_Data_Lcd(unsigned char Character); DelayMs(50);
Write_Command_Lcd(0X0C); /* Display ON cursor off*/
sbit LCD_RS = P1^5; DelayMs(50);
sbit LCD_RW = P1^6; Write_Command_Lcd(0X80); /* Set cursor to 1st line*/
sbit LCD_EN = P1^7; DelayMs(50);
Write_Data_Lcd('W’); /* Call Data routine*/
void main() DelayMs(50); /* Delay routine*/
{ Write_Data_Lcd('P’);
XBR1 = 0x40; /* Enable Crossbar*/ DelayMs(50);
P2MDOUT = 0xFF; /* P2 output port*/ Write_Data_Lcd('U');
P1MDOUT = 0xE0; /* P1.5,P1.6&P1.7 output DelayMs(50);
pins*/
while (1);
}
 LCD Functions

void Write_Command (unsigned char command) void Delay(unsigned int Ms)

{ {
LCD_RS = 0; unsigned int i,n;
LCD_RW = 0; for(n=0;n<Ms;n++)
P2 = command; {
LCD_EN = 1; for(i=0;i<65;i++);
Delay(15); }
LCD_EN=0; }
}

void Write_Data_Lcd(unsigned char character)

{
LCD_RS = 1;
LCD_RW = 0;
P2 = character;
LCD_EN = 1;
Delay(15);
LCD_EN=0;
}
 Unit-III

Interfacing of DAC to C8051F340

Digital to Analog Converter (8 bit)
DAC 0808 Pin Diagram
DAC 0808 Internal Structure
 Digital to Analog Conversion (DAC)
• Converts digital pulses to analog signals
• Resolution of a DAC is a function of number of binary
inputs
• In DAC0808, binary numbers at D7-D0(A1-A8) inputs are
converted to reference current Iref
 Converting lout to voltage in DAC0808
• Ideally we connect the output pin Iout to a resistor,
convert this current to voltage
• This can cause inaccuracy since the input resistance of the
load where it is connected will also affect the output
voltage.
• Iref current output is isolated by connecting it to an op-
amp such as the 741 with Rf = 5K ohms for the feedback
resistor.
DAC Voltage Output
DAC Interfacing with C8051F340

DSO
DAC Calculations
Converting Digital Input to Analog Output
• Equation for converting Digital Input into its equivalent Analog output
is,

• Where, A1 is the MSB and A8 is the LSB

Considering Vref = 5V, calculate the Analog output
obtained from the following Digital input:
Digital input Analog Output
11001100
11101101
1000101
11111
10110110
11111111 5
(10)d=(1010)b 0.196=0.2
 DAC PROGRAMING

• Square
• Triangular
• Sawtooth
• Trapezoidal Wave
• Sine
Square Wave
FFH

00H
void DelayMs(unsigned int Ms)
#include "c8051F340.h"
void DelayMs(unsigned int Ms); {
void main() unsigned int n;
{ unsigned int i;
P4MDOUT = 0xFF; /* All P4 pins configured as
Output*/ for (n=0; n < Ms; n++)
while(1) {
{
for (i=0; i < 165; i++);
P4 = ~P4;
DelayMs(10); }
} }
}
Triangular Wave #include "c8051F340.h"
int main()
{
P4MDOUT = 0xFF; // All data lines Output
int i;
255 255
while (1)
{
for (i = 0; i =< FE; i++)
0 0 0 {
P4 = i;
}
for (i = FF; i > 0; i--)
{
P4 = i;
}
}
}
 #include "c8051F340.h"
Sawtooth Wave int main()
{
P4MDOUT = 0xFF; // All data lines Output
int i;
255 255 while (1)
{
for (i = 0; i =< FE; i++)
0 0 0 {
P4 = i;
}
}
}
Trapezoidal Wave

255
Complete program of it as
Homework
0
 Generating a Sine Wave

180o
0o 90o 360o
 Generating a Sine Wave
• We first need a table whose values represent the magnitude of the sine of
angles between 0 and 360 degrees
• The table values are integer numbers representing the voltage magnitude
for the sine of theta
• This method ensures that only integer numbers are output to the DAC by
the 8051 microcontroller
• Full-scale output of the DAC is achieved when all the data inputs of the
DAC are high. Therefore, to achieve the full-scale 10 V output, we use
the following equation:

• To find the value sent to the DAC for various angles, we simply multiply the
Vout voltage by 25.60 because there are 256 steps and full-scale Vout is 10
volts. Therefore, 256 steps /10 V = 25.6 steps per volt.
 Angle vs. Voltage Magnitude for Sine Wave
i Angle (ѳ) Sine ѳ Voltage out Vo = 5+(5*Sine ѳ) DAC count =
Vo * 25.6
0 0 0 5 128
1 30 0.5 7.5 192
2 60 0.866 9.33 238
3 90 1.0 10 255
4 120 0.866 9.33 238
5 150 0.5 7.5 192
6 180 0 5 128
7 210 -0.5 2.5 64
8 240 -0.866 0.669 17
9 270 -1.0 0 0
10 300 -0.866 0.669 17
11 330 -0.5 2.5 64
12 360 0 5 128
Waveform
Sine w
Sine wave generation using DACC8051F340
#include "c8051F340.h"
unsigned char x[12] = {128,192,238,255,238,192,128,64,17,0,17,64};
int i;
int main(void)
{
P4MDOUT = 0xFF;
while(1)
{
for(i=0;i<12;i++)
{
P4=x[i]; Note: You should use more samples i.e. higher
} value of i so that you will get smoother wave.
}
}
C8051F340 TIMERS
 Difference between Timer and Counter
Counter: Uses External Clock Timer: Uses Internal Oscillator Clock

T0 T1
T0 T1

T2 T3
T2 T3 Fosc
 Timers
• Timers are used for: interval timing, event counting or baud rate generation
• In interval timing applications, a timer is programmed to overflow at a regular
interval and the following:
• Set the timer overflow flag or
• Generate an interrupt
• This can also be used to generate waveforms at set frequencies
• Event counting is used to determine the number of occurrences of an event, rather
than to measure the elapsed time between events. In this case, the timer functions
as a counter.
• An “event” is any external stimulus that provides a high-to-low transition at
the selected input pin
• The timers can also function as the baud rate generators for the C8051F340’s
internal serial ports (UART0 and UART1)
• “Baud rate” is the bit rate of the serial port
(the time period of a bit)
Timers
• C8051F340 has four counter/timers: Timer 0, Timer 1,
Timer 2 and Timer 3
• Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation.
• Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality
with auto-reload.
 TO and T1 Mode 0
• Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0.

• Both timers operate identically.

• The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4-TL0.0.

• The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be ignored.

• As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow
flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled.
• Timer 0 and Timer 1 Modes: Timer 2 Modes: Timer 3 Modes: 13-bit counter/timer 16-bit timer with auto-
reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto-reload Two 8-bit timers
with auto-reload Two 8-bit timers with auto-reloadTwo 8-bit counter/timers (Timer 0 only)

• TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
One of the clock inputs
Timer/ Counter Registers
Description Register Function
Name
Timer Control Register TCON Enables and disables Timer0 and Timer1, Also has overflow flag and
interrupt related bits
Timer Mode Register TMOD Selects the timer or counter operation with C/T0 and C/T1 bits, Also
has mode selection for timer0 and timer1
Clock Control CKCON Controls clock supplied to timer0 and timer 1 if configured to use
prescaled clock inputs, or system clock
Timer 0 low byte TL0 Lower byte of timer0
Timer 0 high byte TH0 Higher byte of timer0

Timer 1 low byte TL1 Lower byte of timer1

Timer 1 high byte TH1 Higher byte of timer1

Timer 2 low byte TMR2L
Timer 2 High byte TMR2H
 Timer 0 & 1 Mode 1: 16 bit Counter/Timer
• Mode 1: 16-bit Counter/Timer :
• Mode 1 operation is the same as Mode 0, except that the counter/timer
registers use all 16 bits

• The counter/timers are enabled and configured in Mode 1 in the same

manner as for Mode 0.

• TH0 and TL0 holds the count. When the count in TH0 and TL0 overflows
from all ones to 0x00, the timer overflow flag is set. The count in TH0 and
TL0 should be loaded for next iteration.

• If Timer 0 interrupts are enabled, an interrupt will occur when the TF0
flag is set. The count in TH0 and TL0 should be loaded for next iteration.
T0 Mode 1 Block Diagram

1
Timer 0 & 1 Mode 2: 8bit Counter/Timer with Auto-Reload
• Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit
counter/timers with automatic reload of the start value.

• TL0 holds the count and TH0 holds the reload value. When the counter
in TL0 overflows from all ones to 0x00, the timer overflow flag TF0
(TCON.5) is set and the counter in TL0 is reloaded from TH0.

• If Timer 0 interrupts are enabled, an interrupt will occur when the

TF0 flag is set. The reload value in TH0 is not changed. TL0 must be
initialized to the desired value before enabling the timer for the first
count to be correct. When in Mode 2, Timer 1 operates identically to
Timer 0.
T0 Mode 2 Block Diagram
SFR- CKCON: Clock Control
SFR- CKCON: Clock Control
SFR TMOD: Timer Mode(First 4 bits bit 7 to bit 4
dedicated to timer 1)
SFR TMOD: Timer Mode
(Last 4 bits bit 3 to bit 0 are dedicated to timer 0)
SFR TCON: Timer Control
SFR TCON: Timer Control
Configure TMOD register for the following:

• Timer 1 in mode 1
• Timer 1 in mode 2
• Timer 0 in mode 1
• Timer 0 in mode 2
• Timer 1 in mode 2 and Timer 0 in mode 1
Configure TMOD register for the following:
• Timer 0 in mode 1 - 0x01H
Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0
0 0 0 0 0 0 0 1

• Timer 1 in mode 1 – 0x10

Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0
0 0 0 1 0 0 1 0

• Timer 1 in mode 2 –?
• Timer 0 in mode 2 –?
• Timer 1 in mode 2 and Timer 0 in mode 2 – ?
Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0
Time Delay Calculations – For Mode 1
Time period of 1clock cycle = (1/SystemClock)

Count = (Required delay/Time period of 1

clock cycle)

Value to be loaded in timer register,

Value (in decimal)= 65536-Count

Convert Value from decimal to hex (YYXX)

Load YY in THx, and XX in TLx register

Note: Assume SystemClock = 12MHz

 Time Delay Calculations – For Mode 2
Time period of 1clock cycle = (1/SystemClock)
e.g. 12 MHz system clock , time period of 1 clock cycle is:1/12
MHz=

Count = (Required delay/Time period of 1

clock cycle)

Value to be loaded in timer register,

Value (in decimal)= 256-Count

Convert Value from decimal to hex (XX)

Load XX in THx register

 Steps to program in mode 1

1. Load the TMOD value to timer mode register

2. Load the CKCON value to select the clock
3. Load registers TLx and THx
4. Start the timer (SETB TRx)(Timer run bit)
5. Keep monitoring the timer flag (TFx)
6. Stop the timer (CLR TR0 or CLR TR1)
7. Clear the TF flag
8. Go back to step 3
 Steps to program 8-Bit Auto-Reload Mode (Mode 2)
• This mode configures Timers 0 (and 1) to operate as 8-bit counter/timers with
automatic reload of the start value
• The timer low byte (TLx) operates as an 8-bit timer while the timer high byte (THx)
holds a reload value
• When the count in TLx overflows from FFH to 00H, the timer flag is set and the value
in THx is automatically loaded into TLx
• Counting continues from the reload value up to the next FFH overflow, and so on
• This mode is convenient for creating regular periodic intervals, as the timer overflows
at the same rate once TMOD and THx are initialized
• TLx must be initialized to the desired value before enabling the timer for the first count
to be correct
• Timer 1 can be used as an 8-bit baud rate generator for UART0 and/or UART1 in
mode 2
Timer Programs
Configure TMOD register for the following:
• Timer 0
Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0

• Timer 1– counter Timer0 in mode 2

Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0

• Timer 1 in mode 2 –20H

• Timer 0 in mode 2 –02H
• Timer 1 in mode 2 and Timer 0 in mode 2 – 22H
Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0
Procedure for Time to Count Calculation – For Mode 1
Time period of 1clock cycle = (1/SystemClock)

Count = (Required delay/Time period of 1

clock cycle)

Value to be loaded in timer register,

Value (in decimal)= 65536-Count

Convert Value from decimal to hex (YYXX)

Load YY in THx, and XX in TLx register

FIND THE VALUE TO BE LOADED
INTO TIMER REGISTER IF
REQUIRED DELAY IS 4MSEC
(TIMER0 AND MODE 1)
ANS:
COUNT=(17517)d
= (446D)hex
TH0=44h TL0=6Dh
Example for
Time to Count
Calculation
Mode 1

Delay Required=
3mSec
Procedure for Time to Count Calculation– For Mode 2
Time period of 1clock cycle = (1/SystemClock)

Count = (Required delay/Time period of 1

clock cycle)

Value to be loaded in timer register,

Value (in decimal)= 256-Count

Convert Value from decimal to hex (XX)

Load XX in THx register

Example for Time to Count Calculation - Mode 2

Delay Required= 2uSec

Procedure for Count to Time Calculation – For Mode 1
Example for Count to time calculation – For Mode 1
Procedure for Count to Time Calculation – For Mode 2
IF TH0=74hex
Delay?
Example for Count to time calculation – For Mode 2
Steps to program in Mode 1
1. Load the TMOD value to timer mode
2. Load the CKCON value to select the clock
3. Load the count in registers TLx and THx
4. Start the timer (SETB TRx)
5. Keep monitoring the timer flag (TFx)
6. Stop the timer (CLR TR0 or CLR TR1)
7. Clear the TF flag
8. Go back to step 3
Steps to program in Mode 2
1. Load the TMOD value to timer mode
2. Load the CKCON value to select the clock
3. Load the count in register THx
4. Start the timer (SETB TRx)
5. Keep monitoring the timer flag (TFx)
6. Stop the timer (CLR TR0 or CLR TR1)
7. Clear the TF flag
8. Go back to step 4
Timer Programs
Write an embedded C program to flash the LED connected to Port P4 continuously at an
interval of 3mSec. Use Timer 0 in Mode 1 for generating the delay.

#include “c8051F340.h” void Delay()

void Delay(); {
int main()
TH0 = 0x73; //Load High Byte of Count in TH0
{
TL0 = 0x52; //Load Low Byte of Count in TL0
P4MDOUT = 0xFF; // Configure Port4 as output
TMOD = 0x01; // Select Timer 0 in Mode 1 TR0 = 1; //Start the Timer
CKCON = 0x04; // Select System Clock for Timer 0 while (TF0 ==0 ); //Wait for overflow
while (1) TF0 = 0; //Clear overflow flag
{ TR0 = 0; //Stop the Timer
P4 = ~P4; // Compliment Port4 for flashing
}
Delay(); // Delay of 3ms between ON and OFF
status of LED
}
return 0;
}
Write an embedded C program to flash the LED connected to Port P4 continuously at an
interval of 2micro Sec. Use Timer 1 in Mode 2 for generating the delay.

#include “c8051F340.h” void Delay()

void Delay(); {
int main()
TR1 = 1; //Start the Timer
{
while (TF1 ==0 ); //Wait for overflow
P4MDOUT = 0xFF; // Configure Port4 as output
TMOD = 0x20; // Select Timer 1 in Mode 2 TF1 = 0; //Clear overflow flag
CKCON = 0x08; // Select System Clock for Timer 1 TR1 = 0; //Stop the Timer
TH1 = 0x10; //Load High Byte of Count in TH1 }
while (1)
{
P4 = ~P4; // Compliment Port4 for flashing
Delay(); // Delay of 3ms between ON and OFF
status of LED
}
return 0;
}
Interrupt Structure of C8051F340
Interrupt in Embedded System
• An interrupt is a signal to the processor emitted by hardware
or software indicating an event that needs immediate attention.

• Whenever an interrupt occurs, the controller completes the

execution of the current instruction and starts the execution of
an Interrupt Service Routine (ISR) or Interrupt Handler.

• ISR tells the processor or controller what to do when the

interrupt occurs. The interrupts can be either hardware
interrupts or software interrupts.
 Hardware Interrupt and Software Interrupt
• Hardware Interrupt
A hardware interrupt is an electronic alerting signal sent to the processor
from an external device, like a disk controller or an external peripheral. For
example, when we press a key on the keyboard or move the mouse, they
trigger hardware interrupts which cause the processor to read the keystroke
or mouse position.

• Software Interrupt
A software interrupt is caused either by an exceptional condition or a special
instruction in the instruction set which causes an interrupt when it is
executed by the processor. For example, if the processor's arithmetic logic
unit runs a command to divide a number by zero, to cause a divide-by-zero
exception, thus causing the computer to abandon the calculation or display
an error message. Software interrupt instructions work similar to subroutine
calls.
 What is Polling?

• The state of continuous monitoring is known as polling. The

microcontroller keeps checking the status of other devices; and
while doing so, it does no other operation and consumes all its
processing time for monitoring. This problem can be addressed
by using interrupts.

• In the interrupt method, the controller responds only when an

interruption occurs. Thus, the controller is not required to
regularly monitor the status (flags, signals etc.) of interfaced
and inbuilt devices.
 Introduction to Interrupts

• An interrupt is the occurrence of a condition that causes a temporary suspension of

a program while the condition is serviced by another (sub) program

• Interrupts are important because they allow a system to respond asynchronously to

an event and deal with the event while in the middle of performing another task

• An interrupt driven system gives the illusion of doing many things

simultaneously

• The (sub) program that deals with an interrupt is called an interrupt service
routine (ISR) or interrupt handler
 Interrupt Service Routine

For every interrupt, there must be an interrupt service routine

(ISR), or interrupt handler. When an interrupt occurs, the
microcontroller runs the interrupt service routine. For every
interrupt, there is a fixed location in memory that holds the
address of its interrupt service routine, ISR. The table of memory
locations set aside to hold the addresses of ISRs is called as the
Interrupt Vector Table.
Comparison of Polling and Interrupt Method
 Summarize Interrupts…
• An interrupt is an external or internal event that interrupts the
microcontroller to inform it that a device needs its service.

Interrupts vs. Polling

• A single microcontroller can serve several devices.

• There are two ways to do that:

• interrupts
• polling.
• The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
 Interrupts
• When an interrupt occurs, the main program temporarily suspends execution
and branches to the ISR

• The ISR executes, performs the desired operation, and terminates with a “return
from interrupt” (RETI) instruction
• The RETI instruction is different from the normal “RET” instruction

• Finishes the current instruction and saves the contents of PC on stack.

• Jumps to a fixed location in memory depending on the type of an interrupt.

• Starts to execute the interrupt service routine until RETI (return from interrupt).

• Upon executing the RETI the microcontroller returns to the place where it was
interrupted. Get pop PC from stack
Execution Flow Reset
Push PC
on Stack

Execute Push
Main Code Registers
on Stack
Timer Overflow
Interrupt Occurs
At This Time Execute
ISR Code

Pop
Registers
from Stack

Continue to
Execute Pop PC
Main Code from Stack
 Interrupt handler
• Interrupt handler provides 16 interrupt sources into the CIP-51, allowing
numerous analog and digital peripherals to interrupt the controller.

• An interrupt driven system requires less intervention by the MCU, giving

it more effective throughput.

• Each interrupt source can be individually enabled or disabled through the

use of an associated interrupt enable bit in an SFR (IE-EIE2).

• However, interrupts must first be globally enabled by setting the EA bit

(IE.7) to logic 1 before the individual interrupt enables are recognized.
Setting the EA bit to logic 0 disables all interrupt sources regardless of the
individual interrupt-enable settings.
Interrupt Summary
Interrupt
Summary
Interrupt Registers
Sr. Name of Register Function
No
1. Enables and Disables interrupts for entire system and also
IE(Interrupt Enable) enables interrupts from SPI, Timer 2, UART0, Timer 1, Timer 0
and external interrupt 1 and 2
2. Sets the priorities of enabled interrupts in IE register
IP (Interrupt Priority)
3. …
Enabling and Disabling an Interrupt

• Upon Reset, all the interrupts are disabled even if they are
activated. The interrupts must be enabled using software in
order for the microcontroller to respond to those interrupts.

• IE (interrupt enable) register is responsible for enabling and

disabling the interrupt. IE is a bit addressable register.
IE: Interrupt Enable
IE: Interrupt Enable
IP: Interrupt Priority
IP: Interrupt Priority
 Power Management Modes

Power Management Modes

• The CIP-51 core has two software programmable power

management modes:

1. Idle

2. Stop.
 Power Control Register (PCON)
Power Control Register (PCON) is used to control the CIP-51's
power management modes.
SFR Definition PCON: Power Control
 Idle mode
• Idle mode-
• Halts the CPU
• internal registers and memory maintain their original data
• Peripherals and clocks active.
• Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the
CPU and enter Idle.
• Idle mode is terminated when an enabled interrupt is asserted or a
reset occurs. The assertion of an enabled interrupt will cause the Idle
Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation.
• If enabled, the Watchdog Timer (WDT) will eventually cause an
internal watchdog reset and thereby terminate the Idle mode.
 Stop mode

• CPU is halted
• All interrupts inactive
• Internal oscillator is stopped
• All digital & analog peripherals stopped
• External oscillator circuit is not affected
• Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon
as the instruction that sets the bit completes execution.
• Stop mode can only be terminated by an internal or external reset.
• If enabled, the Missing Clock Detector will cause an internal reset and there by terminate
the Stop mode.
• The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode
for longer than the MCD timeout of 100 μsec
Reference

Datasheet:
https://www.silabs.com/documents/public/datasheets/C8051F34x.pdf