Adheesh Trivedi (22016)

EXP I : Familiarize with lab instruments

In partnership with Aditya Pratap Singh (22020)

Objectives
1. Introduction to lab instruments
2. Running a LT Spice simulation

Introduction to lab instruments

Instruments studied
1. Multimeter
2. Oscilloscope
3. Function generator
4. Small resistors
5. DC power supply
Determining the resistance of given resistor
We determined the resistance of the given resistor using a multimeter. Based
on the resistor's colour code, the expected resistance was approximately
10kΩ.

To measure the resistance, we set the multimeter dial to the resistance

measurement mode and connected the test leads to the COM and Ω

Universal Gates August 6, 2024 1

 Adheesh Trivedi (22016)

terminals. The multimeter's functionality was confirmed, as the measured

resistance closely matched the calculated value, falling within the acceptable
error range. This verified the accuracy of the multimeter in measuring
resistance.
DC Power Supply and Voltage measurement
The DC power supply was set to 5V, and the output was then measured using
a multimeter. To measure the voltage, the multimeter dial was set to voltage
measurement mode, and the test leads were connected to the COM and V
terminals.

The measured voltage closely matched the voltage set on the power supply,
verifying the accuracy of both the power supply and the measurement
procedure. This confirms that the setup and the method used to measure the
voltage were correct.
Using the Oscilloscope and Function generator
We experimented with Oscilloscope and function generator. Making a function
wave and trying to find its plot without the auto function, using knob. Adjusting
scale and Location we finally get a good representation of the original function
wave.

Universal Gates August 6, 2024 2

 Adheesh Trivedi (22016)

Left is function generator and right is oscilloscope. We generated a square

wave function and observed the output on the oscilloscope.
1. First connect the wires with any one of the channels of oscilloscope and
function generator.
2. Design a square wave in function generator by going to menu and
selecting square wave.
3. Adjust the parameters on the oscilloscope to nicely visualize the wave
output.
As it’s shown, oscilloscope plots the square wave voltage input.
Precautions
 One shouldn’t operate at high voltages, as it can be dangerous. For our
experiments, we should not go above 12 volts.
 Always turn off the power supply, multimeter, oscilloscope, and other
equipment when not in use to conserve energy and prevent accidents.
 Before powering on any device, double-check all connections to ensure
they are secure and correctly configured to prevent short circuits or
equipment damage.
 Keep all instruments dry and away from liquids to prevent electrical
hazards and equipment malfunction.
 Always ensure that all equipment is properly grounded to avoid electrical
shocks and interference in measurements.

Universal Gates August 6, 2024 3

 Adheesh Trivedi (22016)

LT Spice Simulation
Prerequisites
Install LTSpice on your device. One can install it from LTspice - EngineerZone
(analog.com)
Schematic

We implemented a basic voltage divider on LTSpice with above schematic. We

simulated it to compute and plot the voltages across both resistors.

Green is about both the resistors, while blue is about the 10Ω resistor. ≈3.4V
We thus learnt very basic functionality of LTSpice software. It can be later
used in our course to simulate advanced electronic circuitry.

Universal Gates August 6, 2024 4

 Adheesh Trivedi (22016)

EXP II : Familiarization with DC and AC sources

In partnership with Aditya Pratap Singh (22020)

Objectives
1. Verification of ohm's law using IV characteristics (DC input).
2. Verification of ohm's law using IV characteristics (AC input).
3. Experiment to verify the Voltage Divider Rule.

Verification of ohm's law using IV characteristics (DC)

The circuit diagram for the experiment as shown above.

Required instruments
1. Resistors: 100Ω, 500Ω, 100kΩ, 500kΩ, 10MΩ (1 each)
2. Variable Voltage Source: 0-12V with resolution of .5V or higher
Theory
Current through an ohmic resistor increases proportionally with the increase in
applied voltage i.e.,
V =I × R

where V is applied voltage, and I is the current through the ohmic resistor and
R is the proportionality constant which is known as resistance.
Procedure
1. Make the circuit shown in a breadboard or kit provided.
2. Sweep the voltage from Vmin to Vmax in a small step (say 0.5V).
3. Measure the current using the digital multi-meter and record the values.
4. Plot the I-V characteristics in laboratory book.
5. Repeat the experiment from step 2 to step 4 for different values of R.

Universal Gates August 6, 2024 5

 Adheesh Trivedi (22016)

Take Vmax = 10V or 5V (Based on current change is less or more) and voltage
step between 0.5V to 2V.
Perform the test for 5 different resistances, R = 100Ω, 500Ω, 100kΩ, 500kΩ,
10MΩ
The values of Vmin, Vmax, voltage step and R were given by the instructor in the
lab.
Observations
Voltage (V) Current (mA)
2 17.26
2.5 21.36
3 25.64
3.5 33.23
4 37.25
5 44.30

Resistance will be inverse of the slope of IV graph. Here the slope of best fit
line is nearly 8.99kΩ-1. Thus, the resistance calculated is nearly 111Ω.

Universal Gates August 6, 2024 6

 Adheesh Trivedi (22016)

Voltage (V) Current (µA)

2 0.1
4 0.3
6 0.5
8 0.7
10 0.9

Resistance will be inverse of the slope of IV graph. Here the slope of best fit
line is nearly 0.086MΩ-1. Thus, the resistance calculated is nearly 11.5MΩ.

Universal Gates August 6, 2024 7

 Adheesh Trivedi (22016)

Voltage (V) Current (µA)

2 20.8
4 41.3
6 61.9
8 82.2
10 102.4

Resistance will be inverse of the slope of IV graph. Here the slope of best fit
line is nearly 10.3MΩ-1. Thus, the resistance calculated is nearly 97.4kΩ.

Universal Gates August 6, 2024 8

 Adheesh Trivedi (22016)

Voltage (V) Current (mA)

2 3.69
4 7.21
6 10.87
8 14.54
10 18.12

Resistance will be inverse of the slope of IV graph. Here the slope of best fit
line is nearly 1.813kΩ-1. Thus, the resistance calculated is nearly 551Ω.

Universal Gates August 6, 2024 9

 Adheesh Trivedi (22016)

Voltage (V) Current (µA)

2 3.6
4 7.2
6 10.8
8 14.3
10 17.8

Resistance will be inverse of the slope of IV graph. Here the slope of best fit
line is nearly 1.79MΩ-1. Thus, the resistance calculated is nearly 559kΩ.

Universal Gates August 6, 2024 10

 Adheesh Trivedi (22016)

Verification of ohm's law using IV characteristics (AC)

The above diagram shows the circuit involved in the experiment

Requirements
1. Resistors: 100Ω, 500Ω, 100kΩ, 500kΩ, 10MΩ (1 each)
2. Alternating Voltage Source: With parametric Vpp
Theory
Resistors are bi-directional electronic passive component and hence the
behaviour of the resistor does not change with the direction of current flowing
through it. In AC circuits as shown in figure above, the direction of the current
flowing through a component change with time and the change in the direction
of has no effect on the behaviour of the resistor, thus the current will rise and
fall as the applied voltage rises and falls. In this case, the current through and
voltage across the resistor reach to a maximum value, then fall through zero
and reach to a minimum value at the same time. i.e., they rise and fall
simultaneously and are said to be “in-phase.”
Procedure
1. Make the circuit shown in figure in a breadboard or kit provided.
2. Apply the AC voltage signal at the input side.
3. Measure the AC current using the digital multimeter/digital oscilloscope
and record the values.
4. Plot the I-V characteristics in laboratory book.
5. Change the value of resistor R.
6. Repeat the experiment from step 2 to step 4.
Take Vmax = 10V or 5V (Based on current change is less or more) and voltage
step between 0.5V to 2V.
Perform the test for 5 different resistances, R = 100Ω, 500Ω, 100kΩ, 500kΩ,
10MΩ

Universal Gates August 6, 2024 11

 Adheesh Trivedi (22016)

Observation
For 100Ω resistance:
Voltage (V) Current (mA)
5 52.4
10 105.1
12.5 131.1
15 157.5
20 182.3

Resistance will be inverse of the slope of IV graph. Here the slope of best fit
line is nearly 9.89kΩ-1. Thus, the resistance calculated is nearly 101.1Ω.

Universal Gates August 6, 2024 12

 Adheesh Trivedi (22016)

For 10MΩ resistance:

Voltage (V) Current (µA)
5 .6
10 1.
12.5 1.1
15 1.3
20 1.5

Resistance will be inverse of the slope of IV graph. Here the slope of best fit
line is nearly 0.084MΩ-1. Thus, the resistance calculated is nearly 11.8MΩ.

Universal Gates August 6, 2024 13

 Adheesh Trivedi (22016)

For 100kΩ resistance:

Voltage (V) Current (µA)
5 50.04
10 100.64
12.5 125.38
15 150.12
20 200.16

Resistance will be inverse of the slope of IV graph. Here the slope of best fit
line is nearly 10.02MΩ-1. Thus, the resistance calculated is nearly 99kΩ.

Universal Gates August 6, 2024 14

 Adheesh Trivedi (22016)

For 560Ω resistance:

Voltage (V) Current (mA)
5 9.05
10 16.58
12.5 22.67
15 27.24
20 36.3

Resistance will be inverse of the slope of IV graph. Here the slope of best fit
line is nearly 1.8kΩ-1. Thus, the resistance calculated is nearly 555.55Ω.

Universal Gates August 6, 2024 15

 Adheesh Trivedi (22016)

For 560kΩ resistance:

Voltage (V) Current (µA)
5 10.1
10 21.1
12.5 28.2
15 32.0
20 40.0

Resistance will be inverse of the slope of IV graph. Here the slope of best fit
line is nearly 2.1MΩ-1. Thus, the resistance calculated is nearly 478kΩ.

Universal Gates August 6, 2024 16

 Adheesh Trivedi (22016)

Experiment to verify the Voltage Divider Rule

The focus of this experiment is an examination of basic series DC circuits with
resistors. A key element is Kirchhoff’s Voltage Law which states that the sum
of voltage rises around a loop must equal the sum of the voltage drops. The
voltage divider rule will be investigated.
Theory Overview
A series circuit is defined by a single loop in which all components are
arranged in daisy-chain fashion. The current is the same at all points in the
loop and may be found by dividing the total voltage source by the total
resistance. The voltage drops across any resistor may then be found by
multiplying that current by the resistor value. Consequently, the voltage drops
in a series circuit are directly proportional to the resistance. An alternate
technique to find the voltage is the voltage divider rule. This states that the
voltage across any resistor (or combination of resistors) is equal to the total
voltage source times the ratio of the resistance of interest to the total
resistance.
Equation to find the voltage drop across any of the resistor, suppose, R1,
E × R1
V 1=
R1 + R2 + R3

Equipment
1. Adjustable DC Power Supply
2. Digital Multimeter
3. R1 = 100
4. R2 = 500
5. R3 = 100k

Universal Gates August 6, 2024 17

 Adheesh Trivedi (22016)

Procedure
1. Using the circuit of Fig.1.3 with R1 = 1 k, R2 = 2.2 k, R3 = 3.3 k, and E =
5 volts, determine the theoretical current and record it in table. Construct
the circuit. Set the DMM to read DC current and insert it in the circuit at
point A. Remember, ammeters go in-line and require the circuit to be
opened for proper measurement. The red lead should be placed closer
to the positive source terminal. Record this current. Repeat the current
measurements at points B and C.
2. Using the theoretical current found in Step 1, apply Ohm’s law to
determine the expected voltage drops across R1, R2, and R3. Record
these values.
3. Set the DMM to measure DC voltage. Remember, unlike current, voltage
is measured across components. Place the DMM probes across R1 and
measure its voltage. Again, red lead should be placed closer to the
positive source terminal. Record this value. Repeat this process for the
voltages across R2 and R3. Determine the percent deviation between
theoretical and measured for each of the three resistor voltages and
record.

Universal Gates August 6, 2024 18

 Adheesh Trivedi (22016)

Observation
E = 2V
I Theory I point A I point B I point C
19.88 20.9 20.9 20.9

Voltage across Theory Measured Deviation

R1 = 100 .02 .02 0%
R2 = 500 .004 .003 25%
R3 = 100k 2.01 2.01 0%

E = 10V
I Theory I point A I point B I point C
99.4 101.6 101.6 101.5

Voltage across Theory Measured Deviation

R1 = 100 .06 .056 12%
R2 = 500 .01 .01 0%
R3 = 100k 9.96 9.96 0%

Universal Gates August 6, 2024 19

 Adheesh Trivedi (22016)

EXP III : RC and RL circuit

In partnership with Aditya Pratap Singh (22020)

Objectives:
1. Charging and discharging characteristics of capacitor using DC source.
2. Effect on the output of RC circuit for a square wave input signal.
3. Experiment with RL circuit with DC source. Record the voltage and
current across the L with time.

Charging and discharging using DC source

Capacitor:
A discharged capacitor connected to a DC voltage source charges up with
increase in the voltage of the source. Similarly, a charged capacitor discharges
in opposite direction when the applied voltage of the DC source is reduced.
Capacitors in this line can be compared with small batteries. The charge
stored in a capacitor plates is proportional to the applied voltage and can be
defined as, Q = C × V, where Q is the stored charge, V is the applied voltage,
and C is the proportionality constant which is known as capacitance.
The charging and discharging of capacitor generally takes some time and
depends on the time constant (τ) i.e. the time taken for a certain percentage of
charging and discharging of capacitor. As per the RC circuit given in Fig. 1.3,
the capacitor will charge up through the resistor connected in series with time
until the voltage across the capacitor (VC) becomes equal to supply voltage
(VS). The time constant specifies the rate of charge or discharge and can be
defined as, τ = R × C, where R is in ohm and C is in Farad where the τ is in
seconds. In the given circuit, at any point of time (t) the voltage across the
capacitor can be given by, VC = VS(1 – e−t⁄τ).

~100% charged, i.e. VC ≅ VS;

From the above equation, it is clear that at t = 5τ, the capacitor becomes

at t = 4τ, the capacitor becomes ~98% charged, i.e. VC ≅ 0.98VS; and at t = τ,

the capacitor becomes ~63% charged, i.e. VC ≅ 0.63VS. In this situation, t ≤ 4τ
is known as transient period and t > 4τ is known as steady state where at t=5τ,
the capacitor can be treated as fully charged. Similar is the case for
discharging condition.

Universal Gates August 6, 2024 20

 Adheesh Trivedi (22016)

Results:
Input voltage = 5 Vpp square wave for all the experiments bellow
RC circuit with R = 1kΩ and C = 90nF implies 𝝉 = 90µs;
Time constant Rise time (µs) Fall time (µs) Vout (Volts)
(µs)
𝝉 = 90 45 45 1.41

5 𝝉 = 450 224 226 4.28

8 𝝉 = 720 359 361 4.99

RC circuit with R=1kΩ and C=90nF and 𝝉 = 90µs;

Time constant Rise time (µs) Fall time (µs) Vout (Volts)
(µs)
𝝉 = 90 45 45 0.85

5 𝝉 = 450 226 224 3.16

8 𝝉 = 720 360 360 4.01

Universal Gates August 6, 2024 21

 Adheesh Trivedi (22016)

RC circuit with R=1kΩ and C=8.5nF and 𝝉 = 8.5µs;

Time constant Rise time (µs) Fall time (µs) Vout (Volts)
(µs)
𝝉 = 8.5 4.23 4.27 1.13

5 𝝉 = 42.5 20.9 21.6 3.89

8 𝝉 = 68 33.2 34.8 4.71

RC circuit with R=1kΩ and C=8.5nF and 𝝉 = 8.5µs;

Time constant Rise time (µs) Fall time (µs) Vout (Volts)
(µs)
𝝉 = 8.5 4.24 4.26 0.66

5 𝝉 = 42.5 21.2 21.3 2.83

8 𝝉 = 68 33.8 34.2 3.22

Inductor:
The series LR circuit is composed of an inductor (L) and resistor (R)
connected in series along with a constant DC voltage source V. This is similar
to that of RC circuit discussed in the previous experiment where capacitor (C)
was used instead of inductor (L). Once the circuit is connected to a constant
DC voltage source, the current starts flowing through the circuit but takes
some time to reach to the maximum value as per ohms law i.e. V⁄R. The
reason behind the delay of reaching maximum current is the self-induced emf
within the coil i.e. inductor due to the magnetic flux as per Lenz’s law. Thus, it
takes some time to for the applied voltage source to neutralize the self-
induced emf and thereafter the current becomes constant. The rate of change
of current and voltage depends on the time constant (τ), similar to that of RC
circuit. In case of RL circuit, the time constant is determined and defined as, τ
= L⁄R, where τ is in seconds when inductance L is in Henry and resistance R is
in ohms.
The voltage across the L (VL) at any time t can be given by, VL = V e−t⁄τ, where
V is the applied voltage.

Universal Gates August 6, 2024 22

 Adheesh Trivedi (22016)

Similarly, the current through the L (IL) at any time t can be given by,
IL = (V/R)(1 − e−t⁄τ ), where V is the applied voltage and R is the resistance.

Results:
Input voltage = 5 Vpp square wave for all the experiments bellow
RL circuit with R=1kΩ and L=4.7mH and 𝝉 = 4.7µs,
Time constant (µs) Vout (Volts)
𝝉 = 4.7 1.62

5 𝝉 = 23.5 4.66

RL circuit with R=1kΩ and L=4.7mH and 𝝉 = 4.7µs,

Time constant (µs) Vout (Volts)
𝝉 = 4.7 1.59

5 𝝉 = 23.5 4.64

Output waveform for Inductor Output waveform for Capacitor

Universal Gates August 6, 2024 23

 Adheesh Trivedi (22016)

EXP IV : Low and High pass filters

In partnership with Aditya Pratap Singh (22020)

Objectives
1. Design a passive low-pass filter in LTspice and verify with experiment.
2. Design a passive high-pass filter in LTspice and verify with experiment.

Designing a low-pass filter

Representation of the circuit in LTSpice

Required Instruments
1. Breadboard
2. Signal Generator
3. Oscilloscope
4. Resistance (1 kΩ)
5. Capacitor (1 µF)
6. Connecting wires

Universal Gates August 6, 2024 24

 Adheesh Trivedi (22016)

Theory
The RC low pass filter allows frequency signals below the cut-off frequency fc:
1
f c=
2 π RC

The output voltage signal attenuates when the supply frequency is greater
than the cut-off frequency as shown in figure below. At the cut-off frequency,
capacitor C’s capacitive reactance is equal to resistor R's resistance, causing
the output voltage to be 0.707 times the input voltage (-3 dB).
V out
Gain ( dB ) =20 log
V¿

Here is the output of the

simulation done on LTSpice, for
the Voltage (Amplitude) about
the capacitor for the input
voltage being 2Vpp. The sim
params were as follows:

Universal Gates August 6, 2024 25

 Adheesh Trivedi (22016)

Procedure
1. Connect the circuit as shown in the circuit diagram.
2. Supply the AC sinusoidal signal from the signal generator.
3. Measure the AC output voltage from an oscilloscope (or) multimeter by
varying the supply frequency.
Results
We compare the experimental plots with the plots obtained from LTSpice
above:

As you can see the results are close and withing the margin of experimental
error.

Universal Gates August 6, 2024 26

 Adheesh Trivedi (22016)

Designing a high-pass filter

Representation of the circuit in LTSpice

Required Instruments
1. Breadboard
2. Signal Generator
3. Oscilloscope
4. Resistance (1 kΩ)
5. Capacitor (1 µF)
6. Connecting wires
Theory
The RC high pass filter allows frequency signals above the cut-off frequency fc:
1
f c=
2 π RC

The output voltage signal attenuates when the supply frequency is greater
than the cut-off frequency as shown in figure below. At the cut-off frequency,
capacitor C’s capacitive reactance is equal to resistor R's resistance, causing
the output voltage to be 0.707 times the input voltage (-3 dB).
V out
Gain ( dB ) =20 log
V¿

Universal Gates August 6, 2024 27

 Adheesh Trivedi (22016)

Here is the output of the simulation done on LTSpice, for the Voltage
(Amplitude) about the capacitor for the input voltage being 2Vpp.
Procedure
1. Connect the circuit as shown in the circuit diagram
2. Supply the AC sinusoidal signal from the signal generator.
3. Measure the AC output voltage from an oscilloscope (or) multimeter by
varying the supply frequency.
Results
We compare the experimental plots with the plots obtained from LTSpice
above:

As you can see the results are close and withing the margin of experimental
error.

Universal Gates August 6, 2024 28

 Adheesh Trivedi (22016)

EXP V : RLC circuit

In partnership with Aditya Pratap Singh (22020)

Objectives
1. For the given RLC circuit, apply input signals of different frequencies and
vary the resistance values for a fixed value of L and C and measure
output voltage, Vout(t).
2. Measuring Vout for these combinations for observing underdamp,
overdamp and critically damped behaviour after adjusting the
appropriate values of RLC.

RLC circuit with varying frequency and resistance

Brief theory
The series RLC circuit is composed of a resistor (R), a capacitor (C), and an
inductor (L) connected in series as illustrated in figure. In case of a pure ohmic
resistor the voltage and current waveforms are in-phase with each other. In
case of pure inductance surface the voltage waveform leads the current by 90°
and for pure capacitance the voltage lags the current by 90°.
The mentioned phase difference between the voltage and current depends on
the reactance (X) of circuit. For a purely resistive circuit element, X = 0; for
purely inductive circuit element, X > 0; and for purely capacitive circuit
element, X < 0.
The reactance and impedance of the circuit elements are,

Universal Gates August 6, 2024 29

 Adheesh Trivedi (22016)

The RLC circuit in this case will help us to analyse each circuit element
simultaneously. This circuit is like the series RL and RC circuits discussed
previously, the difference in similar to case is that the reactance of both L and
C will be counted together in overall reactance of the circuit. In the circuit
under consideration consists of a single loop with the same current flowing
through all three-circuit element. Since, the reactance’s of L and C are a
function of frequency (ω = 2πf, f is frequency), hence the sinusoidal response
of the circuit will vary with input frequency, f. In this case, the individual voltage
drop of each circuit element, R, L, and C will be out of phase with each other.
Procedure
1. Connect the circuit as per figure above on breadboard using connecting
wires.
2. Connect the function generator in the input of the circuit.
3. Connect one channel of the oscilloscope across the resistor (R) and the
other channel with input.
4. Provide a sinusoidal signal of amplitude 5 V and a frequency of 50 Hz or
as instructed by the lab instructor.
5. Record the output voltage signal across the resistor.
6. Thereafter, connect the oscilloscope across the inductor and record the
output voltage signal.
7. Finally, connect the oscilloscope across the capacitor and record the
output voltage signal.
8. Change the frequency and plot the frequency versus peak voltage to find
the resonance
9. frequency, ω0 =1/ √ LC .

Universal Gates August 6, 2024 30

 Adheesh Trivedi (22016)

Results
We performed the experiment with three different resistances, 1 kΩ, 10 kΩ
and 220 Ω. The results are as follows:

Notice the peak is nearly at 730 Volts which is roughly equal to our resonance
frequency for the circuit too.

Measuring Voltage for different damping conditions

We take the same circuit as we have taken in previous experiment.

Universal Gates August 6, 2024 31

 Adheesh Trivedi (22016)

Components Required:
1. Inductor
2. Capacitor
3. Resistor (less than, equal to, and more than 110)
4. Breadboard
5. Jumper wires
6. Oscilloscope
Brief Theory:
The basic discussion on the RLC circuit has been discussed in the previous
experiment. If we consider KVL the, VR + VL + VC = V(t) where VR, VL, and VC
are the voltages across, R, L , and C, respectively and V(t) is the input voltage
signal. Substituting the values of the voltages across each electronic
components we get,

for a unchanging voltage signal the same will reduce to,

This can be written as the following form,

Where α = R/2L, is the attenuation or Neper frequency and ω0 = 1/√LC, is the
angular frequency. The term α decides how fast the transient response will
settle down. Depending on the electrical component values the circuit can be
categorized as overdamped, critically damped, and underdamped. The
following are the conditions for the same.
If α > ω0 then it is overdamped
If α = ω0 then it is critically damped
If α < ω0 then it is underdamped

Universal Gates August 6, 2024 32

 Adheesh Trivedi (22016)

Procedure:
1. Connect the circuit as per figure above on breadboard.
2. Connect the function generator in the input of the circuit.
3. Connect one channel of the oscilloscope across the inductor (L) and the
other channel with input.
4. Provide a square wave of amplitude 1 V and a frequency of 50 Hz
(adjust the signal if necessary) or as instructed by the lab instructor.
5. Make the circuit for three different LC combinations as instructed by lab
instructor for three different damping conditions.
6. Expand the time scale of the oscilloscope to get the damping behavior of
the circuit.
7. Connect one channel of the oscilloscope across the capacitor (C) and
the other channel with input.
8. Perform the same experiment (4-6) and observe the damping behavior.
Results:

Overdamped Underdamped

Critically damped

Universal Gates August 6, 2024 33

 Adheesh Trivedi (22016)

EXP VI : Diode Behaviour

In partnership with Aditya Pratap Singh (22020)

Objectives
1. I-V characteristics of a diode
2. Study of Full-wave and Half-wave rectifier circuit
3. Study if Clipper and Clamper circuit

I-V Characteristics of Diode

Brief theory:
A diode is a unidirectional passive device, therefore the polarity of the power
source connected to it counts. An ideal diode is a perfect conductor in one
direction of current and an ideal insulator in the opposing direction. However,
the diode does not behave as an ideal conductor or insulator in any scenario.
A junction diode is essentially a semiconductor PN junction made up of p-type
and n-type semiconductive regions. If the positive (negative) terminal of a
voltage source is connected to the P-side (N-side) of the diode, the diode is
said to be forward biased or ON; otherwise, it is reverse biased or OFF. A true
semiconductor diode built of Silicon requires around 0.7 V forward bias before
it can conduct current.
It conducts very little current in reverse bias, which should ideally be zero. The
forward current moves from the region of p to n. The following formula
represents the typical voltage-current (V-I) relationship in a true PN junction
diode.,

Universal Gates August 6, 2024 34

 Adheesh Trivedi (22016)

VD
nVT
I =I S (e −1)

Where, I is the diode current, I S is the reverse bias saturation current or scale
current, V D Is the applied voltage across the diode, V T Is the thermal voltage,
and nIs the ideality factor.
Procedure:
1. Connect the power supply, voltmeter, ammeter with the diode as shown
in the figure above. Use two multimeters, one to measure current
through diode and other to measure voltage across diode as shown in
the Figure 4.1.
2. Increase voltage from the power supply from 0 V in step as shown in the
observation table.
3. Measure voltage across diode and current through diode. Note down
readings in the observation table.
4. Plot the graphs of Diode voltage vs. Diode current.
Results:

Universal Gates August 6, 2024 35

 Adheesh Trivedi (22016)

Study of Full-wave and Half-wave rectifier circuit

Brief theory:
Rectifiers are the electrical circuits that converts the alternating currents (i.e.
the currents that changes its direction with time) to a direct current (i.e. the
current that has only one direction) by either removing a section of the signal
with one polarity or converting the polarity of the signal to a single one. Most
used two types of rectifiers are the half-wave and full-wave rectifiers. The
associated circuits are given in Figure 4.2.
In case of half-wave rectifier, the diode conducts current only during the
positive cycle of the sinusoidal input and blocks the negative cycle of the input.
Hence, the output of the rectifier is only the positive cycle of the input signal.
Thus, it is called half-wave rectifier as it only rectifies the half part of the full
signal.
In case of full-wave rectifier, the 4 diodes are arranged in such a way that
during positive cycle two of the 4 diodes conduct and during negative cycle the
other two of the 4 diodes will conduct. In both the cases, the current follows
different paths and reflect as a positive signal at the output.

Universal Gates August 6, 2024 36

 Adheesh Trivedi (22016)

Full-wave rectifier:

Half Wave rectifier

Universal Gates August 6, 2024 37

 Adheesh Trivedi (22016)

Study of Clipper and clamper circuit

Brief theory:
Clipper Circuit: Clipping circuits are used to remove a part of a signal that is
above or below a reference level. Clipping circuits are also known as limiters,
amplitude selectors, or slicers. The half-wave rectifier is a good basic example
of a clipper circuit where the reference level is zero, and the signal below zero
voltage (i.e., negative) cannot pass through. A DC voltage source is put in
series with the diode to alter the reference level to a desired value. Depending
on the DC source's polarity and the diode's direction, the circuit will clip the
input signal above or below the reference level set by the user.
Clamping Circuits: Conversely, a clamper circuit shifts a signal to a defined
value. This circuit adds a DC component to the input signal. The circuit can
work with a bias or no-bias condition. If the signal shifts above the central line
of an input wave, it is called a positive clamper circuit; if it shifts downwards, it
is called a negative clamper circuit.

Results:

Output of the clamper circuit

Universal Gates August 6, 2024 38

 Adheesh Trivedi (22016)

The clamper circuit

Output of the clipper circuit

Universal Gates August 6, 2024 39

 Adheesh Trivedi (22016)

EXP VII : Bipolar Junction Transistor

In partnership with Aditya Pratap Singh (22020)

Objective
Study of Common emitter configuration (IC vs VCE for different VBE)

Common emitter configuration

Brief Theory:
Bipolar Junction Transistor (BJT) has three terminals namely, emitter (E), base
(B), and collector (C). A BJT is composed of two PN junctions and the
operation of BJT is mainly based on the PN junction characteristics. In case of
a npn transistor in active region, under forward biased emitter-base (EB)
junction, the majority carrier electrons in n-type emitter region are injected to
thin p-type base region where the electrons as minority carrier diffuse towards
the collector through the reverse biased collector-base (CB) junction. Some of
the electrons recombine with holes in the thin p-type base region to produce a
small base current (IB) and the remaining reach collector as a collector current
(IC).

Universal Gates August 6, 2024 40

 Adheesh Trivedi (22016)

Hence, if there is no current from emitter (IE), then there will be almost no IC.
Combining all the currents, the total emitter current, IE = IB + IC.
In case of pnp transistor, the polarity of voltage sources must be reversed.
Depending on the biasing of two junctions (i.e. EB and CB) transistor, the
transistor can be said to be in different modes of operation.

Output characteristics are obtained between the output voltage and output
current at constant input current. It is plotted between VCE and IC at constant
IB in CE configuration.
Results:

Above are the plots obtained for PNP

Universal Gates August 6, 2024 41

 Adheesh Trivedi (22016)

Above are the plots obtained for NPN

These are the output characteristic.

Universal Gates August 6, 2024 42

 Adheesh Trivedi (22016)

EXP VIII : Universal Gates

Objective
Realization of logic functions with the help of universal gates NAND and NOR
Gate

Materials Required
 NAND IC – 7400
 NOR IC – 7404
 Bread Board
 Jumper wires
 LEDs
 DMM
 DC Power supply

Nand
NAND gate is a combination of two logic gates i.e. AND gate followed by NOT
gate. So its output is complement of the output of an AND gate. This gate can
have minimum two inputs. By using only NAND gates, we can realize all logic
functions: AND, OR, NOT, Ex-OR, Ex-NOR, NOR. So this gate is also called
as universal gate.

NAND gate as OR
From DeMorgan’s theorems:

Universal Gates August 6, 2024 43

 Adheesh Trivedi (22016)

( A . B)’=A ’+ B ’

( A ’ . B’ )’= A ’ ’ + B ’ ’=A + BSo, give the inverted inputs to a NAND gate, obtain OR
operation at output.

0 or 0 1 or 0 / 0 or 1

1 or 1
NAND gate as AND
A NAND produces complement of AND gate. So, if the output of a NAND gate
is inverted, overall output will be that of an AND gate.

Universal Gates August 6, 2024 44

 Adheesh Trivedi (22016)

Y =((A . B)’ )’

Y =( A . B)

0 and 0 1 and 0 / 0 and 1

1 and 1
NAND gates as Ex-OR
The output of a two input Ex-OR gate is shown by: Y = A’B + AB’. This can be
achieved with the logic diagram shown in the left side.

Universal Gates August 6, 2024 45

 Adheesh Trivedi (22016)

0 xor 0 0 xor 1 / 1 xor 0

1 xor 1

Universal Gates August 6, 2024 46

 Adheesh Trivedi (22016)

NAND gates as Ex-NOR

Ex-NOR gate is actually Ex-OR gate followed by NOT gate. So give the output
of Ex-OR gate to a NOT gate, overall output is that of an Ex-NOR gate.

Y = AB+ A ’ B ’

0 n-xor 0 0 n-xor 1 / 1 n-xor 0

1 n-xor 1

Universal Gates August 6, 2024 47

 Adheesh Trivedi (22016)

NOR
NOR gate is actually a combination of two logic gates: OR gate followed by
NOT gate. So its output is complement of the output of an OR gate.This gate
can have minimum two inputs, output is always one. By using only NOR gates,
we can realize all logic functions: AND, OR, NOT, Ex-OR, Ex-NOR, NAND. So
this gate is also called universal gate.

Universal Gates August 6, 2024 48

 Adheesh Trivedi (22016)

NOR gates as OR
A NOR produces complement of OR gate. So, if the output of a NOR gate is
inverted, overall output will be that of an OR gate.
Y =((A + B)’)’

Y =( A+ B)

0 or 0 0 or 1 / 1 or 0

1 or 1

Universal Gates August 6, 2024 49

 Adheesh Trivedi (22016)

NOR gates as AND

From DeMorgan’s theorems:
( A+ B)’= A ’ B ’

( A ’+ B ’)’= A ’ ’ B ’ ’= AB

So, give the inverted inputs to a NOR gate, obtain AND operation at output.

0 and 0 0 and 1 / 1 and 0

1 and 1

Universal Gates August 6, 2024 50

 Adheesh Trivedi (22016)

NOR gates as Ex-OR

Ex-OR gate is actually Ex-NOR gate followed by NOT gate. So give the output
of Ex-NOR gate to a NOT gate, overall output is that of an Ex-OR gate.
Y = A ’ B+ AB ’

0 xor 0 0 xor 1 / 1 xor 0

1 xor 1

Universal Gates August 6, 2024 51

 Adheesh Trivedi (22016)

NOR gates as Ex-NOR

The output of a two input Ex-NOR gate is shown by: Y = AB+ A ’ B ’. This can be
achieved with the logic diagram shown in the left side.

0 x-nor 0 0 x-nor 1 / 1 x-nor 0

1 x-nor 1

Universal Gates August 6, 2024 52

 Adheesh Trivedi (22016)

Results
The setup done through experiments are along the theory of truth tables. Thus
we verify the setup and universality of NAND and NOR gates.

Universal Gates August 6, 2024 53