Digital Logic Test 1

Number of Questions: 25 Section Marks: 30

Directions for questions 1 to 25: Select the correct alterna- (A) x1 y, z (B) x + y1, z1
tive from the given choices. (C) x, z (D) x1 + y, z
1. Assume the propagation delay time of 2 input gates as 9. In the above problem statement, how many number of
EXOR-20 ns, AND – 10 ns, OR-10 ns, the propaga- NOR are gates required implement output B.
tion delay time for sum and carry output of a full adder (A) 3 (B) 4
circuit are respectively, when all the data inputs are (C) 5 (D) 6
applied simultaneously? 10. A combinational circuit takes 2 inputs and output is the
(A) 30 ns, 20 ns (B) 40 ns, 30 ns 2’s complement of input binary number. Consider the
(C) 40 ns, 20 ns (D) 20 ns, 20 ns inputs as a and b and output as x and y, the equations of
2. The minimized POS expression of the function f (A, B, x and y respectively?
C, D) = AB + AC + C + AD + ABC + ABC (A) a  b, b (B) a1 b, a  b
(A) A + C (B) A + B
1
(C) a b, ab 1
(D) a ⊕ b, b
(C) AC (D) A + C 11. The output F in the digital logic circuit shown in the
figure is:
3. The signed two’s complement representation of
XNOR
(–783)10 is (in HEX): a
(A) 830FH (B) 04F1H b
(C) FCF1H (D) F3F1H F
4. The two numbers represented in signed 2’s complement NOR
form are: c
P = 11011101 and Q = 11100101, if Q is subtracted XOR
from P, the value obtained in signed 2’s complement
form is? (A) a1 bc + ab1 c (B) a1bc1 + ab1c1
1 1
(A) 11110111 (B) 11000010 (C) a b c + abc (D) a1b1c1 + abc
(C) 11111000 (D) 00000111 12. To construct a 5 to 32 line decoder, how many num-
5. The subtraction of a binary number B from another bers of 3 to 8 line decoders and 2 to 4 line decod-
binary number A, done by adding the 2’s complement ers are required respectively without using any extra
of B to A, results in a binary number without carry, this hardware?
implies that the result is: (A) 3, 2 (B) 4, 1
(A) negative and is in normal form (C) 2, 4 (D) 2, 2
(B) positive and is in normal form 13. Parity is a common error detection mechanism that
(C) negative and is in 2’s complement form is often used in data reception or retrieval systems.
(D) positive and is in 2’s complement form Consider a parity encoder that is used for data trans-
6. f (a, b, c) = ab + b1c in the canonical POS form is rep- mission or storage. If a word contains an even number
resented as: of 1’s, the parity bit is 0. If the word has odd number of
(A) (a + b + c) (a + b + c1) (a + b1 + c) (a1 + b1 + c) 1’s the parity bit is 1. If the data is w, x, y, z then the min
(B) (a + b1 + c) (a + b1 + c1) (a + b + c) (a1 + b + c) terms for parity bit is?
(C) (a + b + c) (a1 + b1 + c) (a + b1 + c) (A) ∑m(1, 2, 4, 7, 8, 11, 13, 14)
(D) (a1 + b + c) (a1 + b1 + c) (a + b + c) (a + b1 + c) (B) ∑m(0, 3, 5, 6, 9, 10, 12, 15)
7. The Essential prime Implicants of the function (C) ∑m(0, 1, 3, 5, 8, 10, 13, 15)
f (A, B, C, D) = AC + ABD + AB + BD + ABCD are: (D) ∑m(1, 3, 5, 7, 9, 11, 13, 15)
(A) BD, BD, A (B) AC , BD, B 14. Consider the Boolean functions
f1 (A, B, C, D) = AC + BD
(C) BD, AC , B (D) AB , BD, C
f2 (A, B, C, D) = ∑m(4, 5, 6, 7, 10, 11, 14, 15)
8. A combinational circuit has 3 inputs x, y, z and three Then find f1 + f2 in minimized POS form
outputs A, B, C. When the binary input is 4, 5, 6 and 7, (A) ( A + B )( B + D )( A + B + C )
the binary output is 2 less than the binary input. When
(B) ( A + B)( B + C )( A + C + D )
the binary input is 0, 1, 2 and 3, the output is 4 more
than the binary input the Boolean expression for output (C) ( A + B )( B + D )( A + C + D )
A and C respectively are: (D) ( A + D )( B + C )( A + B + C )
3.6 | Digital Logic Test 1

15. A 16-bit ripple carry adder is realized using 16 identi- ac + d = 1

cal full address as shown in figure. The carry propaga- ab + cd = 0
tion delay of each FA is 15 ns and the sum propagation have the following solutions for a, b, c and d respec-
delay of each FA is 18 ns. tively:
The worst delay of this 16-bit adder will be: (A) 1011 (B) 1100
A B A B A1 B1 A1 B1 (C) 1000 (D) 1101
22. What is Boolean expression for output (F) of the com-
C1 binational logic circuit of NAND-NOR gate given
F F F F C1
0 CD C1 below?
A
S0 S1 S1 S1 B

C
(A) 243 ns (B) 228 ns
A
(C) 240 ns (D) 270 ns F
16. For an n-variable Boolean function, the maximum B
C
number of prime implicants is:
n A
(A) (B) 2n – 1
2 B
(C) 2n–1 (D) 2n
(A) A + B (B) A + C
17. If the Boolean function f (a, b, c, d) = a + b + c + d has
to be implemented with only 2 input NAND gates, then (C) ABC (D) A + B + C
how many NAND gates are required? 23. Let f (A, B, C, D) = ∑m(0, 2, 3, 4, 5, 7, 9, 13, 15)
(A) 6 (B) 7 Which of the following expressions is not equivalent
(C) 8 (D) 9 of f ?
18. The following expression is valid for the number sys- (P) ABD + ABC + ACD + ACDBD
302 (Q) ACD + ABC + ACD + BD
tem with base ______ = 12.1.
20 (R) ABD + ABC + BCD + ACD
(A) 6 (B) 5 (S) ABD + ACD + ABD + ACD
(C) 4 (D) 8 (A) only Q (B) only S
19. P is a 16 bit signed number integer, the 2’s complement (C) P and S (D) P and Q
representation of P is (FB8A)16. The 2’s complement 24. The range of integers that can be represented by an ‘n’
representation of 8 × P is: bit 2’s complement signed number system is:
(A) (B8 A0)16 (B) (C 7B4)16 (A) –2n–1 to +(2n–1 – 1)
(C) (ABCD)16 (D) (DC50)16 (B) –(2n–1 – 1) to +(2n–1 – 1)
20. For a 4 bit magnitude comparator with two inputs each (C) –2n–1 + 1 to +2n–1
of 4 bit A(a3, a2, a1, a0) and B(b3, b2, b1 b0), the Boolean (D) –2n–1 to +2n–1
equation for A < B is: 25. The minimized POS expression for k-map shown is:
(A) a13b3 + a12 b2 + a11b1 + a10 b0
AB
00 01 11 10
(B) a3b31 + ( a3 ⊕ b3 )a2 b21 + ( a3 ⊕ b3 )( a2 ⊕ b3 )a2 b1 CD

+ ( a3 ⊕ b3 )( a2 ⊕ b2 )( a1 ⊕ b1 )a0 b0 00 0 0 X

(C) a13b3 + ( a3 ⊙ b3 )a12 b2 + ( a3 ⊙ b3 )( a2 ⊙ b2 )a11b1 01 X X X

+ ( a3 ⊙ b3 )( a2 ⊙ b2 )( a1 ⊙ b1 )a10 b0
11 0 0 0
(D) a13b3 + ( a3 ⊕ b3 )a12 b2 + ( a3 ⊕ b3 )a11b1 + ( a3 ⊕ b3 )
( a2 ⊕ b2 )( a1 ⊕ b1 )a10 b0 10 0 0 0
21. The simultaneous equations on the Boolean variables
a, b, c and d. (A) A + B (B) AB
a+b+c=1
ab = 0 (C) A + B ( A + B )( A + B) (D) A( A + B)
 Digital Logic Test 1 | 3.7

Answer Keys
1. B 2. D 3. C 4. C 5. C 6. B 7. A 8. D 9. C 10. D
11. B 12. B 13. A 14. B 15. A 16. C 17. D 18. C 19. D 20. C
21. A 22. D 23. D 24. A 25. B

Hints and Explanations

1. Sum = a ⊕ b ⊕ c 6. f (a, b, c) = ab + b1 ⋅ c
Carry = ab + bc + ac = (ab + b1)(ab + c) [x + yz = (x + y)(x + z)]
a = (a + b1)(a + c)(b + c)
b Sum = (a + b1 + c ⋅ c1)(a + b ⋅ b1 + c)(a ⋅ a1 + b + c)
c = (a + b1 + c)(a + b1 + c1)(a + b + c)(a + b1 + c)(a + b + c)
(a1 + b + c)
20 + 20 = 40 ns = (a + b1 + c)(a + b1 + c1)(a + b + c)(a1 + b + c)
a Choice (B)
b
b 7. f (A, B, C, D) = AC + ABD + AB + BD + ABCD
c
Product term Equivalent Min terms
a
c AC 0X1X 0010, 0011, 0110, 0111

10 + 10 + 10 = 30 ns ABD 11X1 1101, 1111

Two level exor gate for sum AB 01XX 0100, 0101, 0110, 0111
So 20 + 20 = 40 ns
BD X0X0 0000, 0010, 1000, 1010
Carry will be implemented with 2 input gates in 3 lev-
els, so 10 + 10 + 10 = 30 ns Choice (B) ABCD 0001 0001
2. f = AB + AC + C + AD + ABC + ABC
f (A, B, C, D) = ∑m(0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 13, 15)
= AB + A + C + AD + AC
= A( B + 1 + D + C ) + C CD
AB 00 01 11 10
=A+C Choice (D)
00 1 1 1 1
3. 783 = 512 + 256 + 8 + 4 + 2 + 1 = 1100001111
+783 = 0000 0011 0000 1111 (add 0’s to MSB) 01 1 1 1 1
– 783 = 1111 1100 1111 0001 (2’s complement of +783)
In HEX ⇒ FCF1 Choice (C) 11 1 1
4. P = 11011101
10 1 1
00100011 (by taking 2’s complement)
P = –35
Q = 11100101
00011011 (By taking 2’s complement) f (A, B, C, D) = A + BD + BD
Q = –27 Essential prime implicants are A, BD, BD
P – Q = –35 – (–27) = –8 = 1111 1000 (in signed 2’s Choice (A)
complement form) 8. The truth table is:
(or)
x y z A B C
P = 1101 1101 0 0 0 1 0 0
Q = 1110 0101 (direct subtraction) 0 0 1 1 0 1 output is 4 more
0 1 0 1 1 0 than input
1111 1000 Choice (C) 0 1 1 1 1 1
5. A – B has to be performed 1 0 0 0 1 0
1 0 1 0 1 1
So, the 2’s complement of B (which is 2n – B, n = no. of 1 1 0 1 0 0 output is 2 less
bits in B) is added to A 1 1 1 1 0 1 than input
So result is A + 2n – B; and there is no carry
A + 2n – B = 2n – (A – B) A(x, y, z) = ∑m(0, 1, 2, 3, 6, 7)
So, the result is negative and it is in 2’s complement B(x, y, z) = ∑m(2, 3, 4, 5)
form. Choice (C) C(x, y, z) = ∑m(1, 3, 5, 7)
3.8 | Digital Logic Test 1

The k map for A So parity bit P = w ⊕ x ⊕ y ⊕ z

yz P = ∑m(0001, 0010, 0100, 0111, 1000, 1011, 1101,
x 00 01 11 10
1110)
0 1 1 1 1 = ∑m(1, 2, 4, 7, 8, 11, 13, 14) Choice (A)
A = x1 + y
1 1
14. f1 (A, B, C, D) = AC + BD
1
= AC ( B + B )(C + C ) + ( A + A)(C + C ) BD
The k map for C = ∑m(5, 7, 10, 11, 13, 14, 15)
= PM(0, 1, 2, 3, 4, 6, 8, 9, 12)
yz
x 00 01 11 10 f2 = ∑m(4, 5, 6, 7, 10, 11, 14, 15)
= PM(0, 1, 2, 3, 8, 9, 12, 13)
0 1 1
C=z f1 + f2 = PM(0, 1, 2, 3, 8, 9, 12) [common max terms of
1 1 1 f1 and f2]
CD
AB 00 01 11 10
Choice (D)
00 0 0 0 0
9. B(x, y, z) = ∑m(2, 3, 4, 5)
yz 01
00 01 11 10
x
0 1 1 11 0
B = xy1 + x1y = x ⊕ y
1 1 1 10 0 0

2 input XOR required 5 NOR gates. Choice (C)

10. a, b are inputs of 2’s complementer, and x, y are the f1 + f2 = (A + B) (B + C) (A + C + D) Choice (B)
outputs. 15. The final carry we will get after n times of the delay of
So truth table is the carry of each full adder. But sum has more propaga-
a b x y tion delay. To get the carry of last but one, stage (C14)
0 0 0 0 we required 15 × t carry = 15 × 15 = 225 ns
0 1 1 1
1 0 1 0
The next carry C15 we get after another 15 ns, but sum
1 1 0 1 S15 we get after another 18 ns (= 243 ns)
The worst delay = (n – 1)tcarry + tsum = (16 – 1) × 15 + 18
x = a1b + ab1 = a ⊕ b = 243 Choice (A)
y=b Choice (D) 16. Choice (C)
11. Output of XNOR = a  b = a b + ab
1 1
17.
Output of XOR = [a  b] ⊕ c = A
Output of NOR gate = [a  b ⊕ c + (a  b)]1 B f
(x ⊕ y + x) = x1y + xy1 + x = x + y C
[(a  b) ⊕ c + (a  b)]1 = (a  b + c)1 D
= (a  b)1 ⋅ C1 = (a ⊕ b) c1 = a1bc1 + ab1c1
Choice (B) Each 2 input OR gate required 3–2 input NAND gates
12. 5 to 32 line decoder will have 32 output lines So total 9 NAND gates are required. Choice (D)
So 4, 3 to 8 line Decoders are required, these 4 decod- (302) r
18. = (12.1) r
ers will be selected by one 2 to 4 lines decoder. (20) r
So 4, 3 to 8 line decoder and 1, 2 to 4 line decoder Convert to decimal number system
(or)
3r 2 + 0 r1 + 2r 0 1
5 to 32 line decoder will have 32 output lines
1 0
= 1r1 + 2r 0 + 1
So 8, 2 to 4 line Decoders are required, to select one of 2r + 0 ⋅ r r
these 8, one 3 to 8 line Decoder is required. 3r 2 + 0 ⋅ r1 + 2 ⋅ r 0 1
8, 2 to 4 Decoders, and 1, 3 to 8 Decoder. Choice (B) − 1 0
= 1 ⋅ r1 + 2 ⋅ r 0 + 1 ⋅
2r + 0 ⋅ r r
13. For even number of 1’s parity bit is 0.
So even parity, 3r 2 + 2 1
= r + 2 + ⇒ 3r 2 + 2 = 2r 2 + 4 r + 2
Even parity can be implemented by XOR gate 2r r
XOR of even 1’s given output 0. ⇒ r2 = 4r ⇒ r = 0 or 4
XOR of add 1’s gives output 1. r = 4 is valid Choice (C)
 Digital Logic Test 1 | 3.9

19. P = FB8A = 1111101110001010 Similarly output of 2nd NOR-NAND structure

8P = 23 P → P shifted to left by 3 bits, =A+B+C
8P = 1101 1100 0101 0000 So output F = A + B + C Choice (D)
= (DC50)16 Choice (D) 23. We can verify by writing the min terms
20. If A(a3 a2 a1 a0) and B(b3 b2 b1 b0) are the two inputs the (P) ABD + ABC + ACD + ACD + BD
A < B is possible only when the bits in A are 0 and the 00X0 010X 0X11 1X01 X1X1
bits in B are 1. So we can check MSB by using a13b3 ,
∑m(0, 2, 3, 4, 5, 7, 9, 13, 15)
if the MSB bits are equal, then we check next bits
(a3  b3) a12 b2 and if the higher order bits are equal (Q) ACD + ABC + ACD + BD
then we move to next bits so (A < B) = a13b3 + (a3  b3) 0X00 001X 1X01 X1X1
a12 b2 + (a3  b3) (a2  b2) a11b1 + (a3  b3)(a2  b2) ∑m(0, 2, 3, 4, 5, 7, 9, 13, 15)
(a1  b1) a10 b0. Choice (C) (R) ABD + ABC + BCD + ACD 00X0, 010X,
X111, 1X01
21. a + b + c = 1 ∑m(0, 2, 4, 5, 7, 9, 13, 15) – min term 3 missing
ab = 0 → by substituting in 4th equation
(S) ABD + ACD + ABD + ACD 00X0, 0X11, 11X1,
ab + cd = 0 ⇒ 0 + cd = 0 ⇒ c + d = 0
1X01
⇒ c+d=1
ac + d = 1 ⇒ (a + d) (c + d) = 1 ∑m(0, 2, 3, 7, 9, 13, 15) – min terms 4, 5 missing.
already c + d = 1 so a + d = 1 Choice (D)
So we have now a + b + c = 1, ab = 0, c + d = 1, 24. Choice (A)
a + d = 1 by verification option (A) is valid for all
25. Two octates present so minimized expression is A ⋅ B
the four equations. Choice (A)
AB
22. NOR–NAND is equivalent to OR-OR CD 00 01 11 10
00 0 X X

01 X X X

11 0 0 0

So output of 1st NOR-NAND structure = A + B + C + A 10 0 0 0

=A+B+C
Choice (B)