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ch7

Chapter 7 of 'Digital Fundamentals' by Thomas L. Floyd discusses latches, flip-flops, and timers, detailing their functions and applications. It explains the operation of S-R latches, gated latches, D latches, and various types of flip-flops, including their asynchronous inputs and timing specifications. Additionally, the chapter covers the use of flip-flops in frequency division and counting, as well as the functionality of one-shot devices.

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29 views36 pages

ch7

Chapter 7 of 'Digital Fundamentals' by Thomas L. Floyd discusses latches, flip-flops, and timers, detailing their functions and applications. It explains the operation of S-R latches, gated latches, D latches, and various types of flip-flops, including their asynchronous inputs and timing specifications. Additionally, the chapter covers the use of flip-flops in frequency division and counting, as well as the functionality of one-shot devices.

Uploaded by

gxrc46r82m
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Digital Fundamentals

Thomas L. Floyd

Latches, Flip-Flops, and Timers


Chapter 7
Ch.7 Summary

Latches
A latch is a temporary storage device that has two stable states
(bistable). It is a basic form of memory.

The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds to
active-HIGH inputs; with NAND gates, it responds to active-LOW inputs.
Ch.7 Summary

Latches
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
Assume the latch is initially
RESET (Q = 0) and the inputs
are at their inactive level (0). To
SET the latch (Q = 1), a
momentary HIGH signal is
applied to the S input while the
R remains LOW.

To RESET the latch (Q = 0), a


momentary HIGH signal is
applied to the R input while the
S remains LOW.
Ch.7 Summary

Latches
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET
(Q = 0) and the inputs are at their
inactive level (1). To SET the latch
(Q = 1), a momentary LOW signal is
applied to the S input while the R
remains HIGH.
To RESET the latch a momentary
LOW is applied to the R input
while S is HIGH.

Never apply an active set and reset at the same time (invalid).
Ch.7 Summary

Latches
Ch.7 Summary

Latches

The three modes of


basic S-R operation
Ch.7 Summary

Latches
Ch.7 Summary

Latches
Ch.7 Summary

Latches: Applications
Ch.7 Summary

Gated S-R Latch


A gated latch is a variation on the basic latch.
The gated latch has an additional input, called enable
(EN) that must be HIGH in order for the latch to
respond to the S and R inputs.
Ch.7 Summary

Gated S-R Latch


Ch.7 Summary

Gated D Latch
The D latch is an variation of the S-R latch but combines the
S and R inputs into a single D input as shown:

A simple rule for the D latch is:


Q follows D when the EN is active.
Ch.7 Summary

Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be
positive or negative.
Ch.7 Summary

Edge-Triggered Flip-flops

The output from an edge-


triggered flip-flop changes
on the positive-going or
negative-going edge of its
clock signal.

A bubble on the clock


input indicates that it is a
negative-edge triggered
flip-flop.
Ch.7 Summary

Edge-Triggered D Flip-flops
The data bit at the D-input is transferred to the component output
on the edge of the clock signal.

Once triggered, the output (Q) equals the last value at the D input
until a new value is triggered in.
Ch.7 Summary

Edge-Triggered D Flip-flops
Ch.7 Summary

J-K Flip-flops

The values at the


J and K inputs to
a J-K flip-flop
determine its
output state.
The results of
the four possible
input
combinations of
J and K are
shown.
Ch.7 Summary

J-K Flip-flops
Ch.7 Summary

J-K Flip-flops
Ch.7 Summary

Edge Triggered Operation


Ch.7 Summary

D Flip-flops
Ch.7 Summary

D Flip-flops
Ch.7 Summary

J-K Flip-flops
Ch.7 Summary

J-K Flip-flops
Ch.7 Summary

Flip-flop Asynchronous Inputs


Synchronous (clocked) inputs are transferred on the
triggering edge of the clock. Most flip-flops have other inputs
that are asynchronous, meaning they operate independently
of the clock.
Asynchronous flip-flop inputs are
normally labeled preset (PRE) and clear
(CLR). These inputs are usually active
LOW. A J-K flip flop with active LOW
preset and CLR is shown.
Note that the asynchronous inputs
always override the synchronous inputs.
Ch.7 Summary

Flip-flop Asynchronous Inputs


Ch.7 Summary

Flip-Flop Propagation Delay


Propagation delay time is specified for the rising and falling
outputs. It is measured between the 50% level of the clock to the
50% level of the output transition.

Propagation delay (tPLH) is measured as shown in (a). Propagation delay


(tPHL) is measured as shown in (b).
Ch.7 Summary

Flip-flop Propagation Delay


Another propagation delay time specification is the time
required for an asynchronous input to cause a change in
the output. Again it is measured from the 50% levels.
Ch.7 Summary

Flip-flop Set-up Time


Another time-related specification is flip-flop set-up time.
This is the minimum time between the arrival of an input to
the D (or J-K) flip-flop and the CLK signal.
Ch.7 Summary

Flip-flop Hold Time


Another time-related specification is flip-flop hold time.
This is the minimum time over which the input to the D (or
J-K) flip-flop must remain stable after the arrival of the CLK
input for reliable triggering.
Ch.7 Summary

Flip-Flop Frequency Division


Flip-flops can be used as frequency dividers, as shown below.

The D and J-K flip flops on the left are wired as “divide-by-2” circuits.
The J-K flip-flops on the right are cascaded to form a “divide-by-4”
circuit.
Ch.7 Summary

Flip-Flop Counters
Flip-flops can be
used to count the
number of clock
signals they receive
as shown here.
Each CLK input triggers
the flip-flops, which are
wired to toggle whenever
triggered.
The QA and QB outputs
indicate the number of
CLK inputs received.
Ch.7 Summary

One-Shots
The one-shot or monostable multivibrator is a device
with only one stable state. When triggered, it goes to its
unstable state for a predetermined length of time, then
returns to its stable state.
Ch.7 Summary

Nonretriggerable One-Shots
A nonretriggerable one-shot does not respond to any
triggers that occur while in its unstable state, as shown here.
Ch.7 Summary

Retriggerable One-Shots
Retriggerable one-shots respond to any trigger, even if it
occurs while the component is in its unstable state. If it
occurs during the unstable state, the state is extended by an
amount equal to its normal output pulse width.
Ch.7 Summary

A One-Shot Sequential Timer


One-shots can be wired (as shown) to form a sequential
timer; a circuit that can set up a sequence of actions, such
as lighting a group of lights in a particular order.

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