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Timing Arc and It's characteristics

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Madhuri Ushannagari
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37 views5 pages

Timing Arc and It's characteristics

Uploaded by

Madhuri Ushannagari
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Standard Cells

The chip is designed using the basic blocks such as AND,OR,NOT,NAND,


FLIPFLOPS,LATCHES etc.,
They are called as Standard cells. They are predesigned.
The timing and Functionality of these Standard Cells is available to the user in
the form of nothing but called standard cell Libraries.

Timing Arcs
A timing arc is a representation of the relationship between an input pin and
an output pin of a logic cell (or gate) that defines how a change in the input
propagates to the output
A path from each input pin to the each output pin of the cell.
- Provides a simple understanding of the structure of the gate
There are two types of timing Arcs:
1. Cell Arc
2. Net Arc

Cell Arc:
Cell Arc is present between input pin and output pin of a cell.
There are 2 types of Cell Arcs:
 Combinational Cell Arc
 Sequential Cell Arc

Combinational Cell Arcs:


These arcs represent the timing paths through combinational logic gates, such
as AND, OR, NOT, etc.
Sequential Cell Arcs:
These arcs represent the timing paths through sequential elements, such as
flip-flops and latches.

Timing check Arc ( for setup and hold):


Represents the relationship between the data input and the clock input,
ensuring that data is stable before the clock edge.
Delay Arc:
Represents the delay from the clock input to the output (Q) of a flip-flop.

Net Arc:
Net arcs represent the timing paths that include the delays introduced by the
interconnects (wires) between different circuit elements.
The Arc between source pin(output pin of the cell) and the sink pin(input pin of
an another cell).
Consist of the source pin (starting point of the net), the destination pin (ending
point of the net), and the propagation delay caused by the net.
They capture the delay due to the resistance and capacitance of the
interconnect, which can significantly impact the overall timing of the circuit.
These arcs are always a delay timing arcs.

Characteristics of a Timing Arc:


There are mainly 3 characteristics of Timing arcs. They are Delay, Unateness
and Slew.
1.DELAY:
- Cell delay and net delay
Cell delay can be determined by
1. Intrinsic delay: Time for the gate to produce an output
2. The load it is driving
3. Input transition also known as input slew: Time for the output signal
to transition
Cell delay = intrinsic delay + transition delay
Intrinsic delay: It represents the time taken by the gate to process the
input and produce an output transition (e.g., LOW to HIGH or HIGH to
LOW).
Transition delay: The time it takes for the signal at the output of a gate to
change from one logic level to another (e.g., rising from 0 to 1 or falling
from 1 to 0).
Net delay:
 Occurs due to resistance and capacitance of the inter connect
 Wire-Load Models are used to calculate Net delay

WIRE LOAD MODELS(WLM):


A Wire Load Model (WLM) is a method used in static timing analysis (STA) to
estimate the delay and capacitance of nets (wires) in a circuit before detailed
physical design is completed (during pre-layout analysis).
Purpose:
 Before the placement and routing stages in the design flow, the exact
geometry of wires is unknown. WLM provides an approximate way to
model the delay and load of interconnects based on logic synthesis
information.
 A WLM predicts:
o Wire Capacitance: Total capacitance of the net.
o Wire Resistance: Total resistance of the net.
o Fanout Dependency: The estimation depends on the number of
pins (fanout) connected to the net.
How STA Calculates Net Delay Using WLM
- WLM is an estimation of delay based on area and fanout.
- The net resistance (R) and net capacitance(C) are used to calculate net
delay.
- Net delay = Rnet * Cnet
- The wire load model is also used to estimate the length of a net-based upon
the number of its fanouts.
- The wire load model depends upon the area of the block, and designs with
different areas may choose different wire load models.
- The wire load model also maps the estimated length of the net into the
resistance, capacitance, and the corresponding area overhead due to
routing. The average wire length within a block increases as the block size is
increased.
- Generally, a number of wire-load models are present in the Synopsys
technology library, each representing a particular size block of the logic.
These models define the capacitance, resistance, and area factor of the net.
- Typically a wire load model selection is based upon the chip area of the block.
However these WLM models can be modified or changed according to the
user’s requirement by the designers.
2.UNATENESS:
Unateness refers to the relationship between the input and output transitions
of a timing arc. It describes how the output of a cell changes in response to
changes in the input. There are three types of unateness:
1. Positive Unate: When the input transitions from low to high, the output
also transitions from low to high, and vice versa.
2. Negative Unate: When the input transitions from low to high, the output
transitions from high to low, and vice versa.
3. Non-Unate: The output transition depends on multiple inputs and is not
only determined by a single input transition.
 AND Gate: Positive Unate
 OR Gate: Positive Unate
 NAND Gate: Negative Unate
 NOR Gate: Negative Unate
 NOT Gate (Inverter): Negative Unate
 XOR Gate: Non-Unate
 XNOR Gate: Non-Unate

3.SLEW:
Slew refers to the rate of change of a signal's voltage over time. It is the transition
time it takes for a signal to switch from one voltage level to another, typically
from low to high (rise slew) or high to low (fall slew). Slew Rate, is typically
measured in Volts per nanosecond (V/ns) or Volts per microsecond (V/µs) or
similar units, depending on the speed of the transition. STA tool calculates Input
Transition time using Slew threshold values from the library.

(Input or Output)slew: Transition time from 10% to 90%

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