SEMINAR REPORT

ON

HISTORIC DEVELOPMENT OF VLSI FROM SSI TO ULSI

Submitted to
NMAM INSTITUTE OF TECHNOLOGY, NITTE
Off Campus Centre of Nitte (Deemed to be University)

In partial fulfillment of the requirements for the award of the

Degree of Bachelor of Engineering

in
Electrical & Electronics Engineering

by
Kishan Revankar
4NM21EE037

April 2025

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 ABSTRACT

The evolution of VLSI technology has redefined modern electronics, enabling exponential
The historic progression of Very Large Scale Integration (VLSI) technology from Small-
Scale Integration (SSI) to Ultra Large-Scale Integration (ULSI) represents one of the most
transformative journeys in modern engineering. Beginning with the invention of the first
integrated circuit by Jack Kilby in 1958, the semiconductor industry has witnessed
exponential growth governed by Moore’s Law, which predicted the doubling of transistors
every 18–24 months. This report meticulously documents this evolution, starting with SSI
chips of the 1960s containing mere tens of transistors, through the Medium-Scale
Integration (MSI) and Large-Scale Integration (LSI) eras of the 1970s, and into the VLSI
and ULSI domains that now pack billions of transistors onto a single chip.

Key technological milestones are explored, including the transition from bipolar junction
transistors to Complementary Metal-Oxide-Semiconductor (CMOS) technology, the
development of photolithography techniques enabling sub-micron feature sizes, and the
introduction of FinFET transistors to overcome leakage currents at nanoscale nodes. The
report also addresses critical challenges such as power dissipation, interconnect delays,
and quantum tunneling effects that emerge below the 10nm process node. Practical
applications spanning microprocessors, memory devices, and System-on-Chip (SoC)
designs are analyzed, demonstrating how VLSI advancements have enabled breakthroughs
in artificial intelligence, IoT, and high-performance computing.

Keywords: SSI, MSI, VLSI, ULSI, Moore’s Law, CMOS, FinFET, Photolithography,
Semiconductor Scaling

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 CONTENTS

Sl.No Title Page No

1. List of Figures 4
2. Introduction 5
3. Literature Review 6
4. Methodology 12
5. Results and Discussion 18
6. Conclusion 19
7. Reference 20

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 List of Figures

Figure 1. Comparison of process nodes from 10um to 3nm ................................................. 7

Figure 2. Comparison of emerging semiconductor materials ............................................... 9

Figure 3. Roadmap of semiconductor technology from 2025–2035.................................... 10

Figure 4. Comparative analysis ............................................................................................. 11

Figure 5. Evolution of chips from SSI to VLSI ................................................................... 12

Figure 6: MSI Design Flow .................................................................................................

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Figure 7. VLSI/ULSI Design flow ........................................................................................ 16

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 1. INTRODUCTION

The story of VLSI begins with the invention of the integrated circuit (IC) in 1958 by
Jack Kilby at Texas Instruments, a breakthrough that earned him the Nobel Prize in
Physics. Early ICs, classified as Small-Scale Integration (SSI), contained fewer than 10
transistors and were fabricated using germanium wafers. These primitive chips, such as
the TI SN502 logic gate, were prohibitively expensive and primarily used in military and
aerospace applications, including the Apollo Guidance Computer. The 1960s saw the
transition to silicon wafers, which offered superior thermal stability and lower costs,
paving the way for commercial adoption.

By the 1970s, Medium-Scale Integration (MSI) chips emerged, integrating hundreds of

transistors and enabling complex functions like arithmetic logic units (ALUs) and memory
registers. The introduction of Transistor-Transistor Logic (TTL) and Emitter-Coupled
Logic (ECL) families improved speed and power efficiency, though heat dissipation
remained a challenge. The real paradigm shift occurred with the advent of Large-Scale
Integration (LSI) in the late 1970s, epitomized by the Intel 4004 microprocessor (1971),
which packed 2,300 transistors onto a single die. This era also saw the rise of Computer-
Aided Design (CAD) tools, which automated layout processes and reduced human error.

The 1980s marked the dawn of Very Large-Scale Integration (VLSI), defined by chips
with over 100,000 transistors. The adoption of CMOS technology revolutionized the
industry by reducing power consumption by 90% compared to bipolar transistors.
Photolithography advancements enabled feature sizes to shrink below 1µm, while new
materials like polysilicon gates and tungsten interconnects improved performance. By the
1990s, VLSI had evolved into Ultra Large-Scale Integration (ULSI), with Intel’s
Pentium processors exceeding 3 million transistors. Today, Apple’s M1 chip integrates 16
billion transistors using 5nm technology, a testament to six decades of relentless
innovation.

This report will explore these developments in detail, analyzing the technical
challenges, economic drivers, and future prospects of VLSI technology.

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 2. LITERATURE REVIEW

2.1 SSI Era (1960s): The Dawn of Integration

The Small-Scale Integration (SSI) period (1960–1965) marked the first practical
implementation of integrated circuits. Early SSI chips like the Fairchild µLogic
series contained simple logic gates (NAND, NOR) with 4–10 bipolar junction transistors
(BJTs). These devices were fabricated using planar technology, invented by Jean Hoerni
in 1959, which allowed transistors to be built on a single silicon plane. A key limitation
was yield rates—only 10–20% of chips functioned due to contamination during
photolithography. Military applications dominated, with the Minuteman II missile
program being the largest consumer. The TI SN51 series (1961) exemplified SSI,
offering 5mW/gate power dissipation—a 10x improvement over discrete transistors.

2.2 MSI/LSI Transition (1970s): The Microprocessor Revolution

Medium-Scale Integration (MSI) chips (1966–1971) integrated 100–1,000 transistors,

enabling complex functions like 4-bit ALUs (e.g., Texas Instruments SN74181). The
transition to Large-Scale Integration (LSI) began with Intel’s 4004
microprocessor (1971), which packed 2,300 PMOS transistors at 10µm feature size. Two
breakthroughs enabled this:

1. Silicon Gate Technology (Federico Faggin, 1968): Replaced aluminum gates with
doped polysilicon, reducing threshold voltages.

2. DRAM Invention (Robert Dennard, 1968): 1-transistor memory cells replaced

magnetic core memory.

By 1975, LSI chips like the Motorola 6800 integrated 4,000 transistors using NMOS
technology, though power dissipation reached 1W/cm²—a critical thermal challenge.
Nano insulation material 1

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2.3 VLSI Breakthroughs (1980–2000): CMOS Dominance

The 1980s saw the rise of VLSI (100,000–1M transistors), driven by three innovations:

1. CMOS Adoption: Intel’s 80386 (1985) used 1.5µm CMOS, reducing power to
0.1mW/gate.

2. Stepper Lithography: Projection aligners enabled <1µm features (e.g., Intel 486 at
0.8µm).

3. CAD Tools: SPICE (1973) and VHDL (1987) automated verification.

The Pentium Pro (1995) exemplified VLSI’s maturity with 5.5M transistors at 0.35µm.
However, interconnect delays became critical—aluminum wires (ρ=2.8µΩ·cm) caused
RC delays exceeding clock periods. This led to copper interconnects (IBM, 1997) with
40% lower resistance.

2.4 ULSI Challenges (2000–Present): Nanoscale Frontiers

Below 22nm (2012), traditional planar FETs suffered leakage currents >100nA/µm.
Intel’s FinFET (2011) solved this with 3D gates:

• 22nm Ivy Bridge: 37% speed gain at 50% lower power.

• 5nm Nodes: TSMC’s N5 (2020) used EUV lithography with 171M

transistors/mm².

Fig1: Comparison of process nodes from 10um to 3nm

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2.5 The Rise of System-on-Chip (SoC) Designs (2000s–Present)
The transition to Ultra Large-Scale Integration (ULSI) enabled System-on-Chip
(SoC) designs, integrating CPUs, GPUs, memory, and peripherals onto a single die. A
landmark example is Apple’s A4 SoC (2010), fabricated using Samsung’s 45nm process,
which combined an ARM Cortex-A8 CPU, PowerVR GPU, and memory controller.
Key advancements in SoC development include:
• Heterogeneous Computing: Combining CPU, GPU, and NPU cores (e.g., Qualcomm
Snapdragon, Huawei Kirin).
• Advanced Packaging: 2.5D/3D IC stacking (e.g., AMD’s Zen 3 with TSMC’s
CoWoS).
• Low-Power Design: ARM’s big.LITTLE architecture (2012) for dynamic power
management
.
However, SoCs face challenges like thermal throttling and memory bandwidth
bottlenecks, leading to innovations such as High Bandwidth Memory (HBM) and silicon
interposers.

2.6 Beyond Silicon: Emerging Technologies

As silicon approaches physical limits, research focuses on post-CMOS technologies:

1. III-V Semiconductors (GaAs, InP):
o Higher electron mobility (5–10x silicon) but costly.
o Used in RF/mm-wave applications (e.g., 5G transceivers).
2. Carbon Nanotubes (CNTs):
o IBM’s 2019 CNT transistor demonstrated 5nm node compatibility.
o Challenges: Precise alignment, metallic vs. semiconducting CNT separation.
3. 2D Materials (Graphene, MoS₂):
o Atomic-layer thickness enables ultra-scaled FETs.
o Samsung’s 2021 study showed MoS₂ FETs with 10nm gate lengths.
4. Quantum Computing:
o Intel’s spin qubits (2018) and Google’s Sycamore (2019) represent early
milestones.

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Fig2: Comparison of emerging semiconductor materials

2.7. Economic and Environmental Impacts

The semiconductor industry’s growth has been accompanied by cost

escalation and sustainability challenges:
1. Fab Costs:
o A 3nm fab requires ~$20B (TSMC, 2022).
o Only 3 companies (TSMC, Samsung, Intel) can afford leading-edge nodes.
2. Environmental Concerns:
o E-Waste: 53M tonnes/year (UN, 2021), with chips as major contributors.
o Water Usage: TSMC consumes 150,000 tons/day (2023).
3. Geopolitical Factors:
o US-China trade wars over ASML’s EUV machines.
o India’s $10B semiconductor incentive plan (2023).

2.8 The Future of VLSI: Challenges and Opportunities

As the semiconductor industry approaches the 1nm node (expected by 2030), researchers are
confronting fundamental physical and economic barriers while exploring disruptive
innovations:
A. Fundamental Limitations
1. Quantum Tunneling:
o At sub-3nm nodes, gate oxides become thin enough (~5 atomic layers) for
electrons to tunnel through, increasing leakage currents.
o Potential solutions:
▪ High-κ Dielectrics (e.g., HfO₂ with EOT < 0.5nm)
▪ Negative Capacitance FETs (NCFETs) to reduce subthreshold swing
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 2. Interconnect Bottlenecks:
o Copper resistivity increases due to surface scattering at nanoscale dimensions.
o Alternatives:
▪ Cobalt Interconnects (Intel’s 10nm, 2019)
▪ Airgap Dielectrics (IBM’s 7nm, 2015)

3. Thermal Dissipation:
o Power densities exceed 100W/cm² in modern CPUs (vs. 10W/cm² in 2000).
o Advanced cooling solutions:
▪ Microfluidic Channels (DARPA ICECool program)
▪ Diamond Substrates (thermal conductivity 5× silicon)

B. Next-Generation Computing Paradigms

1. Neuromorphic Computing
o Intel's Loihi 2 (2021): 1M artificial neurons with asynchronous spiking
o Applications: Edge AI with 1000× lower power than GPUs
2. Chiplet-Based Designs
o AMD's 3D V-Cache (2022): 192MB L3 cache stacked using TSVs
o UCIe standard (2022) for heterogeneous chiplet integration
3. Optical Interconnects
o Lightmatter's photonic AI accelerator (2023): 10Tbps/mm² bandwidth
o Challenges: CMOS-compatible silicon photonics integration

Fig3: Roadmap of semiconductor technology from 2025–2035

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C. Sustainable Semiconductor Manufacturing

1. Green Fab Initiatives

o TSMC's 2050 net-zero commitment (RE100 renewable energy)
o ASML's EUV tools with 30% lower energy consumption
2. Circular Economy Approaches
o Silicon wafer recycling (90% recovery rate)
o Lead-free solder and halogen-free packaging
3. Alternative Computing Architectures
o Approximate computing for error-tolerant applications
o Reversible computing to minimize entropy generation

Fig4: Comparative analysis of future computing technologies

Technology Energy/Op (J) Speed Maturity Best Application

CMOS (3nm) 1e-18 5GHz Production General computing

Neuromorphic 1e-15 1MHz Prototype Pattern recognition

Photonic 1e-16 50GHz Research Optical networking

Quantum (CMOS) 1e-12 N/A Lab Cryptography

This extended analysis demonstrates that while traditional scaling faces existential challenges,
the VLSI field is evolving through heterogeneous integration, new computing paradigms,
and sustainable manufacturing - ensuring continued progress even beyond Moore's Law.
The next decade will likely see a coexistence of advanced CMOS with specialized
accelerators, marking a new era of "More than Moore" innovation

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 3. METHODOLOGY
3.1. SSI Design flow :

SSI refers to the integration of a small number (typically fewer than 10) of logic
gates or components into a single chip. Early ICs were SSI, and the design
process for these chips was relatively simple compared to modern designs.

1. Design Specification: Define the functionality and performance

requirements (e.g., number of gates, type of logic).
2. Logic Design: Define the basic logic gates and circuits (AND, OR, NOT
gates) required for the design.
3. Schematic Design: Create a schematic diagram of the logic gates and their
connections.
4. Simulation: Perform simulation (using basic tools) to check the logical
behavior of the design.
5. Fabrication: Using standard CMOS or bipolar technology, fabricate the
chip on a silicon wafer.
6. Testing: Verify the chip’s functionality using basic testing equipment (e.g.,
logic analyzers, oscilloscopes).

Characteristics of SSI:

1. Small number of gates per chip.

2. Simple design and layout process.
3. Limited in functionality and complexity.

Fig5: Evolution of chips from SSI to VLSI

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3.2. MSI Design flow :

MSI refers to the integration of hundreds of gates or logic functions into a

single chip. With MSI technology, more complex circuits, such as decoders,
multiplexers, and small arithmetic units, could be implemented.

1. Design Specification: Define higher-level functions (e.g., multiplexers,

registers, decoders).
2. High-Level Design: Choose the type of components needed (e.g., adders,
flip-flops) and their interconnections.
3. Logic Design: Design individual functional blocks like counters, registers,
etc.
4. Schematic and RTL Design: Use hardware description languages (HDLs)
like VHDL or Verilog for RTL (Register Transfer Level) design.
Schematic capture tools also become useful here.
5. Simulation: Perform simulations at the gate level to verify functionality.
6. Physical Design: Start considering layout constraints, such as area and
power consumption. Use tools to place and route components on the chip.
7. Fabrication: Fabricate using the selected semiconductor process.
8. Testing: Functional testing and performance evaluation.

Characteristics of MSI:

1. Chips integrate hundreds of logic gates.

2. Capability for more complex functions.
3. Introduces the use of RTL design and simulation tools.

Fig6: MSI Design Flow

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3.3. LSI Design flow

LSI involves integrating thousands of gates into a single chip. LSI allows for
the creation of entire functional blocks such as microprocessors, memory
chips, and controllers on a single silicon chip.

1. Design Specification: Define the overall functionality of the integrated

circuit (e.g., microprocessor design, memory).
2. Architectural Design: Define the architecture of the chip (e.g., 8-bit, 16-
bit processors).
3. RTL Design: Use HDLs (VHDL or Verilog) to describe the logic at a
higher level.
4. Simulation: Extensive functional and timing simulation to ensure the
design meets requirements.
5. Synthesis: Use synthesis tools to convert RTL code into gate-level
representations.
6. Place and Route: Use EDA (Electronic Design Automation) tools to place
and route the gates to fit the design within the chip.
7. Layout Design: Focus on the physical layer, ensuring that the design fits
within the chip’s constraints and performs at the desired speed.
8. Fabrication: Use CMOS or BiCMOS technologies to fabricate the chip.
9. Testing: Extensive functional testing, including boundary scan and
performance verification.

Characteristics of LSI:

1. Chips integrate thousands of gates.

2. Higher complexity and more sophisticated design methodologies.
3. Early microprocessors and memory ICs used LSI.

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3.4. VLSI Design flow
Generally, the design process of a VLSI chip involves three stages namely the
(i) behavioural, (ii) logic circuit and (iii) layout representations. At each of this
stage, veri cation is to be per‐ formed at the end before proceeding to the
next. Hence, it is common to have repetitions and iterations in the processes .

3.4.1. Behavioural representation

Behavioural representation is the first step of the entire VLSI design
flow. At this stage, it is important to specify the functionalities of the
device and how it is going to communicate with the exterior. The design
architecture is to be drawn panned out. A hardware description language
(HDL) such as Verilog HDL or VHDL is used to define the behaviour of
the device.

3.4.2. Logic circuit representation

After the HDL codes are successfully simulated, functional blocks from
standard cell libraries are used to synthesize the behavioural
representation of the design into logic circuit represen‐tation. Once the
design is verified, the gate level netlist is generated. The netlist is
necessary in order to develop the layout of the design.

3.4.3. Layout representation

At the final stage, the physical layout of the design is created. The
process starts with poor planning which defines the core and routing
areas of the chip. In order to optimize the design, the building blocks are
arranged and orientated at their best locations. This process is known as
placement. Once this is completed, a routing process is performed
to interconnect the building blocks.

3.4.4. IC fabrication
To fabricate the chip, the layout is sent to a fab or a foundry. In a fab, a
single‐crystal semiconductor ingot is first grown. Wafers are then
sliced from the ingot. The layout is printed onto the dice in each
wafer. In the initial step of chip fabrication, the active regions or wells

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 for the NMOS and PMOS transistors are first formed at the substrate.
In order to separate the transistors, an oxide layer is subsequently
deposited in between each neighbouring well.

3.4.5. IC packaging
To protect the chip from harsh external environment (e.g. being
exposed to UV light or moisture or being scratched), it is essential to
encapsulate the chip in a package. The three most commonly used
techniques for packaging are (i) wirebonding, (ii) flip‐chip and (iii)
tapeautomated bonding (TAB) . Once the chip is carefully packaged,
it is then ready to be released to the market.

Characteristics of VLSI:

1. Chips integrate millions of gates.

2. Complex systems like processors, DSPs, and custom logic.
3. Advanced design tools and techniques for optimization.

Fig7: VLSI/ULSI Design Flow

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3.5. ULSI Design flow

ULSI refers to the integration of billions of transistors onto a single chip. ULSI
technology is used for the most complex ICs like modern CPUs, GPUs, and
memory devices. ULSI is the forefront of current semiconductor technology,
and its design challenges are primarily related to power consumption, heat
dissipation, and signal integrity.

1. Design Specification: Highly detailed and extensive specification to

accommodate billions of transistors.
2. System-Level Design: Advanced system-level design and architectural
planning for multi-core processors, GPUs, and memory systems.
3. RTL Design and High-Level Abstraction: Use sophisticated HDLs (e.g.,
Verilog, VHDL) with abstraction layers for system design.
4. Simulation and Verification: Extensive functional and performance
simulations to meet exacting performance requirements (e.g., 3D chip
stacking, multi-threading).
5. Synthesis and Optimization: Use advanced synthesis tools for the complex
mapping of RTL into gates and logic elements.
6. Power and Thermal Analysis: Perform detailed power analysis and
optimization to ensure the chip meets low power and thermal requirements.
7. Place and Route: Use cutting-edge EDA tools for highly optimized place
and route processes, considering multi-level interconnects, clock domains,
and signal integrity.
8. Design for Manufacturing: Ensure that the design is manufacturable at the
sub-nanometer process nodes (e.g., 7nm, 5nm).
9. Fabrication: Fabrication using state-of-the-art semiconductor
manufacturing processes (often in collaboration with leading foundries).
10. Testing: Post-fabrication testing at multiple levels: functional testing,
performance testing, reliability testing, and yield analysis.

Characteristics of ULSI:

1. Chips integrate billions of transistors.

2. Extremely high complexity, with focus on power, thermal management,
and signal integrity.
3. Used in the most advanced processors and systems-on-chip

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 4.RESULTS AND DISCUSSION

4.1 SSI to MSI (1960s–1970s):

o Transistors: Fewer than 10 (SSI) → 100–1,000 (MSI).

o Impact: Enabled calculators and early computers.
o Limitation: High power use and manual design.

4.2 LSI to VLSI (1980s–1990s):

o Transistors: 1,000–10,000 (LSI) → 1 million (VLSI).

o Breakthroughs: Intel 8086, CMOS chips (lower power).
o Challenge: Wires slowed signals (interconnect delays).

4.3 ULSI (2000s–Now):

o Transistors: Over 1 billion (e.g., Apple A15).

o Tech: FinFETs, 3D chips, EUV lithography.
o Problems: Overheating, tiny wire delays, high costs.

Why It Matters:

• Physics: Confirms/refutes classical device models, pushing quantum-aware design.

• Economics: Rising costs are reshaping industry structure and competition.
• Society: Forces hard choices about energy use, accessibility, and specialization.
• Innovation: Drives interdisciplinary solutions across materials, devices, and systems.
• Advances Medical Tech - Miniaturization enables implantable devices and portable
diagnostics.
• Reduces Tech Costs - Mass production of integrated circuits democratized computing
access.
• Boosts Energy Efficiency - Each node shrink improves performance-per-watt for
green computing.
• Enhances Security - Hardware-level security features become feasible with transistor
density.
• Enables 5G/6G Networks - High-frequency RF chips rely on advanced VLSI
techniques.
• Supports Space Tech - Radiation-hardened ICs enable spacecraft and satellite systems.
• Drives Automotive Innovation - Powers ADAS and autonomous vehicle technologies.

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 6.CONCLUSION

The historic development of VLSI technology from SSI to ULSI represents one of the most
remarkable engineering achievements of the modern era. Over six decades, we have witnessed
exponential growth in computing power, enabled by relentless transistor scaling, innovative
device architectures, and revolutionary fabrication techniques. From the first integrated
circuits with just a handful of components to today's chips containing billions of transistors,
this journey has fundamentally transformed every aspect of our technological landscape. The
semiconductor industry's ability to consistently deliver smaller, faster, and more energy-
efficient devices has been the foundation for the digital revolution, powering everything from
personal computers and smartphones to artificial intelligence and cloud computing.

Looking ahead, the future of VLSI technology presents both challenges and opportunities.
While traditional scaling approaches are reaching fundamental physical limits, new paradigms
such as heterogeneous integration, advanced packaging, and novel computing architectures
are emerging to sustain progress. The transition to post-Moore technologies - including 3D
ICs, photonic interconnects, and quantum-inspired designs - promises to open new frontiers in
performance and efficiency. Moreover, the lessons learned from VLSI's evolution will
continue to guide innovation, emphasizing the importance of interdisciplinary collaboration
between device physicists, materials scientists, circuit designers, and system architects. As we
stand at this technological inflection point, the semiconductor industry remains poised to drive
the next wave of computing breakthroughs that will shape our digital future for decades to
come.

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 8.REFERENCES

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2. Meindl, J.D., "Low-Power Microelectronics: Retrospect and Prospect," Proceedings of the

IEEE, 1995.

3. Bohr, M., "The Evolution of Scaling from the Homogeneous Era to the Heterogeneous Era,"
IEEE IEDM, 2012.

4. ITRS, "International Technology Roadmap for Semiconductors," 2013.

5. Dennard, R.H., "Design of Ion-Implanted MOSFETs with Very Small Physical

Dimensions," IEEE Journal of Solid-State Circuits, vol. 9, no. 5, pp. 256–268, 1974.

6. Kim, N.S. et al., "Leakage Current: Moore’s Law Meets Static Power," IEEE Computer
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7. Noyce, R., "Microelectronics," Scientific American, 1977.

8. Huff, H.R., "High Dielectric Constant Materials for CMOS Applications," Springer, 2005.

9. Frank, D.J., "Power-Constrained CMOS Scaling Limits," IBM Journal of Research and
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10. Waldrop, M.M., "The Chips Are Down for Moore’s Law," Nature, 2016.

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