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20. EEE 3103_Finite State Machines

This document covers Chapter 5 of a course on Digital Electronics, focusing on Synchronous Sequential Logic and the analysis of clocked sequential circuits, specifically Mealy and Moore models of Finite State Machines (FSM). It outlines the steps for analyzing clocked sequential circuits, including state equations, state tables, and state diagrams, providing examples and exercises for practical application. The document is prepared by Baizeed Ahmed Bhuiyan from Ahsanullah University of Science and Technology.

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6 views

20. EEE 3103_Finite State Machines

This document covers Chapter 5 of a course on Digital Electronics, focusing on Synchronous Sequential Logic and the analysis of clocked sequential circuits, specifically Mealy and Moore models of Finite State Machines (FSM). It outlines the steps for analyzing clocked sequential circuits, including state equations, state tables, and state diagrams, providing examples and exercises for practical application. The document is prepared by Baizeed Ahmed Bhuiyan from Ahsanullah University of Science and Technology.

Uploaded by

mahmudhasansami
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EEE 3103: Digital Electronics I

Chapter-5: Synchronous Sequential Logic


Analysis of Clocked Sequential Circuits (FSM)

Reference: Digital Design by M. Morris Mano & Michael D. Ciletti [5th Edition]

Prepared by-
Baizeed Ahmed Bhuiyan
Lecturer (Grade-I)
Department of Electrical and Electronic Engineering
Ahsanullah University of Science and Technology
❑ Mealy and Moore Models of Finite State Machines
The most general model of a sequential circuit has inputs, outputs, and
internal states. It is customary to distinguish between two models of
sequential circuits: the Mealy model and the Moore model. Both are
shown in Fig. 5.21 . They differ only in the way the output is generated.

➢ In the Mealy model, the output is a function of both the present state
and the input.
➢ In the Moore model, the output is a function of only the present state.

A circuit may have both types of outputs. The two models of a


sequential circuit are commonly referred to as a Finite State Machine,
abbreviated FSM. The Mealy model of a sequential circuit is referred to
as a Mealy FSM or Mealy machine. The Moore model is referred to as a
Moore FSM or Moore machine.
❑ ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS
The analysis of a sequential circuit consists of obtaining a table or a
diagram for the time sequence of inputs, outputs, and internal states. It
is also possible to write Boolean expressions that describe the behavior
of the sequential circuit. These expressions must include the necessary
time sequence, either directly or indirectly.

A logic diagram is recognized as a clocked sequential circuit if it


includes flip-flops with clock inputs. The flip-flops may be of any type,
and the logic diagram may or may not include combinational logic
gates.

Consider the sequential circuit shown in Fig. 5.15 . The circuit presented
previously in Fig. 5.15 is an example of a Mealy machine. Output y is a
function of both input x and the present state of A and B .
➢ Step-1: State Equations
The behavior of a clocked sequential circuit can be described algebraically by means of state
equations. A state equation (also called a transition equation ) specifies the next state as a
function of the present state and inputs. The circuit in figure-5.15 consists of two D flip-flops
A and B, an input x and an output y . Since the D input of a flip-flop determines the value of
the next state (i.e., the state reached after the clock transition) it is possible to write a set of
state equations for the circuit:
A(t + 1) = A(t)x(t) + B(t)x(t)
B(t + 1) = A’(t)x(t)
A state equation is an algebraic expression that specifies the condition for a flip-flop state
transition. The left side of the equation, with (t + 1), denotes the next state of the flip-flop one
clock edge later. The right side of the equation is a Boolean expression that specifies the
present state and input conditions that make the next state equal to 1. Since all the variables
in the Boolean expressions are a function of the present state, we can omit the designation (t)
after each variable for convenience and can express the state equations in the more compact
form:
A(t + 1) = Ax+ Bx
B(t + 1) = A’x
The Boolean expressions for the state equations can be derived directly from the gates that
form the combinational circuit part of the sequential circuit, since the D values of the
combinational circuit determine the next state. Similarly, the present-state value of the
output can be expressed algebraically as
y(t) = [A(t) + B(t)]x’(t)
By removing the symbol (t) for the present state, we obtain the output Boolean equation:
y = (A + B)x’

➢ Step-2: State Table


The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state
table (sometimes called a transition table). The state table for the circuit of Fig. 5.15 is
shown in Table 5.2. The table consists of four sections labeled present state, input, next
state, and output. The present-state section shows the states of flip-flops A and B at any
given time t. The input section gives a value of x for each possible present state. The next-
state section shows the states of the flip-flops one clock cycle later, at time t + 1. The output
section gives the value of y at time t for each present state and input condition.
In general, a sequential circuit with m flipflops and n inputs needs 2m+n rows in the
state table
➢ Step-3: State Diagram
The information available in a state table can be represented graphically in the form of
a state diagram. In this type of diagram, a state is represented by a circle, and the
(clock-triggered) transitions between states are indicated by directed lines connecting
the circles. The state diagram of the sequential circuit of Fig. 5.15 is shown in Fig. 5.16 .
The state diagram provides the same information as the state table and is obtained
directly from Table 5.2 or Table 5.3 . The binary number inside each circle identifies the
state of the flip-flops. The directed lines are labeled with two binary numbers
separated by a slash. The input value during the present state is labeled first, and the
number after the slash gives the output during the present state with the given input.
It is important to remember that the bit value listed for the output along the directed
line occurs during the present state and with the indicated input, and has nothing to
do with the transition to the next state. For example, the directed line from state 00 to
01 is labeled 1/0, meaning that when the sequential circuit is in the present state 00
and the input is 1, the output is 0. After the next clock cycle, the circuit goes to the
next state, 01. If the input changes to 0, then the output becomes 1, but if the input
remains at 1, the output stays at 0.
➢ Exercise Problem
➢ Exercise Problem
5.19 A sequential circuit has three flip-flops A, B, C ; one input x_in ; and one output
y_out. The state diagram is shown in Fig. P5.19. The circuit is to be designed by
treating the unused states as don’t-care conditions. Use D flip-flops in the design.
Design Sequence:
State table from State
Diagram → State
Equations from the table by
K-map → Circuit Diagram
From the Equations, draw the circuit diagram.

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