Received: 17 December 2019

| Revised: 30 August 2020

| Accepted: 3 November 2020

DOI: 10.4218/etrij.2019-0556

ORIGINAL ARTICLE

An efficient reliability estimation method for CNTFET-based

logic circuits

Hadi Jahanirad | Mostafa Hosseini

Department of Electrical Engineering,

University of Kurdistan, Sanandaj, Iran
Carbon nanotube field-effect transistors (CNTFETs) have been widely studied
as a promising technology to be included in post-complementary metal-oxide-
Correspondence semiconductor integrated circuits. Despite significant advantages in terms of delay
Hadi Jahanirad, Department of Electrical
Engineering, University of Kurdistan, and power dissipation, the fabrication process for CNTFETs is plagued by fault oc-
Sanandaj, Iran. currences. Therefore, developing a fast and accurate method for estimating the reli-
Email: [email protected]
ability of CNTFET-based digital circuits was the main goal of this study. In the
proposed method, effects related to faults that occur in a gate's transistors are first
represented as a probability transfer matrix. Next, the target circuit's graph is tra-
versed in topological order and the reliabilities of the circuit's gates are computed.
The accuracy of this method (less than 3% reliability estimation error) was veri-
fied through various simulations on the ISCAS 85 benchmark circuits. The proposed
method outperforms previous methods in terms of both accuracy and computational
complexity.

KEYWORDS
CNTFETs, gate-level circuit design, reliability estimation algorithms, transistor-level design

1 | IN T RO D U C T ION promising alternatives to MOSFETs, have some excellent

advantages (eg, near-ballistic transport properties, high car-
The carbon nanotube field-effect transistor (CNTFET) is rier mobility (103 to 104 cm2/V⋅s), and easy integration of
one of the most promising transistor types that can replace high-k dielectric materials) [8–10]. Based on these proper-
metal-oxide-silicon field-effect transistors (MOSFETs) in ties, CNTFET-based ICs exhibit significant advantages in
future digital integrated circuits (ICs) [1,2]. Since the in- terms of power consumption and delay [11–15].
troduction of complementary metal-oxide-semiconductor CNTFET-based implementations of various digital mod-
(CMOS) technology, the downscaling of MOSFETs has been ules, such as inverters and NAND, NOR, and SRAM cells,
pursued continuously to keep pace with Moore's law [3,4]. In have been reported in previous studies [16–19].
sub-micron CMOS technology (<100 nm transistor channel One important challenge in CNTFET-based ICs is re-
length), quantum mechanical effects such as electron tunnel- liability. With progressive downscaling, the control of de-
ing through channels and thin insulator films have become vice features (eg, CNT diameter or the alignment of CNTs)
sources of some undesirable phenomena [5–7]. Increased becomes increasingly complex. This results increased
power dissipation, defect rates, and significant process vari- transistor defect rates, as well as the production of faulty
ations represent significant barriers to achieving enhanced gates and IC reliability degradation. Several studies have
performance using sub-32 nm technologies. CNTFETs, as focused on probabilistically modeling the defects generated
This is an Open Access article distributed under the term of Korea Open Government License (KOGL) Type 4: Source Indication + Commercial Use Prohibition + Change
Prohibition (http://www.kogl.or.kr/info/licenseTypeEn.do).
1225-6463/$ © 2021 ETRI

ETRI Journal. 2021;0(0):1–18. wileyonlinelibrary.com/journal/etrij | 1

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| JAHANIRAD AND HOSSEINI

in CNTFETs (eg, open and short defects) [20–24]. Based The main contributions of this paper can be summarized
on these models, the failure probabilities of various gates as follows. First, we develop a reliability evaluator for combi-
can be extracted. If the error probabilities of a circuit's national logic circuits. Second, we derive gate failure proba-
gates are determined, then the circuit's reliability can be bilities using transistor-level topology. Third, we compare the
analyzed using conventional gate-level estimators. Multi- reliabilities of various design methods for CNTFET-based
valued logic must be handled properly to apply conven- primitive gates.
tional reliability evaluators to CNTFET-based ICs [25,26]. This remainder of this paper is organized as follows.
For example, when the pull-up and pull-down networks in CNTFET-based gate failure modeling is reviewed in
a logic gate turn off (or on) simultaneously based on fault Section 2. In Section 3, the proposed method for the reli-
occurrence, the output state will be neither “0” nor “1.” ability evaluation of logic gates is described, followed by
Instead, a “FLOAT” (or “Tri-STATE”) state will be gener- a description of the reliability evaluation flow for combi-
ated. In this paper, we propose a reliability evaluator based national logic circuits in Section 4. Simulation results are
on a probability transfer matrix (PTM). In this method, four presented in Section 5 and our conclusions are summarized
states (“0,” “1,” “Tri-STATE,” and “FLOAT”) are defined in Section 6.
for each node in a circuit and the transition probabilities
among these states are computed and propagated by tra-
versing the circuit's graph. 2 | CNTFET- BASED GATE
The reliability analysis of CNTFET-based logic cir- FAILURE M ODELING
cuits has been investigated in previous studies. In [26],
a pseudo-complementary CNTFET-based multi-valued Since the invention of CNTFETs in 1998, based on the
logic model was proposed and a stochastic approach was fault-prone nature of these devices, many researchers have
applied for reliability computation. In this method, each studied their reliability [29]. Depending on its chirality, a
gate is replaced with a multiplexer in which the selectors CNT can be a metal or semiconductor. The former type of
connect to the gate's inputs and the multiplexer's inputs CNT is the main reason for fault generation in CNTFETs
contain random sequences including three symbols of “0,” [23]. Generally, there are two main fault types in CNTFETs.
“2,” and “1,” which represent the logic states of “0,” “1,” The first is a short fault, which occurs when a metallic CNT
and “Tri-STATE,” respectively. The execution time of this grows between the source and drain terminals. The second
method is very high because of its simulation-based na- is an open fault, which occurs when no CNTs remain be-
ture. Another probabilistic approach can be found in [27], tween the source and drain terminals following the chemi-
where gate output failures were divided into three cases: a cal removal of metallic CNTs [20]. Figure 1 presents three
gate's inputs are faulty but the gate is fault-free, a gate is possible cases that can occur during the CNTFET synthe-
faulty but gate's inputs are fault-free, and both a gate and sis process. The CNTFETs in Figure 1A and 1B are func-
its inputs are faulty simultaneously. This method is very tional, while those in Figure 1C and 1D contain short and
fast, but it encounters two major problems. First, CNTFET open failures, respectively. Variations in CNT diameter and
fault modeling is inaccurate because it is assumed that the density result in delays and power consumption variation.
CNTFET always turns on when the “Tri-STATE” signal is Additionally, the misalignment of CNTs can lead to incorrect
applied to its gate terminal. In a more realistic model, the functionality [30].
transistor may turn on or turn off according to its chirality. Several statistical failure analyses have been performed
The second problem is related to reconvergent fan-out sig- on CNTFETs [20–24]. In these studies, the distributions
nals, which are a source of inaccuracy in this method (ad- of CNT counts and CNT spacing in a CNTFET were de-
ditional descriptions can be found in Section 4). Sirinivasu fined (typically as geometric probability density func-
and Sridharan [28] developed a PTM-based approach for tions). Next, based on these distributions, the probabilities
CNTFET-based circuit reliability analysis. Based on open of fault occurrences (open and short faults) were derived
and short faults, an error probability matrix is derived for for CNTFETs containing N CNTs [31,32]. A similar ap-
each circuit gate. In this matrix, for every input vector proach was adopted in [20], but a binomial distribution was
(matrix row), the probabilities of generating of “0,” “1,” applied to the CNT counts.
and “Tri-STATE” states in a gate's output are computed. One major barrier to incorporating CNTFETs in very-
The matrix is then reduced to a conventional matrix with- large-scale integration (VLSI) chips is a high metallic
out “Tri-STATE” entries. Finally, the conventional PTM CNT growth rate (30%) during the synthesis process [22].
method is applied. However, this approach cannot handle Various metallic CNT removal methods can be applied
reconvergent fan-outs properly and the removal of “Tri- to reduce this ratio, but these methods may inadvertently
STATE” entries in the PTM matrix results in undesirable remove some semiconductor CNTs [32,33]. To com-
effects. pute the short and open failure probabilities (PS and PO,
JAHANIRAD AND HOSSEINI
| 3

F I G U R E 1 Various structures of
CNTFETs. (A) Functional CNTFET
Drain
containing four CNTs, (B) functional Drain

CNTFET containing one CNT, (C)

CNTFET containing metallic CNTs (short Gate
Gate
fault), (D) CNTFET containing no CNTs
(open fault)
Source
Source

(A) (C)

Drain Drain

Gate Gate

Source Source

(B) (D)

Metallic CNT Semi-Cond CNT

respectively) of a CNTFET, we adopt the analytical model D

that was developed in [26]. In this model, for a CNTFET
containing NCNT CNTs, PS and PO can be computed ac- G

cording to (1) and (4), respectively.

k
( ) S
k k k
(1)
∑
k − k1
PS (k) = (1 − pmr1 )pm1 (1 − pm ) .
k1 FIGURE 2 ACCNT row circuitry
k1 = 1

2 NCNT
( )
∑ 2NCNT 1 (2) CNTFETs. One promising technique was proposed in [24] to
PS = ( )2NCNT PS (k) .
k=1 k 2 improve the reliability of CNTFETs to an acceptable level. In
a so-called asymmetrically correlated CNT (ACCNT), a row
containing c transistors with series wiring (Figure 2) is fab-
k
( )
k k − k1 k1 k
(3)
∑
PO (k) = (psr pmr )pm1 (1 − pm )k − k1 . ricated. In this configuration, a short fault is generated when
k1
k1 = 1
all transistors in the row are shorted, meaning the short fault
probability of a row can be calculated according to (6).
2 NCNT
( )
2NCNT 1 (4)
∑
PO = ( )2NCNT PO (k) . PS - ACCNT = (PS - CNTFET )c . (6)
k=1 k 2

In contrast, an open fault only requires one open CNTFET.

In these equations, Pm is the probability of a CNT being This statement is the complement of the statement “all
metallic and the probabilities of metallic and semiconductor CNTFETs are not open.” Therefore, the average open fault
CNTs being removed during the removal process are denoted probability of a row in an ACCNT can be computed accord-
as Pmr and Psr, respectively. Ultimately, the average probabil- ing to (7).
ity of fault occurence in the CNTFET (PF ) would be calcu-
PO - ACCNT = 1 − (1 − PO - CNTFET )c . (7)
lated according to (5).

PF = PS + PO . (5)
Simulation results reveal a dramatic reduction in the
gate short fault probability for ACCNTs, but some aspects
One major problem encountered by CNTFET-based of ACCNTs, such as the area overhead and additional power
VLSI chips is the high open and short fault probabilities of consumption, reduce efficiency [24].
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| JAHANIRAD AND HOSSEINI

3 | GAT E RE L IA B IL IT Y a gate's PTM construction, the transition probability to the

EVA LUAT IO N “FLOAT” state is divided by three and added to the probabil-
ities of three other states (“0,” “1,” and “Tri-STATE”).
Two main factors should be determined during the reliabil- Before continuing with our analysis, we define the con-
ity evaluation of a logic gate. The first one is how open and ditions under which a CNTFET can act as a closed switch
short faults in a gate's CNTFETs can generate faulty values (turning on) or open switch (turning off). In the following dis-
in that gate's outputs. The second is how faulty values gen- cussion, we only consider an n-type CNTFET (N-CNTFET)
erated by other gates can propagate to the outputs of the because a p-type CNTFET (P-CNTFET) can be treated as a
target gate. dual-n-type transistor. Suppose that the gate terminal of an N-
In this section, we present an effective approach to an- CNTFET is connected to the logic “1.” This transistor turns
alyzing these factors. First, the effects of CNTFET-related on when it is in normal mode or suffers from a short fault
faults are represented using a PTM. Next, the transformation (N/S). In contrast, an open fault (O) would turn this transistor
probabilities from one state to the other states in the gate's in- off. If the gate terminal state becomes “0,” then an n-type
puts are represented by a signal transition probability matrix CNTFET only turns on when the transistor contains a short
(STPM). Based on a joint probability input matrix (JPIM) fault (S) and turns off when the transistor is fault-free or con-
and the gate's PTM, the STMP of the gate's output is com- tains an open fault (N/O).
puted. The reliability of the gate is calculated by summing The case of applying the “Tri-STATE” logic to a
the probabilities of transitions from state “0” to state “0” and CNTFET’s gate terminal requires additional effort. First, it
from state “1” to state “1” in the STPM. must be determined whether or not the “Tri-STATE” voltage
level (VTri) can turn on the transistor. This depends on the Vth
value of the transistor and the value of VTri. If VTri < Vth, then
3.1 | Gate PTM computation the “Tri-STATE” turns off the N-CNTFET. Otherwise, the
transistor turns on the N-CNTFET. As indicated in (8), var-
For an arbitrary gate designed based on complementary, ra- ious factors determine Vth, where a = 2.49 Å is the distance
tioed, and dynamic methodologies, there is at least one path between carbon atoms, Vπ = 3.033 eV is the carbon π-π bond
toward Vdd (the pull-up network (PUN)) and at least one energy, e is the electron charge, and dCNT is the CNT diameter
path toward GND (the pull-down network (PDN)). In some
design methodologies such as pass-transistors or transmis-
√
3aV𝜋
Vth = . (8)
sion gate design styles, the PUN and PDN are determined 3edCNT
by the input states. In a fault-free gate, when the “1” or “0”
states are applied to the inputs, only one of the PUN or PDN √
turns on while the other turns off, meaning the gate's out- 3a0 √ 2 (9)
dCNT = n + m2 + nm .
puts can only take on binary values (“1” or “0”). In contrast, 𝜋
based on probable open or short fault occurrence, the PUN
and PDN may turn on (“Tri-STATE”) or off (“FLOAT”), Among these parameters, only dCNT is variable and is de-
simultaneously. fined by the CNT chirality vector (m, n) according to (9).
To generate the “0” state at the gate's output, at least one For example, two CNTFETs with chirality vectors (19, 0) and
path between the output and GND should turn on and all (13, 0) have threshold voltages equal to 0.293 and 0.428 V,
paths from Vdd to the output should turn off. To generate the respectively.
“1” state, the inverse conditions must be satisfied. Regarding A logic gate is designed such that the drive strengths of
the “Tri-STATE” state, there should be at least one turned on the PUN and PDN are equal. Therefore, if all the paths in
path toward Vdd and at least one turned on path toward GND. the PUN and PDN turn on simultaneously, then the output
For the “FLOAT” state, all paths to Vdd and GND should be voltage should be Vdd / 2. If there are some paths that turn
turned off simultaneously. off in the PUN and PDN, then the value of VTri will devi-
To compute the PTM, we should determine the proba- ate from Vdd / 2. For example, suppose that only one path in
bilities of the “0,” “1,” “Tri-STATE,” and “FLOAT” states the PUN is turned off while all paths in the PDN are turned
for each input vector. For a gate with Ninp inputs, the size of on. This situation leads to greater drive strength in the PDN
the PTM matrix is 3Ninp × 3. For each input vector (an input compared to the PUN, so the generated voltage in the gate's
can take on “0,” “1,” and “Tri-STATE” states), the output is output would be Vdd / 2 − ΔV. In this expression, ΔV is a pos-
a “0,” “1,” or “Tri-STATE” state with varying probabilities. itive voltage that is related to the difference between the PUN
The “FLOAT” state is included in the PTM as follows. When and PDN drive strengths. When additional paths are turned
a node transforms from a state A into the “FLOAT” state, the off in the PUN, the value of ΔV increases, resulting in a lower
logic of that node remains in state A [25]. Consequently, for VTri value. The precise value of VTri should be determined via
JAHANIRAD AND HOSSEINI
| 5

HSPICE simulations of various situations that can occur in similar Vth values because similar CNTs contribute to their
the PUN and PDN. structures [24].
In our method, we simply consider a single “Tri-STATE” To activate (turn on) a path from the output to GND or
state in the PTM that represents all generated voltage lev- from the output to Vdd, all transistors in the path should turn
els. This is a source of error in our method because when on. Unlike in the pass-transistor and transmission gate de-
we apply the “Tri-STATE” to the input of a gate, we should signs, the input voltage is applied to the CNTFET’s gate ter-
know which voltage level to consider for VTri. minal. In this case, the probability of turning on path i can be
Handling this problem in the proposed method is accom- calculated according to
plished as follows. Considering the various scenarios that can
Npath
result in the generation of a “Tri-STATE” in a gate's output,
(11)
∏
it is possible that VTri will take on a value in the range of 0 V Ppath - on (i) = Ptr - on (tr) .
tr = 1
to Vdd. We assume that this value follows a uniform distri-
bution. Consequently, when the “Tri-STATE” is applied to Based on the state of the input connected to the CNTFET’s
the input of a gate, meaning the gate terminals of the related gate terminal, Ptr-on(tr) may be PS (in case S) or 1 − Po (in
CNTFETs are connected to VTri, we should consider all pos- case N/S). To deactivate (turn off) a path, at least one of the
sible cases. Suppose that the gate terminals of four CNTFETs path's transistors must be turned off. Therefore, we use (12)
(two P-CNTFETs from the PUN and two N-CNTFETs from to calculate the path deactivation probability.
the PDN) are connected to VTri. Then, we divide the [0, Vdd]
Ppath - off (i) = 1 − Ppath - on (i) . (12)
voltage range according to the threshold voltages of these
four CNTFETs. An example is presented in Figure 3, where If there is more than one path between the supply rail (Vdd
five regions (R1, R2, …, R5) are defined. In R1, R2, and R3, or GND) and the gate's output (eg, Npath), the activation prob-
the N-CNTFETs are turned on (VTri > Vth,I (N-CNTFET)). abilities of all paths are computed. Then, the disconnection
In R3, R4, and R5, the P-CNTFETs are turned on (VTri > |Vth,j and connection probabilities of the two nodes (supply rail
(P-CNTFET)|). The statuses of P-CNTFET(1) and P- and output nodes) are calculated using (13) and (14), respec-
CNTFET(2), as well as N-CNTFET(1) and N-CNTFET(2), tively. In these equations, up/down represents all paths from
are represented in Figure 3. Once the statuses (turning on or the gate's output to Vdd/GND.
off) of the CNTFETs are determined for each region, we then
Pconn (up∕down) = 1 − Pdisc . (13)
handle a turned on (or turned off) N-CNTFET similar to the
situation where Vdd (or GND) is connected to its gate termi-
Npath
nal. It should be noted that the probability that is calculated
(14)
∏
for a region Rj must be scaled by the probability of VTri fall- Pdisc (up∕down) = Ppath - off (i) .
i=1
ing in this region. This probability is calculated according
to (10), where Vmax(j) and Vmin(j) are the lower and upper There can be some paths in the PUN or PDN that share a
voltage levels defining the region Rj. CNTFET. An example is presented in Figure 4, where the T1
CNTFET is shared between paths 1 and 2. In this case, we
(Vmax (j) − Vmin (j)) combine these two paths into one super path, where the super
Pscale (Rj ) = . (10)
Vdd path's activation probability is calculated according to (15).
According to this equation, the super path turns on when the
It is also worth noting that all transistors (similar types shared transistor is ON and at least one of the unshared tran-
of CNTFETs) in the same column in the gate layout have sistors in ON (this case is equivalent to the complement of all
unshared transistor being OFF simultaneously).
N-CNTFET(2) N-CNTFET(1) Vdd P-CNTFET(2) P-CNTFET(1)
Psuper - path (on) = Ptr - on (1) × (1 − (1 − Ptr - on (2)) × (1 − Ptr - on (3))) .
(15)
ON ON OFF OFF
R1
Vth,PCNTFET(1)
ON ON OFF ON
R2
Vth,PCNTFET(2) Generally, if M paths share Nshared CNTFETs and the kth
path includes Np(k) unshared CNTFETs, then the probabil-
ON ON R3 ON ON
ity of turning on the super path is computed according to
(16).
Vth,NCNTFET(2)
OFF ON R4 ON ON
Vth,NCNTFET(1)
NShared M Np ( k )
R5 ∏ ∏ ∏
OFF OFF ON ON
Psuper - path (on) = Ptr - on (i) × (1 − (1 − Ptr - on (j))) .
GND
i=1 k=1 j=1

FIGURE 3 Region definitions for “Tri-STATE” handling (16)

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| JAHANIRAD AND HOSSEINI

and “FLOAT” states in a gate's outputs can be caused by the

VDD propagation of such states that are previously generated in the
gate's inputs or by the occurrence of an open/short fault in
the gate's CNTFETs. However, for a fault-free gate, the “Tri-
STATE” or “FLOAT” states generated in the gate's inputs can
T2 T3 still be propagated to its outputs. For example, consider a NOT
gate, where the PUN and PDN consist of a single P-CNTFET
Path1 Path2 and a single N-CNTFET, respectively. Additionally, suppose
the related voltage of a “Tri-STATE” state in the input can
T1 turn on both the P-CNTFET and N-CNTFET transistors. In
this case, the “Tri-STATE” state will turn on both the PDN
and PUN, so the generated state in the gate's output will be the
“Tri-STATE” state. If the “Tri-STATE” state cannot turn on
both the P-CNTFET and N-CNTFET, then a “FLOAT” state
FIGURE 4 A super path topology will be generated in the gate's output.
The probability of occurrence of the “FLOAT” state is
merged into the other states, as discussed in Section 3.1. For
Regarding to the gate's PTM computation, for row r (ap- each node in the circuit, we define an STPM according to
plication of the rth input vector), Pconn and Pdisc should be (21). In this context, a transition in a node indicates trans-
calculated before the following steps are implemented. For forming from one state A to another state B based on a pos-
the generation of the “FLOAT” state at the gate's output, the sible fault occurrence.
up and down paths must be disconnected according to (17).
⎡ p(s0 → s0 ) p(s0 → sTS ) p(s0 → s1 ) ⎤
PFLOAT (r) = Pdisc - up (r) × Pdisc - down (r) . (17) ⎢ ⎥
STPM = ⎢ p(sTS → s0 ) p(sTS → sTS ) p(sTS → s1 ) ⎥ . (21)
⎢ p(s → s ) p(s → s ) p(s → s ) ⎥
For the case of the “0” (“1”) state, all up (down) paths ⎣ 1 0 1 TS 1 1 ⎦

should be disconnected and at least one down (up) path

should be connected. Furthermore, the sharing of PFLOAT(r) The rows/columns of this matrix represent a node's signal
should be considered according to (18) (or (19)). states before/after a transition. The first, second, and third
rows/columns are dedicated to the “0,” “Tri-STATE,” and
1 “1” states of the node, respectively. For example, STPM(1,
P0 (r) = Pdisc - up (r) × Pconn - down (r) + × PFLOAT (r). (18)
3 2) represents the probability of a transition from the correct
“0” state to the incorrect “Tri-STATE” state. The STPM con-
1 tains the reliability information for a gate, which is calculated
P1 (r) = Pconn - up (r) × Pdisc - down (r) + × PFLOAT (r). (19)
3 as the sum of the probabilities of correct “0” (STPM(1, 1))
states and correct “1” (STPM(3, 3)) states, as shown in (22).
Finally, for the “Tri-STATE” case, at least one up path
and one down path should be turned on and the sharing of Relgate = STPM(1, 1) + STPM(3, 3) . (22)
the “FLOAT” state also should be included according to (20).
3.3 | Gate STPM computation
1
Ptri - state (r) = Pconn - up (r) × Pconn - down (r) + × PFLOAT (r) .
3 We have adopted the basic PTM-based method discussed in
(20)
[34], which was developed for binary logic values, for our
After computing (17) to (20) for all rows (r = 0 to r = 3Ninp four-valued logic setting. Suppose that a gate has Ninp inputs
− 1), the gate's PTM computation is completed. and one output. The first step in STPM computation is con-
structing a JPIM. The JPIM is a 3Ninp × 3 matrix that is con-
structed by combining the STPMs of all inputs in Ninp steps.
3.2 | STPM Each entry in this matrix represents the occurrence probabil-
ity of an input vector. In the first stage, STPM1 (index repre-
In a fault-free circuit, the output of a gate can be in the “0” sents the index of the related input) is combined with STPM2
or “1” states. However, when open and short faults are intro- according to (23), where (u1, v1) indices are related to STPM1
duced, the circuit's nodes can take on four states (“0,” “1,” “Tri- and (u2, v2) indices are related to STPM2. These variables can
STATE,” and “FLOAT”). Generation of the “Tri-STATE” take on states of “0,” “Tri-STATE,” or “1.”
JAHANIRAD AND HOSSEINI
| 7

correct “0” that is transformed to the incorrect “Tri-STATE;”

JPIM1,2 (u1 , v1 , u2 , v2 ) = p(su1 → sv1 ) × p(su2 → sv2 ) . (23)
and p3 is added to STPM(1, 3), which is related to the correct
“0” that is transformed into the incorrect “1.”
In this operation, each entry in STPM1 is multiplied by The second type is related to generation of the “FLOAT”
the STPM2 matrix using scalar multiplication. The resulting state in the gate's output when applying the i'th input com-
3 × 3 matrix is inserted in place of the corresponding entry bination. We interpret the “FLOAT” state as one of the “0,”
in the final matrix. At the end of the first stage, the generated “Tri-STATE,” and “1” states with probabilities of p1, p2, and
9 × 9 matrix contains the joint probabilities of the first and p3, respectively. For inclusion in the STPM, we assume an
second gate's inputs. For example, the entry (3, 3) contains equally probable expected state for the gate's output. For ex-
the probability of the first input being in the correct “0” state ample, if the “FLOAT” state is interpreted as the “0” state
while the second input is in the correct “1” state (p(I1 is cor- (with a probability of p1), then in the STPM, we select the
rect “0”) × p(I2 is correct “1”)). It is worth noting that the first column. Therefore, based on the assumption above, we
assumption of independent inputs is a default assumption for must add p1 to the entry that is located in the first row and
all stages. In the second stage, the same multiplication and first column. For the “Tri-STATE” state, we add p2 to the
substitution operations are applied to each entry in the gen- second row of the second column. Accordingly, for the “1”
erated 9 × 9 matrix and STPM3. At the end of this stage, a state, p3 is added to the third row of the third column.
27 × 27 matrix is produced, where each entry represents the As an example, consider a two-input NAND gate (for ad-
joint probability of inputs one, two, and three being in the ditional clarity, the internal circuitry of such a gate is illus-
specified states. In the following stages, similar operations trated in figure 9A in Section 3.4), where we assume that the
are applied to the fourth through Ninpth inputs and the pro- Vth values of two P-CNTFETs are equal, as are the Vth val-
duced matrix grows to form the final JPIM of the gate. For ues of two N-CNTFETs. Therefore, regarding VTri there are
additional clarification, we present the JPIM calculation for three different regions (R1, R2, and R3). In R1, VTri can turn
an arbitrary two-input gate in Figure 5, where the STPMs of on the N-CNTFETs, but cannot turn on the P-CNTFETs. In
the inputs are represented by matrices A and B. R2, VTri can turn on both the N-CNTFETs and P-CNTFETs.
In the second step, we calculate PM = JPIM × PTM. By In R3, VTri can turn on the P-CNTFETs, but cannot turn on
comparing the result to an ideal matrix (IM), an STPM is the N-CNTFETs. As stated previously, to derive an IM, we
constructed. The IM is a 3Ninp × 3 matrix that is computed should assume that all CNTFETs are fault-free, meaning we
similarly to the PTM, but all transistors in the gate are as- can extract the IM when VTri is placed into these three regions
sumed to be fault-free. Two types of rows exist in the IM: according to the gate's PTM calculation methodology. The
rows containing a “1” and two “0s” (type 1), and rows con- results are presented in Figure 6.
taining no “0s” (type 2). To clarify type 1, suppose that the For multi-fan-in gates, the size of the JPIM increases ex-
i'th row of the IM contains (1, 0, 0). We can deduce that if ponentially. For example, a six-input NAND gate requires a
the gate is fault-free, then the output must be “0” for the cor- (36)2 × (36)2 JPIM containing 531 441 entries. To reduce the
responding input vector. The equivalent row in the PM con- number of required computations, we decompose such a gate
tains (p1, p2, p3) and we perform the following operations: into a tree of two-input gates. The STPM derivation proce-
p1 is added to STPM(1, 1), which represents the correct “0” dure is then applied to each sub-circuit. The STPM of the
probability; p2 is added to STPM(1, 2), which represents the final gate in the tree is considered as the final STPM.
For primitive gates (AND, OR, NAND, and NOR) with
 a1 a2 a3   b1 b2 b3  N inputs, decomposition is applied based on the following
A   a4 a5 a6  B  b4 b5 b6  Boolean expressions:
 a7 a8 a9  b7 b8 b9 

 a1b1 a1b2 a1b3 a2b1 a2b2 a2b3 a3b1 a3b2 a3b3 

ab ab ab a2b4 a2b5 a2b6 a3b4 a3b5 a3b6 
 1 4 1 5 1 6
 a1b7 a1b8 a1b9 a2b7 a2b8 a2b9 a3b7 a3b8 a3b9 
 
 a4b1 a4b2 a4b3 a5b1 a5b2 a5b3 a6b1 a6b2 a6b3 
JPIM A, B   a4b4 a4b5 a4b6 a5b4 a5b5 a5b6 a6b4 a6b5 a6b6 
 
 a4b7 a4b8 a4b9 a5b7 a5b8 a5b9 a6b7 a6b8 a6b9 
a b a b a b a8b1 a8b2 a8b3 a9b1 a9b2 a9b3 
 7 1 7 2 7 3

 a7b4 a7b5 a7b6 a8b4 a8b5 a8b6 a9b4 a9b5 a9b6 
 a9b9  The AND, OR, and NOT operators are indicated by ., +,
 a7b7 a7b8 a7b9 a8b7 a8b8 a8b9 a9b7 a9b8
and ~symbols, respectively. A parenthesis on the right-hand
FIGURE 5 JPIM construction for a two-input gate side of an expression indicates a two-input gate. In the cases
8
| JAHANIRAD AND HOSSEINI

of NAND and NOR gates (the final two expressions), decom- P-CNTFETs and N-CNTFETs to propagate the faulty state
positions are performed based on decompositions of equiv- with maximum probability.
alent AND and OR gates, respectively. Then, the necessary To verify the accuracy of this decomposition approach,
inversion is accomplished by using a NOT gate following we compared the resulting STPM of the output of the multi-
decomposition. fan-in gate to the STPM of the output of the corresponding
The application of this method for a four-input NAND decomposed tree. These comparisons were performed for all
gate is illustrated in Figure 7. The corresponding tree is pre- primitive gates (AND, OR, NAND, and NOR) with fan-in
sented in Figure 7A. This tree consists of three two-input numbers between three to nine, while the STPM for each
AND gates and a single NOT gate. This tree is constructed gate's input was selected randomly to cover all possible cases.
based on the Boolean expression below. We considered the complementary and ratioed design styles
in our simulations. In the pass-transistor logic, the core of the
design was realized using two connected N-CNTFETs (for
additional clarity, the internal circuitry of a two-input NAND
gate is presented in figure 10 in Section 3.4), meaning the
implementation of high fan-in gates can be accomplished
using two-input modules. The problem of a very large JPIM
is solved by this design methodology automatically.
The results of our comparisons are presented in Figure 8.
Based on these results, we can deduce that the proposed de-
The transistor-level topology of the tree is presented in composition approach has less than 0.01% error for STPM
Figure 7B, where the green CNTFETs are fault-free and calculations. Additionally, the problem of exponential
Ti is equivalent to Ti in the four-input NAND gate topol- growth in JPIM size is resolved by the proposed decompo-
ogy (Figure 7C). Additionally, in this figure, for all gates sition method. For example, in the four-input NAND case,
(AND1, AND2, AND3, and NOT), the related transistors each NAND and NOT gate is related to a 9 × 9 and 3 × 3
are identified using colored regions. As an important point JPIM, respectively. Therefore, the six-input NAND gate's tree
in Figure 7C, the “Tri-STATE” state turns on both the green
0.007
Average error
0.006
AND OR NAND NOR
0.005
Absolute error

0.004

0.003

0.002

0.001

0
3 4 5 6 7 8
Fanin number

FIGURE 6 IM for a two-input NAND gate: (A) R1, (B) R2, (C) R3 FIGURE 8 Average error of decomposition

VDD
VDD
i0 i1
T1 T2
i0 T1 i1 T2 i2 T3 i3 T4
i2
T3
i0 T5 i3 out
T4 i0 T5

AND1
out
i0
AND2 i1 T6 i1 T6
AND3
NOT
i1 out i2 T7
i2 T7
i2
i3
AND1 i3 T8
i3 T8
AND2

AND3
(A) (B) (C)

FIGURE 7 Multi-Fan-in NAND gate

JAHANIRAD AND HOSSEINI
| 9

consists of five two-input NAND gates and six NOT gates. to the GND (logic state “0”) permanently. The related equa-
Consequently, the total number of related JPIM entries is 459 tions for A = “0” and B = “Tri-STATE” are defined in (26)
(= 81 × 5 + 9 × 6), which is a significant reduction compared and (27), respectively.
to the 531 441 entries for a six-input NAND gate.
Pdisc (up) = PO (T1) . (26)

(27)
|
( )
Pdisc (down) = 1 − PS (T3) × 1 − PO (T4) .
3.4 Various gate design method examples

In this subsection, we present some examples to clarify the The internal circuitry of NANDpass, which is implemented
approach of our proposed method for the reliability evalua- using the pass-transistor design method, is presented in
tion of CNTFET-based logic gates. We consider complemen- Figure 10. As an example, assume that in the NANDPass to-
tary, ratioed, and pass-transistor design methodologies. pology, the N-CNTFETs are fully correlated with Vth < VTri.
In the complementary gate design, the PUN and PDN Additionally, suppose that the first NOT gate produces a
are implemented using P-CNTFETs and N-CNTFETs, inde- “Tri-STATE” state in B, meaning VTri is connected to the gate
pendently. The internal circuitry of a two-input NAND gate terminal of the T2 CNTFET. Subsequently, this transistor is
is illustrated in Figure 9A. Assume that for the T1 transistor, turned on and connects node F to the GND. In contrast, if
|Vth| < VTri, and for the T2 transistor, |Vth| > VTri. Therefore, the T1 CNTFET turns on (as B = “1” or “Tri-STATE,” or a
the “Tri-STATE” state voltage can turn on T1, but cannot short fault in the transistor occurs), then the path from A to F
turn on T2. The T3 and T4 transistors (which comprise the may conflict with the turned on path from F to GND. If the
PDN) are placed in the same column, meaning they are fully state of A is “0,” then two paths connect F to GND simulta-
correlated and their threshold voltages are equivalent [25]. neously, meaning the state of F would be “0.” If A = “1” or
We assume that for the T3 and T4 transistors, Vth < VTri. “Tri-STATE,” then the first path connects F to the GND, but
Then, the PTMComp and STPMcomp can be calculated accord- the second path connects F to Vdd or VTri. These two cases
ing to the approach described in the previous subsections. For produce the “Tri-STATE” state in the F node.
example, suppose that we wish to calculate the second row of To compute the PTM of a NANDpass gate (Figure 10),
the PTM, which is related to A = “0” and B = “Tri-STATE.” three steps are applied for every input vector. First, the STPM
According to the assumptions outlined above, the input B can of B is calculated using the PTM of the corresponding NOT
turn on T4 and turn off T2, while the input A turns on T1 gate and STPM of input B. Second, the STPM of node F is
and turns off T3. The related equations for Pdisc (up) and Pdisc calculated, where T1 and T2 connect node F to input A and
(down) are represented in (24) and (25), respectively. the GND, respectively. The turned on/off states of T1 and T2
are determined based on the B and B logic values, as well as
Pdisc (up) = (1 − 1 − PO (T1) × 1 − PS (T2) . (24)
( ) ( )
the V th values of the transistors. If A = “0,” then there is no
possible way to generate “Tri-STATE” or “1” states in the F
(25)
( )
Pdisc (down) = 1 − PS (T3) × 1 − PO (T4) .
node. However, if A = “1” (= Vdd), then T1 acts as a PUN.
In contrast to the complementary and ratioed logic styles,
where P-CNTFETs are used in the PUN, this PUN cannot
The internal circuitry of a NAND gate implemented using charge the voltage of node F to Vdd (that is, Vdd – Vth,n).
the ratioed method is illustrated in Figure 9B. Compared to
the complementary design, the NANDRat and NANDcomp
B
have similar PDN networks, but the PUN in NANDRat con-
tains only a P-CNTFET, where the gate terminal is connected A VDD
VDD T1
VDD
VDD (13,0) (19,0)
(10,0)
F
(19,0) (19,0) Out
T1
A T1 T2 B (19,0) (19,0)
Out Out
A A B B
T3 (19,0) T3 (19,0)

B T4 (19,0) T2
B T4 (19,0) (19,0) (13,0)
(A) (B)

FIGURE 9 (A) NANDComp, (B) NANDRat FIGURE 10 NANDPass

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| JAHANIRAD AND HOSSEINI

Suppose that T1 and T2 turn on simultaneously based on the STPM’1 and STPM’2 (see (28) and (29)) instead of STPM1
application of proper gate voltages (eg, VG(T1) = Vdd and and STPM2, respectively.
VG(T2) = Vdd). Then, the generated voltage in node F would
be much lower than Vdd / 2. In this case, we approximate the ⎡ p(s0 (1) → s0 (1)) 0 0 ⎤
⎢ ⎥
logic of node F as the “0” state. Based on the full correlation STPM�1 =⎢ 0 0 0⎥ . (28)
between CNTs in T1 and T2, short and open faults occur ⎢ 0 0 ⎥⎦
⎣ 0
simultaneously. If both transistors contain open faults, then
node F will be in the “FLOAT” state. Furthermore, the exis-
tence of short faults in T1 and T2 results in a “Tri-STATE” ⎡ p(s0 (2) → s0 (2)) 0 0 ⎤
⎢ ⎥
state in node F. In the final step, the STPM of the gate's out- STPM�1 =⎢ 0 0 0⎥ . (29)
put is calculated based on the PTM of the second NOT gate ⎢ 0 0 ⎥⎦
⎣ 0
and the STPM of node F.

This approach generates exact results, but it is not scal-

4 | R E L IA B IL IT Y E VA LUAT ION able for large circuits. For a circuit with NFOC-rec problematic
O F CO M BINAT IONA L C IRC U ITS FOCs, the total number of necessary iterations is 9Nfoc-rec,
which grows exponentially (approximately 3.48 × 109 for
The overall flow of the proposed reliability estimation iterations NFOC-rec = 10). In this study, we selected a small
method for combinational logic circuits can be summarized number of reconvergent FOCs to achieve enhanced accuracy
as follows. In the initial step, required parameters such as in our reliability evaluation flow. This selection was per-
pm, pmr, and psr are tuned. Additionally, for each gate type formed according to a ranking process based on the num-
(NAND, NOR, XOR, NOT, etc) the chirality vectors of the ber of reconvergent points generated by each FOC. In [34],
gate's CNTFETs are defined. Next, by using (8) and (9), the a correlation-coefficient-based approach was developed to
Vth values of all CNTFETs are calculated. handle the reconvergent fan-out problem efficiently.
In the next step, the circuit is levelized in topological order. The proposed method is applicable to combinational
Starting from level 1, where all gate inputs are connected to circuits, but by using the sequential-to-combinational con-
the primary inputs, the following operations are applied to version methodology developed in [35], we can handle se-
each gate. Based on the STPMs of the gate's inputs, the JPIM quential CNTFET-based logic circuits appropriately.
is constructed and the PTM of the gate is calculated using the The proposed reliability evaluation method has linear com-
method discussed in Section 3.1. According to Section 3.3, putational and space complexity relative to the number of cir-
the STPM of the gate can be derived from the JPIM and the cuit gates. Therefore, the proposed method is scalable to large
STPMs of the inputs. The calculated STPM is assigned to circuits. Suppose that a logic circuit contains Ng two-input
all branches of the fan-out cone (FOC) originating from the gates (or is converted into such a circuit according to the pro-
target gate. For the other levels, similar operations are applied posed decomposition procedure) that are ordered in L levels,
until the primary outputs are reached. At this time, all STPMs each of which contains ng(l) gates. The proposed algorithm tra-
are calculated and the reliabilities of all circuit nodes can be verses the circuit graph in level-by-level fashion. In each level,
derived using (22). two processes are executed. First, we compute a PTM for every
One noteworthy issue in this process flow is reconvergent gate belonging to the current level. If the average effort (mul-
fan-out handling. As stated previously, in the calculation of tiplication and summation) required to compute this matrix is
a gate's JPIM, independency among inputs is assumed, but PPTM, then the corresponding total computational complexity
this assumption is incorrect in the case of reconvergent fan- is PPTM × Ng. Second, we compute an STPM for the gates in
out. When the branches of an FOC intersect at two inputs level l using the procedure outlined in Section 3. The average
of a specific gate, those two inputs become dependent. This effort required for this step is considered to be PSTPM and the
error in JPIM computation leads to inaccuracies in the com- overall corresponding complexity is PSTPM × Ng.
puted STPM of such a gate. Similar to the authors of [28], For greater clarity, assume that a circuit is synthesized
we use a multiple-iteration approach to solve this problem. using only two-input NAND gates (we refer to the inputs as A
In this approach, FOCs that generate reconvergent points are and B). It should be noted that the NAND gate is a universal
first identified. Next, in each iteration, only one state of the gate and every switching function can be realized using only
identified FOCs is used in the reliability evaluation flow. For NAND gates. In this case, there are two parallel paths in the
example, if two identified FOCs (F1 and F2) generate a re- PUN and a single series path in the PDN. Based on the exis-
convergent point in a circuit, then in the first iteration, F1 and tence of two P-CNTFETs in the PUN and two N-CNTFETs
F2 are assumed to be in states STPM1(1, 1) and STPM2(1, in PDN, there are five regions for each “Tri-STATE” state in
1), respectively. This means that in the first iteration, we use a gate's inputs. Therefore, there are 49 different cases ((AB,
JAHANIRAD AND HOSSEINI
| 11

number of different cases) = (00, 1), (01, 1), (0T, 5), (T0, different output values, then an error occurrence is registered
5), (TT, 25), (T1, 5), (10, 1), (1T, 5), and (11, 5)) for each for the corresponding scenario. Suppose that for an arbitrary
gate's PTM calculation. For each case, according to (11) to logic gate, we consider NFault_Scen fault scenarios, where Ninp_
(20), nine multiplications, five subtractions, and three addi- vec input vectors are simulated for each scenario. If the total
tions are required. Therefore, for complete calculation of the number of error occurrences is Errtot, then the reliability of
PTM, we must apply 49 × (9 + 5 + 3) arithmetic operations the gate can be calculated according to (31).
(PPTM = 833). In the STPM calculation, we perform 81 mul-
Errtot
tiplications to construct the JPIM (Figure 5). Next, (3 × 9) Relgate = 1 − . (31)
NFault_Scen × Ninp_vec
multiplications and (3 × 8) summations are performed in the
JPIM ×PTM calculation. The next steps to derive the STPM
require (3 × 9) summations. Finally, the total number of re- However, this method is very time-consuming and has high
quired operations required for STPM computation (PSPM) is computational complexity (NFault_Scen different HSPICE sim-
159. Ultimately, for a circuit with Ng two-input NAND gates, ulations). In contrast, our proposed method can estimate gate
the total number of arithmetic operations is 992 × Ng. This reliability rapidly and accurately. To verify the accuracy of
result indicates linear growth in computational complexity our method, we compared the reliability estimates generated
for the proposed reliability evaluation approach. by our method to those generated by the MC SPICE method.
Space complexity includes the registration of circuit Various gate types (NAND, NOR, AND, OR) with multiple
graph information (k1 memory words, including the type of fan-in numbers (two to eight fan-in numbers for each gate type)
gate and its fan-in and fan-out interconnections), the STPM were considered in our simulations. Additionally, complemen-
of Iprim primary inputs (nine memory words for every input), tary, ratioed, and pass-transistor design styles were used in our
and STPMs of Ng gates (nine memory words for every gate). simulations. The states of all CNTFETs in each gate (fault-free,
The gate PTM and STPM calculations are accomplished open fault, and short fault) must be determined prior to HSPICE
in level-by-level fashion, as well as in gate-by-gate fashion simulation. We generated the required (at least 10 000) fault
within each level. Therefore, the space complexity of this scenarios using MATLAB for various PS and PO probabilities
process is based on a 9 × 9 JPIM, 9 × 3 PTM, and 9 × 3 (in the range of 0.001 to 0.1). For each scenario, the related
IM, which are independent of the number of circuit gates. data were added to the MC SPICE simulation externally. The
Consequently, the space complexity of a circuit containing Ng generated output values (from the HSPICE simulations) were
two-input NAND gates can be calculated according to (30). then registered in an output file corresponding to the applied
input vectors. Finally, error occurrence cases were identified
M = (k1 + 9) × Ng + Iprime × 9 . (30) for the target scenario using MATLAB. The average errors of
reliability estimation for the proposed method compared to MC
One can see that the space complexity of our proposed HSPICE simulation are presented in Figure 11. According to
method is also linear relative to the number of circuit gates. the simulation results, the average value of estimation error is
only 0.01% for various gate types, demonstrating the high ac-
curacy of our proposed method.
5 | S IM U LAT ION R E S U LTS
⎡ 0.25 0 0 ⎤
5.1 | Reliability comparisons of various ⎢
STPMIdeal = ⎢ 0 0
⎥
(32)
0 ⎥.
single gates ⎢0 0
⎣ 0.75 ⎥⎦
Various design methodologies for a logic gate can be selected
by an IC designer. Each design has its advantages and disad- For reliability comparisons using individual gates, three
vantages in terms of delay, power dissipation, noise margin, NAND gates (described in Section 3.4) were considered.
etc [36]. The reliability of emerging technologies such as We applied the proposed method for the STPM derivation
CNTFETs must be considered during gate design selection. of gate outputs when the NAND inputs were connected to
An accurate and straightforward methodology for computing fault–free primary inputs. In this scenario, if there is a fault-
the reliability of a logic gate is the simulation of its behav- free NAND gate, the STPMideal would be equal to (32). All
ior using Monte-Carlo SPICE (MC SPICE). In such simula- entries except for STPMideal(1, 1) and STPMideal(3, 3) are
tions, various scenarios for fault occurrence in CNTFETs are zero. The entries of STPMideal(1, 1) (correct “0” state) and
considered. For each scenario, the output of the target gate STPMideal(3, 3) (correct “1” state) are equal to 0.25 and 0.75,
for different input vectors is derived using HSPICE simula- respectively. We illustrate the values of correct “0” and cor-
tions and compared to the result of a fault-free gate. For a rect “1” states for a conventional CNTFET, ACCNT_5, and
given input vector, if the faulty and fault-free gates generate ACCNT_15 in Figures 12, 13, and 14, respectively. The x
12
| JAHANIRAD AND HOSSEINI

0.012 F I G U R E 1 1 Estimation errors for

various gate types
0.010
Estimation error %

0.008

fanin 2
0.006 fanin 3
fanin 4
0.004 fanin 5
fanin 6
0.002 fanin 7
fanin 8
0

0.8 Pass_0 Pass_1 Rat_0 Rat_1 Comp_0 Comp_1 F I G U R E 1 2 Correct “0” and “1”
probabilities for a conventional CNTFET
0.7

0.6

0.5

0.4

0.3

0.2

0.1

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NCNT

0.8 Pass_0 Pass_1 Rat_0 Rat_1 Comp_0 Comp_1 F I G U R E 1 3 Correct “0” and “1”
probabilities for ACCNT_5
0.7

0.6

0.5

0.4

0.3

0.2

0.1

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NCNT
JAHANIRAD AND HOSSEINI
| 13

F I G U R E 1 4 Correct “0” and “1” 0.8 Pass_0 Pass_1 Rat_0 Rat_1 Comp_0 Comp_1
probabilities for ACCNT_15
0.7

0.6

0.5

0.4

0.3

0.2

0.1

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NCNT

FIGURE 15 Reliability of NANDComp 120

100

80
Reliability

60

40 Conv ACCNT_2 ACCNT_5

ACCNT_10 ACCNT_15
20

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NCNT

axes in these figures represent the number of CNTs contained When an ACCNT is used a gate's topology, deviation from
in each gate's CNTFETs. For example, NCNT = 10 indicates the ideal value decreases as the number of CNTFETs in a
that there are 10 CNTs in T1, T2, T3, and T4 in Figure 8A. row increases. This occurs based on the lower short and open
In the ACCNT_5 and ACCNT_15 gates, any conventional fault probabilities of the ACCNT structure. The behavior
CNTFET is replaced with a row similar to that shown in of NANDRat and NANDCompl differs in producing a correct
Figure 2, where 5 and 15 CNTFETs are placed between the D “1” state. Because the simpler PUN (only one P-CNTFET
and S nodes, respectively. in NANDRat compared to two transistors in NANDCompl)
In all of these cases, the NANDPass performance is rel- in NANDRat is always on, this gate can prevent a transition
atively low, meaning the probabilities of correct “0” and from the correct “1” state to other states more efficiently.
“1” states in STPMPass deviate more than the corresponding Therefore, particularly for small values of NCNT, the correct
probabilities in STPMComp and STPMRati. The main reasons “1” state probability of NANDRat is closer to the ideal value
for this deviation are potential connections from the drain/ (0.75).
source terminals of the T1 transistor to the “Tri-STATE” The reliabilities of three NAND gates are plotted in
state and the NOT gate, which is placed between node F Figures 15 to 17. Each figure contains five graphs. In each
and the output nodes, resulting in additional erroneous val- graph, one type of CNTFET is used to implement the cor-
ues in the gate's outputs (Figure 10). Therefore, the total responding gate's structure. For example, the graph with the
number of cases that can lead to “Tri-STATE” state gener- label “conv” corresponds to a NAND gate using conventional
ation in the NANDPass output increases, making the “Tri- CNTFETs. The graph labeled “ACCNT_N” corresponds to
STATE” state probabilities greater (see STMPPass(1, 2), and a NAND gate using an ACCNT structure with N CNTFETs
STMPPass(3, 2)). in a row. For the aforementioned reasons, the reliability of
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| JAHANIRAD AND HOSSEINI

120 FIGURE 16 Reliability of NANDRat

100

80
Reliability

60

40 Conv ACCNT_2 ACCNT_5

ACCNT_10 ACCNT_15
20

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NCNT

90 FIGURE 17 Reliability of NANDPass

80

70

60
Reliability

50

40

30 Conv ACCNT_2 ACCNT_5

20 ACCNT_10 ACCNT_15

10

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NCNT

NANDPass is lower than that of the other two architectures. all methods were compared using an MC reliability evalu-
For the interpretation of gate reliability behavior, we divide ator, where the following steps were applied in each itera-
each plot into two parts. In the lower part (NCNT < 8), PO tion. First, a fault pattern was generated based on the PO and
dominates PS. Therefore, according to these figures, the PS values of the CNTFETs. In each fault pattern, the states
ACCNT structure with additional transistors is more unre- (normal, short fault, and open fault) of all transistors were
liable. An increasing NCNT leads to a decreasing PO, which determined according to the uniform distribution of the faults
results in an improvement in reliability. When PO decreases, in the IC. Next, a subset of all input vectors was randomly
PS increases, which does not change the reliability of the selected and the selected vectors were applied to the faulty
ACCNT-based gates significantly (based on the negligible and fault-free circuits simultaneously. For each applied vec-
value of PS in the ACCNTs). However, for the conventional tor, the logic values of the outputs in the fault-free and faulty
CNTFET-based NAND gates, PS has significant value com- circuits were compared. If the logic values did not match,
pared to PO. Therefore, in the second part of the graphs, the the corresponding error increased by one. One important con-
reliability of the conventional CNTFET-based gate slightly sideration is how to handle the “FLOAT” state. When the
decreases when PS increases. “FLOAT” state appears in the output of a gate, the value is
converted to one of the other values with an equal probability
(1 / 3). The other major issue is related to the “Tri-STATE”
5.2 | Comparison to previous methods state voltage generated at the output of the gate (VTri). As
mentioned in Subsection 3.1, when both the PUN and PDN
We compared our proposed method to the three methods de- are turned on, the drive strength of the turned on paths in
veloped in [26], [27] and [28]. Hereafter, we refer to these the PUN and PDN determines VTri. For the basic logic gates
methods as M1, M2, and M3, respectively. The results for (AND, OR, etc), to obtain more realistic VTri values, we
JAHANIRAD AND HOSSEINI
| 15

simulated (using HSPICE) the possible scenarios that can caused by a faulty gate (case 1). This method has some short-
generate the “Tri-STATE” state at the output of the gate. We comings. First, it is assumed that the “H” state cannot turn on
recorded the generated VTri values for all scenarios in a table any CNTFET, which is not true in a practical model. Second,
linked to the gate. Subsequently, if one of the possible “Tri- the probability of a gate's output being the “FLOAT” state
STATE” states occurred in a gate, the value of VTri would must be translated into three other states, but in this method,
be calculated based on this table. The next fault pattern was it is considered only as the “H” state. Third, reconvergent fan-
then generated and the steps above were repeated in the next outs are not handled in this method.
iteration. This approach is very accurate if there are sufficient The M3 method is another analytical method based on
fault patterns and selected vectors in each iteration. However, PTMs. In this method, all four states (“0,” “1,” “Tri-STATE,”
achieving acceptable accuracy requires very high run times. and “FLOAT”) are considered for a gate's PTM calculation.
M1 is a semi-analytical method in which each row of One major problem with this method is related to the trans-
the gate's PTM is encoded as a “state sequence” [26]. For formation of a complete PTM (similar to our proposed meth-
example, suppose that we select a sequence size of 1000 od's PTM) into a smaller PTM in which “Tri-STATE” state
and in row r of the gate's PTM, the probabilities of the “0”, probabilities are eliminated. This transformation makes the
“Tri-STATE,” and “1” states are equal to 0.2, 0.1, and 0.7, reliability evaluation flow similar to gate-level PTM-based
respectively. Consequently, there will be 200, 100, and 700 analysis, but introduces significant errors based on the ex-
of the “0”, “Tri-STATE,” and “1” symbols in the sequence, clusion of the “Tri-STATE” and “FLOAT” states in a gate's
respectively. After generating all PTM-related sequences, a STPM calculations. Another concern regarding this method
2k × 1 multiplexer is inserted in place of each gate (k is the is that reconvergent fan-outs are not considered.
gate's input number) and the sequences are connected to the As mentioned previously, MC is the reference method
corresponding multiplexer (MUX) inputs. The input pins of used for measuring the accuracy of the other methods. The
the gate are interpreted as selector inputs for the MUX. The reliability estimation error for a method Mi was calculated
randomly generated sequences are assigned to the primary according to (33). We used the ISCAS 85 benchmark circuits
inputs and propagated through the circuit's MUXs. The reli- to compare the performance of the proposed method to those
ability of a gate is computed by decoding the corresponding of MC, M1, M2, and M3.
MUX’s output sequence. The probability of the “0”, “1”, and Table 1 lists the set of ISCAS 85 benchmark circuits and
“Tri-STATE” states is calculated by dividing the number of two very large circuits from the ITC 99 benchmark circuits
related symbols by the sequence length. The reliability of (b18 and b19). The total numbers of CNTFETs included in
a sequence is computed by summing the “0” and “1” state the benchmark circuits are indicated in second column. The
probabilities. In this method, to achieve high accuracy for re- run times (in seconds) and memory usages (in kilobytes) of
liability estimation, we must adopt a large sequence length the reliability evaluation methods are reported in the third
that imposes additional run time overhead. Additionally, the and fourth columns of Table 1, respectively. All simulations
decoding process is imperfect based on its interpretation of were executed on a 3.2 GHz microprocessor with 4 GB of
all “0” (“1”) states in the gate's output sequence as correct
“0” (“1”) states, even though some of these “0” (“1”) states T A B L E 1 Run times and memory usages of the proposed method
may be incorrect. This misinterpretation will result in greater for different benchmark circuits
inaccuracy in circuits containing many reconvergent fan-outs. Number of Runtime Memory
This effect is caused by the existence of many correlated sig- Circuits CNTFETs (sec) (Kbytes)
nals in such circuits. If the target sequence of correlated sig-
C17 24 6.86 1.48
nals contains incorrect “0” (“1”) states, then they will likely
C432 1006 25.00 36.28
be maintained through the propagation process.
C499 1524 25.39 45.49
The second method (M2) is an analytical reliability eval-
uator in which three states (“0,” “1,” and “H”) are defined C880 2064 25.45 85.01
for each circuit node. The state “H” represents both the C1355 2484 28.13 118.05
“FLOAT” and “Tri-STATE” states in our method. Regarding C1908 4214 31.03 187.95
a gate's failure probability calculation, three cases are consid- C2670 6192 37.96 262.69
ered: 1) the gate's inputs are fault-free and the gate is faulty, C3540 8894 49.23 355.57
2) the gate is fault-free and the gate's inputs are faulty, and C5315 13 942 56.02 499.15
3) both the gate and the gate's inputs are faulty. This method C6288 10 112 43.39 511.88
operates based on event occurrences in the inputs and outputs
C7552 17 544 63.35 755.37
of a gate. An error in the output of a gate may occur based on
b18 428 552 1526.77 19 883.25
input error propagation through fault-free (case 2) or faulty
b19 865 366 3423.79 40 124.74
(case 3) inputs, or through the generation of a faulty output
16
| JAHANIRAD AND HOSSEINI

Our Method M1 M2 M3 F I G U R E 1 8 Estimation errors for the

ISCAS 85 benchmark circuits
45

40

35
Estimation err %

30

25

20

15

10

0
c17 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552
Benchmark circuit

M1 M2 M3 MC F I G U R E 1 9 Run time ratios of

various methods relative to the proposed
1 000 000 method

100 000

10 000
Runtime ratio

1000

100

10

0.1
c17 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552

Benchmark circuit

RAM. The results indicate that the proposed method is fast average errors of the other methods are 9.08%, 16.21%, and
and scalable, even for very large circuits such as b18 (94 249 9.87% for M1, M2, and M3, respectively. M2 exhibits the
gates) and b19 (19 0213 gates). It should be noted that for worst performance because it uses the “H” state instead of the
such large circuits, the MC method requires multiple days “FLOAT” and “Tri-STATE” states.
and several gigabytes of memory to complete its calculations. In circuits with large numbers of reconvergent fan-outs
Therefore, the estimation errors and runtime ratios are not (C432, C499, and C6288), the estimation error of our method
reported for b18 and b19 in Figures 17 and 18. is much lower than those of the other methods. This can be
The average reliability estimation errors for the circuit attributed to the inability of M2 and M3 to handle reconver-
gates are presented in Figure 17 for the ISCAS 85 benchmark gent fan-outs. Generally, when reducing the transistor error
circuits. probabilities (PO and PS), the error values become smaller for
all methods. For each method, the reliability estimation error
Erri = 100 × | RelMC − RelMi | ∕RelMC . (33)
increases with increasing circuit size. In all cases, M1 outper-
forms M2 and M3, which can be attributed to its simulation-
In Figure 18, we present the average results for three val- based nature and handling of reconvergent fan-outs.
ues of PS and PO (0.1, 0.01, and 0.001). In all cases, the pro- The other important factor is the run times of the methods.
posed method outperforms the others methods. The average The ratios of the runtimes of the other methods relative to the
estimation error of the proposed method is 2.67%, while the proposed method are presented in Figure 19. Because it is
JAHANIRAD AND HOSSEINI
| 17

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| JAHANIRAD AND HOSSEINI

29. S. J. Tans, A. R. M. Verschueren, and C Dekker, Room tempera- AUTHOR BIOGRAPHIES

ture transistor based on a single carbon nanotube, Nat. 393 (1998),
49-52.
Hadi Jahanirad received his BS de-
30. C. G. Almudever and A. Rubio, Variability and reliability analy-
sis of CNFET technology: Impact of manufacturing imperfections,
gree in Electrical Engineering from
Micro. Reliab. 55 (2015), 358-366. the Department of Electrical
31. B. Ghavami et al., Statistical functional yield estimation and en- Engineering, Khaje Nasir Toosi
hancement of CNFET-based VLSI circuits, IEEE Trans. VLSI. 21 University, Tehran, Iran in 2006, and
(2013), 887-900. his MS degree and PhD from the Iran
32. F. Yang et al., Chirality pure carbon nanotubes: growth, sorting, University of Science and
and characterization, Chem. Rev. 120 (2020), 2693-2758.
Technology, Tehran, Iran in 2008 and 2012, respectively.
33. M. Ahmad and S. R. P. Silva, Low temperature growth of carbon
Since 2013, he has worked with the Department of
nanotubes—A review, Carbon. 158 (2019), 24-44.
34. H. Jahanirad, CC-SPRA: Correlation coefficients approach for sig- Electrical Engineering at the University of Kurdistan,
nal probability-based reliability analysis, IEEE Trans. Very Large Sanandaj, Iran, where he is currently an assistant profes-
Scale Integr. Syst. 27 (2019), 927-939. sor. His main research interests include digital system de-
35. H. Jahanirad and K. Mohammadi, Sequential logic circuits reliabil- sign, VLSI design, reliability analysis of logic circuits,
ity analysis, J. Circuits Syst. Comput. 21 (2012), no. 5, 1250040. digital circuit testing, approximate computing, and evolu-
36. M. A. Savari and H. Jahanirad, NN-SSTA: A deep neural network tionary computing.
approach for statistical static timing analysis, Expert Syst. Appl.
149 (2020), 113309.
Mostafa Hosseini received his BS
degree in Electrical Engineering
from the Department of Electrical
Engineering, Islamic Azad
University, Hamedan Branch,
Hemedan, Iran in 2016 and his MS
degree in Electrical Engineering
from the Department of Electrical Engineering, University
of Kurdistan, Sanandaj, Iran in 2018. His main research
interests include VLSI design, fault-tolerant systems, dig-
ital circuit testing, approximate computing, and the reli-
ability analysis of logic circuits.