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JitterPres

The document discusses jitter in high-speed services, focusing on noise interference in data signals and its impact on system interoperability. It covers various types of jitter, current standards, and methods for adding noise to test high-speed data devices. Additionally, it presents available products for jitter testing and their applications in R&D and manufacturing test environments.

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getjobeasily145
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2 views

JitterPres

The document discusses jitter in high-speed services, focusing on noise interference in data signals and its impact on system interoperability. It covers various types of jitter, current standards, and methods for adding noise to test high-speed data devices. Additionally, it presents available products for jitter testing and their applications in R&D and manufacturing test environments.

Uploaded by

getjobeasily145
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 27

Jitter in High Speed Services

Author James Lim, Technical Support


Webinar Agenda

• Basic Concepts

• Serial Data Standards

• Products by Application

• Product Summary
What is Noise?

• Unwanted interference on a data signal

• Random noise is caused by thermal


changes in conductive elements -
thermal noise

• Noise coupled to data signals can be


used to assess interoperability among
system components
Adding Jitter Noise Concepts

• Where: High speed data signals that connect


components on PC mother boards, or network systems.

• How: Emulate real world signal interference by adding


precise amounts of noise to a digital system.

• Methods: Amplified broadband noise is fed into


phase modulator that produces edge movement, or
added directly to a signal via AM coupling.

• Products: AWGN Noise Modules and Instruments.

• Results: Changes in BER or Scope persistence eye-


diagram.
Current Standards Addressed
• PCI-Express Gen I and Gen II

• 10 & 40 Gigabit Ethernet

• USB 3.0 - data rate at 4.8Gbps


 Server Back Planes

• SATA Revision 3.0 (6 Gbps)


View in Time & Frequency Domain
Views in A Clean Signal Noise Added Observation

Time Transition or
Domain edge timing
variation

Spreading
Frequency of the
Domain spectrum
Transition Jitter

Edge timing is critical for correct


data detection

Time Domain
• Jitter causes unstable
timing transitions

Frequency Domain
• Manifests as phase noise
• Causes spectral dispersion issues
Adding Noise on a Signal Edge
The PCI-SIG Tj Model

The Total Jitter Equation

• Tj is Total jitter
• Rj is Random jitter
• Dj is deterministic jitter
 Pj is Periodic jitter
 DDj is Data Dependent jitter
- DCD is Duty Cycle Distortion
- ISI is Inter-Symbol Interference
Jitter Types

• White Noise Random


Jitter Rj

• Rj + Deterministic Jitter
Dj (CW)

• Rj + Deterministic Jitter
Dj (Triangle)
 SSC - Spread Spectrum
Clock
Providing True Gaussian Noise

• A high Crest factor of


7σ (sigma) or 18 dB
• Time Domain
 AWGN signal on Scope (magenta)
 Histogram (yellow) - Gaussian
amplitude distribution

• Frequency Domain
 Flat and Smooth across full band

• Statistical Domain
 1 σ ≈ RMS
 nσ/σ = PK-PK Crest Factor
Noise Implementation

• Amplitude Modulated (AM) on data


signal

• Phase modulated (PM) on data signal


via BERT timebase input port
Noise Coupled to Data Signal

Data Signal Gen


J7000 Series

Signal + Noise

DUT

Generator with
Differential Outputs
Oscilloscope (Alternative source)
Noise Coupled to Signal

• Rj noise added directly


to the signal

• AWGN disturbs signal


horizontally & vertically

• Transition rise time


effects dv/dt magnitude

• Precision attenuators
adjust this disturbance
Modulated Time Base (Injected)

J7000 Series
BERT

Data Signal with AWGN

Noise to Disturb
Time Base

DUT Return
Signal
Noise Injected into Time Base

• Noise added directly to


instrument time base

• AWGN disturbs signal


on the time axis

• Precision attenuators
adjust amount of
disturbance

• Translates to seconds
Effects of Varying Amount of Noise

Amplitude Jitter on Scope: Amplitude Jitter on Scope:


Amplitude variation on Amplitude variation on
digital signal with low digital signal due to moderate
amount of noise added. amount of noise added.
Effects of Varying Amount of Noise

Amplitude & Phase Jitter


on Scope:
amplitude variation due to
moderate amount of noise &
edge transition due to low
amount of noise added.

Injecting controlled amount of Rj + Dj noise


into HS data device
• Stress test circuitry to withstand rigors of HS transmission
• Determine a more accurate jitter budget.
Available Products

• Jitter Products -
Module

• Jitter Products -
Instrument
Module Jitter Products

• Part of system or instrument

• Could be BITE, or full-size module


• Require DC supply voltage for operation
• Some models include attenuation capability and
gated input

• Control Signal Source


 An External Source
 TTL Type Switching
NC1000 Series

• Control Signal Source


 Bandwidth
 Power Output

• TTL Controlled
 Step Attenuators
 Burst Noise Switch

• Differential Output
Instrument Jitter Products

• Stand-alone or part of ATE system

• NC6000 series – manual control


 Requires AC Outlet Power

• PNG, UFX, and J series – computer control


 Requires AC Outlet Power
 Requires external computer for remote control
 Internal motherboard allows remote control of
switches, combiners, filters & additional sources
J7000 Series

• Precision Noise Generator

• A High Crest Factor of 7σ or 18 dB for


Jitter Testing

• 7.5 in color TFT Touch Screen Display

• Ethernet, & GPIB


Control
J9005A

Differential
Input

Variable -5dBm
Rj Noise Attenuator Differential
(10Mhz to 2.5Ghz) Max 80dB
Output

GPIB Dj Noise
Interface (Max 100Mhz)

An example solution for testing disk drive


components for SATA requirements
Jitter Applications

Who Can Benefit Using Noisecom Jitter Products?


• R&D – Developer for high speed serial data buses/chips
• Manufacturing Test Engineers
• Design Verification/Validation Test Engineers

Typical Test Requirements


• Test engineers responsible for validating the design of
chipsets and boards
 Main responsibility is to determine how “jitter-Tolerant” is
the designs.

• A typical user would be an engineer responsible for


product qualification.
Thank You for Participating
in Today’s Webinar

Any Questions?
WTG Regional Technical Contacts
for Additional Questions

• Mr. James Lim - [email protected]

• Mr. Tony Lin - Shanghai, China - [email protected]

• Mr. Steven Shaw - Manchester, UK - [email protected]

• Mr. Bob Muro - Parsippany, NJ - [email protected]

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