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Interface and Control Logic for ADPLL IP

The document outlines the interface and control logic for an ADPLL IP, proposing UART, SPI, and future ARM-AXI interfaces for configuration. It details the structure of the interfaces, including 16 registers for control and status, and describes the command word buffer and start of frame detection for data transfer. The default output from the interfaces is the LPF output, which can be modified based on commands to provide various register values.

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17 views

Interface and Control Logic for ADPLL IP

The document outlines the interface and control logic for an ADPLL IP, proposing UART, SPI, and future ARM-AXI interfaces for configuration. It details the structure of the interfaces, including 16 registers for control and status, and describes the command word buffer and start of frame detection for data transfer. The default output from the interfaces is the LPF output, which can be modified based on commands to provide various register values.

Uploaded by

ganniyadav9392
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Interface and Control Logic for ADPLL IP

Interfaces:
Following interfaces are proposed to be used.
1) UART
2) SPI
3) ARM - AXI Interface ( For Future Purpose) ( for final IP)

The purpose of the above block is to provide means for configuration of the proposed ADPLL IP.
The initial Values of the LPF coefficients, Frequency Divider and Band selection of the VCO
needs to be performed to configure the IP for the desired frequency applications.
SPI, UART ( in future AXI) interfaces are provided to configure the IP for desired applications.
UART / SPI Interface Structure:
The figure below presents the detailed block diagram of the Interface and control logic. It is
assumed that both the interfaces accept 8-bit data as input. A special Select pin provided to
select either the UART or SPI Interface.

There will be 16 registers in the ADPLL IP. Most of them are input registers and a few are output
registers. The width of each register is 16-bits. Each register is used to either control / provide
status information of the ADPLL IP Core.The Block needs a 4-Byte longCommand Register.

Command Word Buffer


The incoming command consists of a 16-bit command word followed by 16-bit data. ( in total
4-bytes). While incoming data is 1-byte at an instance.
A suitable protocol can be developed in this regard to transfer the command word using the SPI
or UARt 8-bit interface. It is assumed that a byte for frame identification is sent first, followed by
a 4-byte command word.
Start of Frame Detector
A start of frame detector is required to detect the beginning of a valid frame. Once detected. The
remaining / following bytes ca be stored in the Command Word Buffer

Read / Write Logic


A suitable Logic / FSM can be developed to read / write the register.

Default Output:
LPF output needs to be continuously sent as output from UARt and SPI Interface.
However, based on command this output can be changed to VCo frequency Count, A, B, Gain,
P, S register also.

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