Computer Organization

Unit – 2
Logic Gates

Nowadays, computers have become an integral part of life as they perform many tasks and operations in quite a
short span of time. One of the most important functions of the CPU in a computer is to perform logical operations by
utilizing hardware like Integrated Circuits, electronic circuits and software technologies. But, how these hardware and
software perform such operations is a mysterious puzzle. In order to have a better understanding of such a complex
issue, we must have to acquaint ourselves with the term Boolean Logic, developed by George Boole. For a simple
operation, computers utilize binary digits rather than digital digits. All the operations are carried out by the Basic Logic
gates.

Basic Logic Gates

What is Logic Gate

A logic gate is a basic building block of a digital circuit that has two inputs and one output. The relationship between
the i/p and the o/p is based on a certain logic. These gates are implemented using electronic switches like transistors,
diodes. But, in practice basic logic gates are built using CMOS technology, FETS and MOSFET(Metal Oxide
Semiconductor FET)s. Logic gates are used in microprocessors, microcontrollers, embedded system applications and in
electronic and electrical project circuits. The basic logic gates are categorized into seven: AND, OR, XOR, NAND,
NOR, XNOR and NOT. These logic gates with their logic gate symbols and truth tables are explained below.
Logic Gate
AND Gate
The AND gate is a digital logic gate with ‘n’ i/ps one o/p, which perform logical conjunction based on the combinations
of its inputs.The output of this gate is true only when all the inputs are true. When one or more inputs of the AND
gate’s i/ps are false, then only the output of the AND gate is false. The symbol and truth table of an AND gate with
two inputs is shown below.

AND Gate and its Truth Table

OR Gate
The OR gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs a logical conjunction based on the
combinations of its inputs.The output of the OR gate is true only when one or more inputs are true. If all the i/ps of the
gate are false, then only the output of the OR gate is false. The symbol and truth table of an OR gate with two inputs
is shown below.
OR Gate and its Truth Table
NOT Gate
The NOT gate is a digital logic gate with one input and one output that operates an inverter operation of the input.The
output of the NOT gate is the reverse of the input. When the input of the NOT gate is true then the output will be false
and vice versa. The symbol and truth table of a NOT gate with one input is shown below. By using this gate, we can
implement NOR and NAND gates

NAND Gate
The NAND gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs the operation of the AND gate followed
by the operation of the NOT gate.NAND gate is designed by combining the AND and NOT gates. If the input of the
NAND gate high, then the output of the gate will be low.The symbol and truth table of the NAND gate with two inputs
is shown below.
NOR Gate
The NOR gate is a digital logic gate with n inputs and one output, that performs the operation of the OR gate followed
by the NOT gate. NOR gate is designed by combining the OR and NOT gate. When any one of the i/ps of the NOR
gate is true, then the output of the NOR gate will be false. The symbol and truth table of the NOR gate with truth table
is shown below.

Exclusive-OR Gate
The Exclusive-OR gate is a digital logic gate with two inputs and one output. The short form of this gate is Ex-OR. It
performs based on the operation of OR gate. . If any one of the inputs of this gate is high, then the output of the EX-
OR gate will be high. The symbol and truth table of the EX-OR are shown below.
Exclusive-NOR Gate
The Exclusive-NOR gate is a digital logic gate with two inputs and one output. The short form of this gate is Ex-NOR.
It performs based on the operation of NOR gate. When both the inputs of this gate are high, then the output of the
EX-NOR gate will be high. But, if any one of the inputs is high (but not both), then the output will be low. The symbol
and truth table of the EX-NOR are shown below.

The applications of logic gates are mainly determined based upon their truth table, i.e., their mode of operations. The
basic logic gates are used in many circuits like a push-button lock, light-activated burglar alarm safety thermostat, an
automatic watering system, etc.
By using mixtures of basic logic gates, advanced operations are often performed. In theory, there’s no limit to the
quantity of gates that may be clad along during a single device. However, in application, there’s a limit to the quantity
of gates that may be packed into a given physical area. Arrays of the logic gate area unit are found in digital
integrated circuits (ICs). As IC technology advances, the desired physical volume for every individual gate decreases
and digital devices of an equivalent or smaller size become capable of activity with more complicated operations at
ever-increasing speeds.
This is all about the basic logic gates, which includes AND gate, OR gate, NAND gate, NOR gate, EX-OR gate and
EX-NOR gate. In this, AND, NOT and OR gates are the basic logic gates. By using these gates we can create any
logic gate by combining them. Where, NAND and NOR gates are called universal gates. These gates have a
particular property with which they can create any logical Boolean expression if designed in a proper way.
Furthermore, for any queries regarding this article, or electronics projects.
Minterm vs Maxterm Solution
So far we have been finding Sum-Of-Product (SOP) solutions to logic reduction problems. For each of these SOP
solutions, there is also a Product-Of-Sums solution (POS), which could be more useful, depending on the
application. Before working a Product-Of-Sums solution, we need to introduce some new terminology. The
procedure below for mapping product terms is not new to this chapter. We just want to establish a formal procedure
for minterms for comparison to the new procedure for maxterms.

A minterm is a Boolean expression resulting in 1 for the output of a single cell, and 0s for all other cells in a
Karnaugh map, or truth table. If a minterm has a single 1 and the remaining cells as 0s, it would appear to cover a
minimum area of 1s. The illustration above left shows the minterm ABC, a single product term, as a single 1 in a
map that is otherwise 0s. We have not shown the 0s in our Karnaugh maps up to this point, as it is customary to
omit them unless specifically needed. Another minterm A’BC’ is shown above right. The point to review is that the
address of the cell corresponds directly to the minterm being mapped. That is, the cell 111 corresponds to the
minterm ABC above left. Above right we see that the minterm A’BC’corresponds directly to the cell 010. A Boolean
expression or map may have multiple minterms.
Referring to the above figure, Let’s summarize the procedure for placing a minterm in a K-map:

 Identify the minterm (product term) term to be mapped.

 Write the corresponding binary numeric value.
 Use binary value as an address to place a 1 in the K-map
 Repeat steps for other minterms (P-terms within a Sum-Of-Products).
A Boolean expression will more often than not consist of multiple minterms corresponding to multiple cells in a
Karnaugh map as shown above. The multiple minterms in this map are the individual minterms which we examined
in the previous figure above. The point we review for reference is that the 1s come out of the K-map as a binary cell
address which converts directly to one or more product terms. By directly we mean that a 0corresponds to a
complemented variable, and a 1 corresponds to a true variable. Example: 010 converts directly to A’BC’. There
was no reduction in this example. Though, we do have a Sum-Of-Products result from the minterms.
Referring to the above figure, Let’s summarize the procedure for writing the Sum-Of-Products reduced Boolean
equation from a K-map:

 Form largest groups of 1s possible covering all minterms. Groups must be a power of 2.
 Write binary numeric value for groups.
 Convert binary value to a product term.
 Repeat steps for other groups. Each group yields a p-terms within a Sum-Of-Products.

Nothing new so far, a formal procedure has been written down for dealing with minterms. This serves as a pattern
for dealing with maxterms.
Next we attack the Boolean function which is 0 for a single cell and 1s for all others.

A maxterm is a Boolean expression resulting in a 0 for the output of a single cell expression, and 1s for all other
cells in the Karnaugh map, or truth table. The illustration above left shows the maxterm (A+B+C), a single sum
term, as a single 0 in a map that is otherwise 1s. If a maxterm has a single 0 and the remaining cells as 1s, it would
appear to cover a maximum area of 1s.
There are some differences now that we are dealing with something new, maxterms. The maxterm is a 0, not a 1 in
the Karnaugh map. A maxterm is a sum term, (A+B+C) in our example, not a product term.
It also looks strange that (A+B+C) is mapped into the cell 000. For the equation Out=(A+B+C)=0, all three
variables (A, B, C) must individually be equal to 0. Only (0+0+0)=0 will equal 0. Thus we place our sole 0 for
minterm (A+B+C) in cell A,B,C=000 in the K-map, where the inputs are all0. This is the only case which will give us
a 0 for our maxterm. All other cells contain 1s because any input values other than ((0,0,0) for (A+B+C) yields 1s
upon evaluation.
Referring to the above figure, the procedure for placing a maxterm in the K-map is:

 Identify the Sum term to be mapped.

 Write corresponding binary numeric value.
 Form the complement
 Use the complement as an address to place a 0 in the K-map
 Repeat for other maxterms (Sum terms within Product-of-Sums expression).
Another maxterm A’+B’+C’ is shown above. Numeric 000 corresponds to A’+B’+C’. The complement is 111. Place
a 0 for maxterm (A’+B’+C’) in this cell (1,1,1) of the K-map as shown above.
Why should (A’+B’+C’) cause a 0 to be in cell 111? When A’+B’+C’ is (1’+1’+1’), all 1s in, which is (0+0+0) after
taking complements, we have the only condition that will give us a 0. All the 1s are complemented to all 0s, which
is 0 when ORed.

A Boolean Product-Of-Sums expression or map may have multiple maxterms as shown above.
Maxterm (A+B+C) yields numeric 111 which complements to 000, placing a 0 in cell (0,0,0).
Maxterm (A+B+C’) yields numeric 110 which complements to 001, placing a 0 in cell (0,0,1).
Now that we have the k-map setup, what we are really interested in is showing how to write a Product-Of-Sums
reduction. Form the 0s into groups. That would be a group of two below. Write the binary value corresponding to
the sum-term which is (0,0,X). Both A and B are 0 for the group. But, C is both 0 and 1 so we write an X as a place
holder for C. Form the complement (1,1,X). Write the Sum-term (A+B) discarding the Cand the X which held its’
place. In general, expect to have more sum-terms multiplied together in the Product-Of-Sums result. Though, we
have a simple example here.
Let’s summarize the procedure for writing the Product-Of-Sums Boolean reduction for a K-map:

 Form largest groups of 0s possible, covering all maxterms. Groups must be a power of 2.
 Write binary numeric value for group.
 Complement binary numeric value for group.
 Convert complement value to a sum-term.
 Repeat steps for other groups. Each group yields a sum-term within a Product-Of-Sums result.

Example:
Simplify the Product-Of-Sums Boolean expression below, providing a result in POS form.

Solution:
Transfer the seven maxterms to the map below as 0s. Be sure to complement the input variables in finding the
proper cell location.
We map the 0s as they appear left to right top to bottom on the map above. We locate the last three maxterms with
leader lines..
Once the cells are in place above, form groups of cells as shown below. Larger groups will give a sum-term with
fewer inputs. Fewer groups will yield fewer sum-terms in the result.

We have three groups, so we expect to have three sum-terms in our POS result above. The group of 4-cells yields
a 2-variable sum-term. The two groups of 2-cells give us two 3-variable sum-terms. Details are shown for how we
arrived at the Sum-terms above. For a group, write the binary group input address, then complement it, converting
that to the Boolean sum-term. The final result is product of the three sums.
Example:
Simplify the Product-Of-Sums Boolean expression below, providing a result in SOP form.

Solution:
This looks like a repeat of the last problem. It is except that we ask for a Sum-Of-Products Solution instead of the
Product-Of-Sums which we just finished. Map the maxterm 0s from the Product-Of-Sums given as in the previous
problem, below left.

Then fill in the implied 1s in the remaining cells of the map above right.
Form groups of 1s to cover all 1s. Then write the Sum-Of-Products simplified result as in the previous section of
this chapter. This is identical to a previous problem.

Above we show both the Product-Of-Sums solution, from the previous example, and the Sum-Of-Products solution
from the current problem for comparison. Which is the simpler solution? The POS uses 3-OR gates and 1-AND
gate, while the SOP uses 3-AND gates and 1-OR gate. Both use four gates each. Taking a closer look, we count
the number of gate inputs. The POS uses 8-inputs; the SOP uses 7-inputs. By the definition of minimal cost
solution, the SOP solution is simpler. This is an example of a technically correct answer that is of little use in the
real world.
The better solution depends on complexity and the logic family being used. The SOP solution is usually better if
using the TTL logic family, as NAND gates are the basic building block, which works well with SOP
implementations. On the other hand, A POS solution would be acceptable when using the CMOS logic family since
all sizes of NOR gates are available.
The gate diagrams for both cases are shown above, Product-Of-Sums left, and Sum-Of-Products right.
Below, we take a closer look at the Sum-Of-Products version of our example logic, which is repeated at left.

Above all AND gates at left have been replaced by NAND gates at right.. The OR gate at the output is replaced by
a NAND gate. To prove that AND-OR logic is equivalent to NAND-NAND logic, move the inverter invert bubbles at
the output of the 3-NAND gates to the input of the final NAND as shown in going from above right to below left.

Above right we see that the output NAND gate with inverted inputs is logically equivalent to an OR gate by
DeMorgan’s theorem and double negation. This information is useful in building digital logic in a laboratory setting
where TTL logic family NAND gates are more readily available in a wide variety of configurations than other types.
The Procedure for constructing NAND-NAND logic, in place of AND-OR logic is as follows:
  Produce a reduced Sum-Of-Products logic design.
 When drawing the wiring diagram of the SOP, replace all gates (both AND and OR) with NAND gates.
 Unused inputs should be tied to logic High.
 In case of troubleshooting, internal nodes at the first level of NAND gate outputs do NOT match AND-OR
diagram logic levels, but are inverted. Use the NAND-NAND logic diagram. Inputs and final output are
identical, though.
 Label any multiple packages U1, U2,.. etc.
 Use data sheet to assign pin numbers to inputs and outputs of all gates.

Example:
Let us revisit a previous problem involving an SOP minimization. Produce a Product-Of-Sums solution. Compare
the POS solution to the previous SOP.

Solution:
Above left we have the original problem starting with a 9-minterm Boolean unsimplified expression. Reviewing, we
formed four groups of 4-cells to yield a 4-product-term SOP result, lower left.
In the middle figure, above, we fill in the empty spaces with the implied 0s. The 0s form two groups of 4-cells. The
solid blue group is (A’+B), the dashed red group is (C’+D). This yields two sum-terms in the Product-Of-Sums
result, above right Out = (A’+B)(C’+D)
Comparing the previous SOP simplification, left, to the POS simplification, right, shows that the POS is the least
cost solution. The SOP uses 5-gates total, the POS uses only 3-gates. This POS solution even looks attractive
when using TTL logic due to simplicity of the result. We can find AND gates and an OR gate with 2-inputs.
The SOP and POS gate diagrams are shown above for our comparison problem.
Given the pin-outs for the TTL logic family integrated circuit gates below, label the maxterm diagram above right
with Circuit designators (U1-a, U1-b, U2-a, etc), and pin numbers.

Each integrated circuit package that we use will receive a circuit designator: U1, U2, U3. To distinguish between
the individual gates within the package, they are identified as a, b, c, d, etc. The 7404 hex-inverter package is U1.
The individual inverters in it are are U1-a, U1-b, U1-c, etc. U2 is assigned to the 7432 quad OR gate. U3 is
assigned to the 7408 quad AND gate. With reference to the pin numbers on the package diagram above, we assign
pin numbers to all gate inputs and outputs on the schematic diagram below.
We can now build this circuit in a laboratory setting. Or, we could design a printed circuit board for it. A printed
circuit board contains copper foil “wiring” backed by a non conductive substrate of phenolic, or epoxy-fiberglass.
Printed circuit boards are used to mass produce electronic circuits. Ground the inputs of unused gates.

Label the previous POS solution diagram above left (third figure back) with Circuit designators and pin numbers.
This will be similar to what we just did.

We can find 2-input AND gates, 7408 in the previous example. However, we have trouble finding a 4-input OR gate
in our TTL catalog. The only kind of gate with 4-inputs is the 7420 NAND gate shown above right.
We can make the 4-input NAND gate into a 4-input OR gate by inverting the inputs to the NAND gate as shown
below. So we will use the 7420 4-input NAND gate as an OR gate by inverting the inputs.

We will not use discrete inverters to invert the inputs to the 7420 4-input NAND gate, but will drive it with 2-input
NAND gates in place of the AND gates called for in the SOP, minterm, solution. The inversion at the output of the
2-input NAND gates supply the inversion for the 4-input OR gate.
The result is shown above. It is the only practical way to actually build it with TTL gates by using NAND-NAND logic
replacing AND-OR logic.

Simplification Of Boolean Functions

Simplification Using Algebraic Functions

In this approach, one Boolean expression is minimized into an equivalent
expression by applying Boolean identities.

Problem 1
Minimize the following Boolean expression using Boolean identities −
[Math Processing Error]F(A,B,C)=A′B+BC′+BC+AB′C′

Solution
Given,[Math Processing Error]F(A,B,C)=A′B+BC′+BC+AB′C′
Or,[Math Processing Error]F(A,B,C)=A′B+(BC′+BC′)+BC+AB′C′
[By idempotent law, BC’ = BC’ + BC’]
Or,[Math Processing Error]F(A,B,C)=A′B+(BC′+BC)+(BC′+AB′C′)
Or,[Math Processing Error]F(A,B,C)=A′B+B(C′+C)+C′(B+AB′)
[By distributive laws]
Or,[Math Processing Error]F(A,B,C)=A′B+B.1+C′(B+A)
[ (C' + C) = 1 and absorption law (B + AB')= (B + A)]
Or,[Math Processing Error]F(A,B,C)=A′B+B+C′(B+A)
[ B.1 = B ]
Or,[Math Processing Error]F(A,B,C)=B(A′+1)+C′(B+A)
Or,[Math Processing Error]F(A,B,C)=B.1+C′(B+A)
[ (A' + 1) = 1 ]
Or,[Math Processing Error]F(A,B,C)=B+C′(B+A)
[ As, B.1 = B ]
Or,[Math Processing Error]F(A,B,C)=B+BC′+AC′
Or,[Math Processing Error]F(A,B,C)=B(1+C′)+AC′
Or,[Math Processing Error]F(A,B,C)=B.1+AC′
[As, (1 + C') = 1]
Or,[Math Processing Error]F(A,B,C)=B+AC′
[As, B.1 = B]
So,[Math Processing Error]F(A,B,C)=B+AC′is the minimized form.

Problem 2
Minimize the following Boolean expression using Boolean identities −
[Math Processing Error]F(A,B,C)=(A+B)(B+C)

Solution
Given, [Math Processing Error]F(A,B,C)=(A+B)(A+C)
Or, [Math Processing Error]F(A,B,C)=A.A+A.C+B.A+B.C [Applying
distributive Rule]
Or, [Math Processing Error]F(A,B,C)=A+A.C+B.A+B.C [Applying
Idempotent Law]
Or, [Math Processing Error]F(A,B,C)=A(1+C)+B.A+B.C [Applying
distributive Law]
Or, [Math Processing Error]F(A,B,C)=A+B.A+B.C [Applying dominance Law]
Or, [Math Processing Error]F(A,B,C)=(A+1).A+B.C [Applying distributive
Law]
Or, [Math Processing Error]F(A,B,C)=1.A+B.C [Applying dominance Law]
Or, [Math Processing Error]F(A,B,C)=A+B.C [Applying dominance Law]
So, [Math Processing Error]F(A,B,C)=A+BC is the minimized form.

Karnaugh Maps
The Karnaugh map (K–map), introduced by Maurice Karnaughin in 1953, is
a grid-like representation of a truth table which is used to simplify boolean
algebra expressions. A Karnaugh map has zero and one entries at different
positions. It provides grouping together Boolean expressions with common
factors and eliminates unwanted variables from the expression. In a K-map,
crossing a vertical or horizontal cell boundary is always a change of only
one variable.

Example 1
An arbitrary truth table is taken below −
A B A operation B

0 0 w

0 1 x

1 0 y

1 1 z

Now we will make a k-map for the above truth table −

Example 2
Now we will make a K-map for the expression − AB+ A’B’
Simplification Using K-map
K-map uses some rules for the simplification of Boolean expressions by
combining together adjacent cells into single term. The rules are described
below −
Rule 1 − Any cell containing a zero cannot be grouped.

Wrong grouping
Rule 2 − Groups must contain 2n cells (n starting from 1).

Wrong grouping
Rule 3 − Grouping must be horizontal or vertical, but must not be diagonal.
 Wrong diagonal grouping

Proper vertical grouping

Proper horizontal grouping

Rule 4 − Groups must be covered as largely as possible.
 Insufficient grouping

Proper grouping
Rule 5 − If 1 of any cell cannot be grouped with any other cell, it will act as
a group itself.

Proper grouping
Rule 6 − Groups may overlap but there should be as few groups as
possible.

Proper grouping
Rule 7 − The leftmost cell/cells can be grouped with the rightmost cell/cells
and the topmost cell/cells can be grouped with the bottommost cell/cells.
 Proper grouping

Problem
Minimize the following Boolean expression using K-map −
[Math Processing Error]F(A,B,C)=A′BC+A′BC′+AB′C′+AB′C

Solution
Each term is put into k-map and we get the following −

K-map for F (A, B, C)

Now we will group the cells of 1 according to the rules stated above −

K-map for F (A, B, C)

We have got two groups which are termed as [Math Processing
Error]A′B and [Math Processing Error]AB′. Hence, [Math Processing
Error]F(A,B,C)=A′B+AB′=A⊕B. It is the minimized form.

Half Adder and Full Adder with Truth Table

An adder is a digital logic circuit in electronics that implements addition of numbers. In many computers and other
types of processors, adders are used to calculate addresses, similar operations and table indices in the ALU and also
in other parts of the processors. These can be built for many numerical representations like excess-3 or binary coded
decimal. Adders are classified into two types: half adder and full adder. The half adder circuit has two inputs: A and B,
which add two input digits and generate a carry and sum. The full adder circuit has three inputs: A and C, which add
the three input numbers and generate a carry and sum. This article gives brief information about half adder and full
adder in tabular forms and circuit diagrams.

Half Adder and Full Adder Circuit

An adder is a digital circuit that performs addition of numbers. The half adder adds two binary digits called as augend
and addend and produces two outputs as sum and carry; XOR is applied to both inputs to produce sum and AND
gate is applied to both inputs to produce carry. The full adder adds 3 one bit numbers, where two can be referred to
as operands and one can be referred to as bit carried in. And produces 2-bit output, and these can be referred to as
output carry and sum.

Half Adder
By using half adder, you can design simple addition with the help of logic gates.

Let’s see an addition of single bits.

0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 10

These are the least possible single-bit combinations. But the result for 1+1 is 10, the sum result must be re-written as
a 2-bit output. Thus, the equations can be written as
0+0 = 00
0+1 = 01
1+0 = 01
1+1 = 10

The output ‘1’of ‘10’ is carry-out. ‘SUM’ is the normal output and ‘CARRY’ is the carry-out.

Half Adder Truth Table

Half Adder Truth Table

Now it has been cleared that 1-bit adder can be easily implemented with the help of the XOR Gate for the output
‘SUM’ and an AND Gate for the ‘Carry’. When we need to add, two 8-bit bytes together, we can be done with the help
of a full-adder logic. The half-adder is useful when you want to add one binary digit quantities. A way to develop a
two-binary digit adders would be to make a truth table and reduce it. When you want to make a three binary digit
adder, do it again. When you decide to make a four digit adder, do it again. The circuits would be fast, but
development time is slow.

Half Adder Logic Circuit

The simplest expression uses the exclusive OR function: Sum=AÅB. An equivalent expression in terms of the basic
AND, OR, and NOT is: SUM=A|.B+A.B’

Decoder
The process of taking some type of code and determining what it represents in
terms of a recognizable number or character is called decoding. A decoder is a
combinational logic circuit that performs the decoding function, and produce an
output that indicates the (meaning) of the input code.
The decoder is an important part of the system which selects the cells to be read
from and write into. This particular circuit is called a decoder matrix, or simply a
decoder, and has a characteristic that for each of the possible 2n binary input
number which can be taken by the n input cells, the matrix will have a unique one
of its 2n output lines selected.
Input Output
1
The decoder is called n to m where m < 2n for example two to four line decoder,
Fig. (1) shows a two to four line decoder and its truth table.
2. Encoder
An encoder is a combinational logic circuit that generate n output lines from 2 n (or
less) inputs. It has the reverse function of the decoder.

Input Output
An encoder accepts digit on its inputs, such as a decimal or octal digit, and
converts it to a coded output, such as a binary or BCD. Encoder can also be
devised to encode various symbol and alphabetic characters. This process of
converting from familiar symbols or numbers to a coded format is called encoding.
Figure shown a four to two line encoder and its truth table.

Multiplexer and De-multiplexer Circuit and

Applications
1.Multiplexer
Multiplexer is a device that has multiple inputs and a single line output. The select lines determine which input is
connected to the output, and also to increase the amount of data that can be sent over a network within certain time.
It is also called a data selector.
The single pole multi-position switch is a simple example of non-electronic circuit of multiplexer, and it is widely used
in many electronic circuits. The multiplexer is used to perform high-speed switching and is constructed by electronic
components.
Multiplexers are capable of handling both analog and digital applications. In analog applications, multiplexers are made
up of of relays and transistor switches, whereas in digital applications, the multiplexers are built from standard logic
gates. When the multiplexer is used for digital applications, it is called a digital multiplexer.

Multiplexer Types
8-to-1 Multiplexer

The 8-to-1 multiplexer consists of 8 input lines, one output line and 3 selection lines.

8-1 Multiplexer Circuit

For the combination of selection input, the data line is connected to the output line. The circuit shown below is an 8*1
multiplexer. The 8-to-1 multiplexer requires 8 AND gates, one OR gate and 3 selection lines. As an input, the
combination of selection inputs are giving to the AND gate with the corresponding input data lines.

In a similar fashion, all the AND gates are given connection. In this 8*1 multiplexer, for any selection line input, one
AND gate gives a value of 1 and the remaining all AND gates give 0. And, finally, by using OR gate, all the AND
gates are added; and, this will be equal to the selected value.
 Applications of Multiplexers
Multiplexers are used in various applications wherein multiple-data need to be transmitted by using single line.

 Communication System
A communication system has both a communication network and a transmission system. By using a multiplexer,
the efficiency of the communication system can be increased by allowing the transmission of data, such as audio and
video data from different channels through single lines or cables.
 Computer Memory
Multiplexers are used in computer memory to maintain a huge amount of memory in the computers, and also to
reduce the number of copper lines required to connect the memory to other parts of the computer.

 Telephone Network
 In telephone networks, multiple audio signals are integrated on a single line of transmission with the help of a
multiplexer.

 Transmission from the Computer System of a Satellite

Multiplexer is used to transmit the data signals from the computer system of a spacecraft or a satellite to the ground
system by using a GSM satellite.
De-multiplexer
De-multiplexer is also a device with one input and multiple output lines. It is used to send a signal to one of the many
devices. The main difference between a multiplexer and a de-multiplexer is that a multiplexer takes two or more
signals and encodes them on a wire, whereas a de-multiplexer does reverse to what the multiplexer does.

Types of De multiplexer
De-multiplexers are classified into four types

 1-2 demultiplexer (1 select line)

 1-4 demultiplexer (2 select lines)
 1-8 demultiplexer (3 select lines)
 1-16 demultiplexer (4 select lines)
1-8 De-multiplexers
The demultiplexer is also called as data distributors as it requires one input, 3 selected lines and 8 outputs. De-
multiplexer takes one single input data line, and then switches it to any one of the output line. 1-to-8 demultiplexer
circuit diagram is shown below; it uses 8 AND gates for achieving the operation. The input bit is considered as data D
and it is transmitted to the output lines. This depends on the control input value of the AB. When AB = 01, the upper
second gate F1 is enabled, while the remaining AND gates are disabled, and the data bit is transmitted to the output
giving F1= data. If D is low, the F1 is low, and if D is high, the F1 is high. So the value of the F1 depends on the value
of D, and the remaining outputs are in low state.
 Applications of De multiplexer
De multiplexers are used to connect a single source to multiple destinations. These applications include the following:

 Communication System
Mux and demux both are used in communication system to carry out the process of data transmission. A De-multiplexer
receives the output signals from the multiplexer and at the receiver end it converts them back to the original form.
 Arithmetic Logic Unit
The output of the ALU is fed as an input to the De-multiplexer, and the output of the demultiplexer is connected to a
multiple register. The output of the ALU can be stored in multiple registers.

 Serial to Parallel Converter

This converter is used to reconstruct parallel data. In this technique, serial data is given as an input to the De-
multiplexer at a regular interval, and a counter is attached to the demultiplexer at the control input to detect the data
signal at the output of the demultiplexer. When all data signals are stored, the output of the demux can be read out in
parallel.

Binary Counters

A binary counter can be constructed from J-K flip-flops by taking the output of one
cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to
produce a toggle at each cycle of the clock input. For each two toggles of the first cell,
a toggle is produced in the second cell, and so on down to the fourth cell. This
produces a binary number equal to the number of cycles of the input clock signal. This
device is sometimes called a "ripple through" counter. The same device is useful as
a frequency divider.
 Flip-Flops

"Flip-flop" is the common name given to two-state devices which offer basic memory for sequential
logic operations. Flip-flops are heavily used for digital data storage and transfer and are commonly used
in banks called "registers" for the storage of binary numerical data.