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The document describes the architecture and functioning of a hypothetical 16-bit processor, detailing its key registers: Accumulator (Ac), Program Counter (PC), and Instruction Register (IR). It outlines the instruction format, which includes a 4-bit opcode and a 12-bit address/operand, allowing for 16 opcodes and 4096 addressable memory locations. The document also explains the instruction cycle consisting of fetch, decode, and execute phases, along with examples of operations such as LOAD, ADD, and STORE.

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statghoul
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12 views

note2

The document describes the architecture and functioning of a hypothetical 16-bit processor, detailing its key registers: Accumulator (Ac), Program Counter (PC), and Instruction Register (IR). It outlines the instruction format, which includes a 4-bit opcode and a 12-bit address/operand, allowing for 16 opcodes and 4096 addressable memory locations. The document also explains the instruction cycle consisting of fetch, decode, and execute phases, along with examples of operations such as LOAD, ADD, and STORE.

Uploaded by

statghoul
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1.

Computer function

Hypothetical machine

Processor 16 bit resgister :

Ac (Accumulator Register)

 A special-purpose register used for arithmetic and logic operations.

 Typically, results of operations are stored here.

 Often interacts with the ALU (Arithmetic Logic Unit).

Pc (Program Counter)

 Holds the memory address of the next instruction to be executed.

 Increments after fetching an instruction unless modified by a jump or


branch instruction.

IR (Instruction Register)

 Temporarily holds the instruction currently being executed.

 Typically, instructions are fetched from memory and loaded into the IR
before being decoded and executed.

For your hypothetical 16-bit processor, you need an instruction format


that includes an opcode (operation code) and an address (or
operand). Since your processor has a 16-bit instruction register (IR),
we need to decide how the bits are allocated.

Basic Instruction Format (16-bit)

A common way to split a 16-bit instruction is:

Bit
Field Description
s

Operation to perform (e.g., ADD, SUB,


4 Opcode
LOAD, STORE)

Address/
12 Memory address or immediate value
Operand

This format allows for:

 16 possible opcodes (since 4 bits allow values from 0 to 15).


 4096 (2¹²) addressable memory locations if using direct
addressing.

 Instruction cycle

o Fetch

o Decode

o Execute

1. Fetch Cycle
The fetch cycle retrieves the next instruction from memory and loads it into the Instruction
Register (IR).

Steps:

1. Read instruction from memory


o MAR ← PC (Load the memory address from the Program Counter)
o Read Memory (Retrieve instruction from memory at MAR)
o IR ← MDR (Move fetched instruction to Instruction Register)
2. Increment Program Counter
o PC ← PC + 1 (Point to the next instruction in memory)

2. Decode Cycle
The CPU decodes the instruction stored in the Instruction Register (IR).

Steps:

1. Extract Opcode and Address/Operand


o Opcode ← IR[15:12] (Extract the first 4 bits as the opcode)
o Address/Operand ← IR[11:0] (Extract the remaining 12 bits as the operand)
2. Determine the operation
o The control unit interprets the opcode and determines the next action (e.g., Load,
Add, Store, Jump, etc.).
3. Execute Cycle
The CPU performs the operation based on the decoded instruction.

Examples of Execution Steps:

(a) LOAD Ac, [Address]

 MAR ← Address (Move address to Memory Address Register)


 Read Memory (Retrieve data from memory at MAR)
 Ac ← MDR (Store data in Accumulator)

(b) ADD Ac, [Address]

 MAR ← Address
 Read Memory
 Ac ← Ac + MDR (Perform addition)

(c) STORE Ac, [Address]

 MAR ← Address
 MDR ← Ac
 Write Memory (Store value from Accumulator to memory)

(d) JUMP Address (Branch Instruction)

 PC ← Address (Set program counter to new location)

 Polling/Interrupt

 Interrupt handling

2. Interconnections

 Memory module

 IO module

 Processor module

 Bus structure

 Bus hierarchy

 Computer buses

 Intel QPI
 PCIe

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