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This document is an examination question paper for the B.E. / B.Tech. degree in Electronics and Communication Engineering, specifically for the Digital Signal Processing course. It includes various questions divided into two parts, with Part A consisting of short answer questions and Part B containing detailed problems to solve. The exam is scheduled for November/December 2023, lasting 3 hours and worth a total of 100 marks.

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K.K.R
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© © All Rights Reserved
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0% found this document useful (0 votes)
2 views

20281

This document is an examination question paper for the B.E. / B.Tech. degree in Electronics and Communication Engineering, specifically for the Digital Signal Processing course. It includes various questions divided into two parts, with Part A consisting of short answer questions and Part B containing detailed problems to solve. The exam is scheduled for November/December 2023, lasting 3 hours and worth a total of 100 marks.

Uploaded by

K.K.R
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Reg. No.

9 5 1 7

Question Paper Code : 20281

B.E. / B.TECH. DEGREE EXAMINATIONS, NOVEMBER / DECEMBER 2023


Fifth Semester
B.E. – Electronics and Communication Engineering
19EC501 – DIGITAL SIGNAL PROCESSING
(Regulations: Mepco – R2019)
Duration: 3 Hours Max. : 100 Marks
Answer ALL Questions
PART A – (10  2 = 20 Marks)
BTL, CO

Apply bilinear transformation to H s   with T = 1 sec and find H z 


A, CO1 1. 2
s  1
A, CO1 2. Given the specifications  p  3 dB ;  s  40 dB ;  p  1000 rad / sec and

s  2000 rad / sec , the order of the Butterworth filter is ________. Justify
your answer.
A) 3 B) 5 C) 7 D) 9
A, CO2 3. The phase delay and group delay of the FIR filter defined by the difference
equation yn  0.25xn  xn  1  0.25xn  2 are _________. Justify your
answer.
A) 3,2 B) 5,5 C) 2,4 D)1,1
A, CO2 4. Draw the direct form realization of the system function
H z   1  2 z 1  3z 2  4 z 3  5z 4
U, CO3 5. Obtain the expression for mean of error in Two’s complement round-off
quantization.
U, CO3 6. Find the incorrect statement about the Floating point arithmetic. Justify your
answer.
A) Overflow does not arise B) Increased dynamic range
C) Fast operation D) Used in larger, general purpose computers
A, CO4 7. Is y1 n  y2 n ? Justify your answer.

xn

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xn y2 n

A, CO4 8. Down sampling by a factor D skips __________. Justify your answer.


A) D samples B) D-1 samples C) No samples D) D/2 samples
U, CO5 9. VLIW architecture differs from conventional P-DSP in which of the following
aspects: Justify your answer.
A) Instruction cache
B) Number of functional units
C) Use pipelining
D) A single word fetched from memory has a number of instructions.
U, CO5 10. How modified Harvard architecture differs from Harvard architecture?

PART B – (5  16 = 80 Marks)
A, CO1 11. a) Design a Butterworth filter using the Impulse Invariant method
for the following specifications:
 
0.8  H e j  1 ; 0    0.2
H e   0.2 ; 0.6    
j

Realize the above filter using Direct form I realization. (16 Marks)
OR
A, CO1 11. b) Determine the system function H z  of the lowest order
Chebyshev filter with the following specifications:
A) 3 dB ripple in passband 0    0.2
B) 25 dB attenuation in stopband 0.45    
Use Bilinear transformation with T = 1 sec. (16 Marks)

A, CO2 12. a) i. Using frequency sampling method, design a band pass filter with
the following specifications:
Sampling frequency F = 8000 Hz
Cut off frequency f c1 = 1000 Hz

Cut off frequency f c 2 = 3000 Hz


Determine the filter coefficients for N = 7 (10 Marks)

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A, CO2 12. a) ii. The length of an FIR filter is 7. If the filter has a linear phase,
M 1
prove that
 hnsin   n  0
n 0 (6 Marks)
OR
A, CO2 12. b) i. Design a low pass filter required with the desired frequency
response
  j 3 3
e ,  
H d (e )  
jw 4
0, 3
  
4
Obtain the filter coefficients h(n) using rectangular window
function. Also, find the frequency response of the designed filter. (10 Marks)
A, CO2 12. b) ii. Obtain cascade realization with minimum number of multipliers
1  1 
for the system function H z     z 1  z 2 1  z 1  z 2 
1
2 2  3  (6 Marks)

A, CO3 13. a) i. The output of an ADC is applied to a digital filter with the system

function H z  
0.5z
. Find the output noise power from the
z  0.5
digital filter, when the input signal is quantized to have 8 bits. (10 Marks)
U, CO3 13. a) ii. Derive the expression for input signal scaling and explain how
scaling can prevent overflow errors which occur when some
intermediate results exceed the range of numbers that can be
represented by the given word-length. (6 Marks)
OR
A, CO3 13. b) i. An LTI system is characterized by the difference equation
y(n)  0.87 y(n 1)  x(n). Determine the limit cycle behavior of
the system when x(n) = 0 and y(-1) = 0.61. Assume that the
product is quantized to 4 bits by rounding. (10 Marks)
U, CO3 13. b) ii. Derive the expression for steady state input noise power of a
system and obtain the expression for Dynamic Range (DR). (6 Marks)

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A, CO4 14. a) i. Find the polyphase decomposition of system
H ( z)  1  4 z 1  3z 2  6 z 3  9 z 4  5z 5  7 z 6 with decimation
factor M = 2 and realize the polyphase structure in Direct form
realization. Also, simplify the structure by sharing the delay
elements. (8 Marks)
A, CO4 14. a) ii.  
For the following interpolation process, draw V e j

Also, derive the input - output relationship in time domain


(general case) when the sampling rate of the input is increased by
an integer factor I. (8 Marks)
OR
A, CO4 14. b) i. Explain the sampling rate decrease by an integer factor D and
derive the input - output relationship in time domain. (8 Marks)
A, CO4 14. b) ii. For the multi rate system shown in figure find the relationship between
input and output

(8 Marks)

U, CO5 15. a) i. Explain the advanced addressing modes and describe how they
are used in DSP processor programming (10 Marks)
U, CO5 15. a) ii. Explain with illustration, how MAC operation is implemented in
DSP processor. (6 Marks)
OR
U, CO5 15. b) Draw the internal architecture diagram of TMS320C50 processor
and explain the function of all blocks. (16 Marks)

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