PCI express

- V L S I T E C H W I T H A N O U S H K A

Session 3
TLP Packet Disassembly in PCIe
Physical Layer Strips Off Transmission Bits

Physical Layer: First to handle the incoming TLP.

Checks Control Characters: Verifies start and end of
the packet.
Forwards Packet: Removes control characters and
passes the packet to the Data Link Layer.
TLP Packet Disassembly in PCIe
Data Link Layer Checks for Errors

• The Data Link Layer is responsible for ensuring

the packet arrived without errors.
• It does this by checking two things:
1. LCRC (Link Cyclic Redundancy Check): This
checks for transmission errors between the
neighboring devices (i.e., on the PCIe link).
2. Sequence Number: It checks the sequence number
to ensure packets are in the right order.
TLP Packet Disassembly in PCIe
Transaction Layer Processes the Core Packet

Transaction Layer: Processes the core packet

(header, data, ECRC).
Switches: Check the header to route the packet,
verify ECRC but don't modify it.
Target Device: Checks ECRC (if enabled) to
ensure error-free transmission.
Non-Posted Transactions in
PCI express
Non-Posted Transactions in PCI express
How the Data Finds its Way Back:
The request includes a return address with:
Bus number
Device number
Function number
(Together, these form the BDF—Bus, Device, Function—specifying where
to send completion packets.)
A unique Tag is included with each request to help match completion
packets with the correct request, especially when handling multiple
requests.
Handling Errors:
The Completer can set specific bits in the completion status field to indicate
an error.
Error handling depends on software, not the PCIe specification.
Non-Posted Transactions in PCI express : Locked Reads (Special Case)

Locked Reads (Special Case):

Purpose: Ensure a processor can access memory exclusively during
critical operations, like Atomic Read-Modify-Write.
Why Locked Reads Are Needed:
Atomic Operations:
Locks memory to prevent other devices from accessing it while a
processor modifies a critical variable, such as a semaphore.
Avoiding Race Conditions:
Prevents multiple processors from simultaneously modifying shared
memory, ensuring operations are completed one at a time.
IO and Configuration Writes
1. Targeting Legacy Endpoints: I/O writes are sent only to legacy-
compatible devices.
2. Routing the Request: Data travels through switches based on its
I/O address until it reaches the target device.
3. Acknowledgement of Data: The Completer device sends a status
confirmation (no data) back to the processor.
4. Error Handling: The processor’s software handles any errors that
occur.
5. Why Wait? Waiting prevents errors by ensuring the data is
delivered before the next operation.
6. Processor-Exclusive Writes: Only the processor can initiate non-
posted writes to manage these critical steps.
Quality of Service (QoS) in PCIe

The Problem:
Imagine a video camera and a file transfer device (like a
hard drive) both need to send data to your computer's
memory (DRAM).
• Video Camera Data: Needs to arrive on time, or the video
will become choppy or lose frames.
• File Transfer Data: Doesn’t care much about timing—it
just needs to arrive without errors.
Transaction Ordering
Key Points About Transaction Ordering:
1. Virtual Channels (VCs):
Packets within the same VC (lane for data) always follow the order they arrived in
unless specific "relaxed ordering" rules apply.
This keeps things organized and avoids conflicts.
2. Traffic Classes (TCs):
Packets with the same TC (priority level) are routed in order.
Packets with different TCs may not follow the same rules because they don’t share
an ordering relationship (they’re treated independently).
3. Why It Matters:
Ordering ensures the system operates efficiently without getting stuck or causing
errors.
For example, if a video packet (high-priority) is sent after a regular data packet, the
video packet might still be processed first due to its priority, but the system ensures
both packets reach their destinations without confusion.
Flow Control
Preventing Overflows and Ensuring Smooth Data Flow

How It Works (Flow Control):

Receiver Buffers: Hold incoming data packets (TLPs)
temporarily, which can fill up if overloaded.
Flow Control Updates: Receiver sends updates about
available buffer space using small Data Link Layer Packets
(DLLPs).
DLLP Usage: DLLPs can be sent even when buffers are
full, ensuring updates on buffer space are always
communicated.
Automatic Management: Handled entirely by hardware,
with no software intervention needed.
Data Link Layer Packets (DLLPs)
Key Functions of the Data Link Layer:
TLP Error Correction:
TLPs (Transaction Layer Packets) carry operation data.
Error detection uses LCRC codes. If an error is found, the receiver
sends a Nak, and the sender retransmits the TLP until an Ack is
received.
Flow Control:
Prevents sender from overloading the receiver.
Receiver updates buffer availability using DLLPs, which permit the
sender to transmit more data.
Power Management:
Manages power efficiency by signaling power state changes through
DLLPs.
Data Link Layer Packets (DLLPs)
Ack/Nak Protocol (Error Correction)
How It All Works in a System
 What is the Physical Layer?

It consists of two main parts:

1. Logical Physical Layer: Deals with digital
logic to prepare packets for transmission and
to process incoming packets.
2. Electrical Physical Layer: Handles the
actual analog signaling between devices over
the PCIe lanes.
How Data Travels Through the Physical Layer
Enumeration
Enumeration: Occurs during system startup.
Process: Scans, identifies devices, assigns bus numbers,
and allocates resources (memory, I/O space).
Same as PCI: Works similarly in both PCI and PCIe
systems, despite PCIe's complexity.
Result: Each device/bridge gets a bus number and can
communicate.
Purpose: Ensures devices know their position and how to
route transactions.