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Ch-05

Chapter 5 covers computer organization, detailing subsystems such as the CPU, main memory, and input/output. It discusses various components like ALU, cache memory, and different I/O methods including programmed I/O and DMA. The chapter also includes exercises and example programs demonstrating instruction handling and memory addressing.

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5 views

Ch-05

Chapter 5 covers computer organization, detailing subsystems such as the CPU, main memory, and input/output. It discusses various components like ALU, cache memory, and different I/O methods including programmed I/O and DMA. The chapter also includes exercises and example programs demonstrating instruction handling and memory addressing.

Uploaded by

Thabo Mojava
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CHAPTER 5

Computer Organization
(Solutions to Odd-Numbered Problems)

Review Questions
1. The three subsystems are the central processing unit (CPU), the main memory, and
the input/output.
3. The ALU performs arithmetic and logical operations.
5. The main memory stores data and programs when the program is being executed.
7. The cache memory provides the CPU with fast access to part of data stored in main
memory.
9. The surface of a magnetic disk is divided into circular rings called tracks. Each
track is divided into sections called sectors. The width of a magnetic tape is
divided into 9 tracks. The length of the tape may be divided into blocks.
11. An SCSI (small computer system interface) controller is a parallel interface that
provides a daisy chain connection between devices and the buses. The FireWire
interface is a high speed serial interface that transfers data in packets. It can use a
daisy chain or tree configuration. USB is a serial controller that connects both low
and high-speed devices to the computer bus. Multiple devices can be connected to
a USB controller.
13. In the programmed I/O method, the CPU waits for the I/O device. A lot of CPU
time is wasted by checking for the status of an I/O operation. In the interrupt-
driven I/O method, the I/O device informs the CPU of its status via an interrupt. In
direct memory access (DMA), the CPU sends its I/O requests to the DMA control-
ler which manages the entire transaction.
15. Pipelining allows different types of phases belonging to different cycles to be done
simultaneously. Pipelining can increase the throughput of the computer.

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2

Multiple-Choice Questions
17. a 19. a 21. d 23. c 25. b 27. a
29. b 31. b 33. b 35. c 37. c 39. a

Exercises
41. We have 64 MB /(4 bytes per word) = 16 Mega words = 16 × 220 = 24 × 220 = 224
words. Therefore, we need 24 bits to access memory words.
43. We need 4 bits to determine the instruction (24 = 16). We need 4 bits to address a
register (24 = 16). We need 10 bits to address a word in memory (210 = 1024). The
size of the instruction is therefore (4 + 4 + 10) or 18 bits.
45. The instruction register must be at least 18 bits (See solution to Exercise 43).
47. The data bus must be wide enough to carry the contents of one word in the mem-
ory. Therefore, it must be 18 bits (See Solution to Exercise 43).
49. The control bus should handle all instructions. The minimum size of the control
bus is therefore 4 bits (log216) (See Solution to Exercise 43).
51. The address bus uses 10 lines which means that it can address 210 = 1024 words.
Since the memory is made of 1000 words and the system uses shared (memory-
mapped I/O) addressing, 1024 − 1000 = 24 words are available for I/O controllers.
If each controller has 4 registers, then 24/4 = 6 controllers can be accessed in this
system.
53. Program S5-53 shows the instruction codes, the first column is not part of the
code; it contains instruction addresses for reference. We type A on the keyboard.
The program reads and stores it as we press the ENTER key.
Program S5-53

(00)16 (1FFE)16 // RF ← MFE, Input A from keyboard to RF


(01)16 (240F)16 // M40 ← RF, Store A in M40
(02)16 (1040)16 // M40 ← R0, Load A from M40 to R0
(03)16 (A000)16 // R0 ← R0 + 1, Increment A
(04)16 (A000)16 // R0 ← R0 + 1, Increment A
(05)16 (A000)16 // R0 ← R0 + 1, Increment A
(06)16 (2410)16 // M41 ← R0, Store The result in M41
(07)16 (1F41)16 // RF ← M41, Load the result to RF
(08)16 (2FFF)16 // MFF ← RF, Send the result to the monitor
(09)16 (0000)16 // Halt

55. Program S5-55 shows the instructions. The first column is not part of the code; it
contains the instruction addresses for reference. First, we type 0 and n (n has a
minimum value of 2) from the key board. The program reads and stores them in
registers R0 and R1 as we press the ENTER key. We then type the first number and
3

press ENTER. The program stores the first number in register R2. The program
then decrements R1 twice. We type the second number which is stored in register
R3. The program adds the content of R2 and R3 and stores the result in register R2.
The program then compares the value of R1 with R0, If they are the same, it dis-
plays the result on the monitor and halts; otherwise, it jumps back to the second
decrement statement and continues (instruction 04).
Program S5-55 Program for Exercise 55

(00)16 (10FE)16 // RF ← MFE, Input 0 from keyboard to R0


(01)16 (11FE)16 // RF ← MFE, Input n from keyboard to R1
(02)16 (12FE)16 // RF ← MFE, Input the first number to R2
(03)16 (B100)16 // R1 ← R1 − 1 Decrement R1
(04)16 (B100)16 // R1 ← R1 − 1 Decrement R1
(05)16 (13FE)16 // RF ← MFE, Input the next number to R3
(06)16 (3223)16 // R2 ← R2 + R3 Add R3 to R2 and store in R2
(07)16 (D104)16 // If R0 ≠ R1 the PC = 04, otherwise continue
(08)16 (2FF2)16 // MFF ← R2, Send the result to the monitor
(09)16 (0000)16 // Halt

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