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VHDL code for 41 MUx using 21 Mux

The document provides VHDL code for a 4 to 1 multiplexer (Mux) using both behavioral and structural models. The behavioral model defines the Mux's functionality based on select lines S0 and S1 to choose between four input signals A, B, C, and D. The structural model utilizes two 2 to 1 Mux components to construct the 4 to 1 Mux, demonstrating modular design in VHDL.

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anktech201
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6 views3 pages

VHDL code for 41 MUx using 21 Mux

The document provides VHDL code for a 4 to 1 multiplexer (Mux) using both behavioral and structural models. The behavioral model defines the Mux's functionality based on select lines S0 and S1 to choose between four input signals A, B, C, and D. The structural model utilizes two 2 to 1 Mux components to construct the 4 to 1 Mux, demonstrating modular design in VHDL.

Uploaded by

anktech201
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VHDL code for 4 to 1 Mux

Behavioral Model

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_4to1 is
port(

A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_4to1;

architecture bhv of mux_4to1 is


begin
process (A,B,C,D,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
Z <= A;
elsif (S0 ='1' and S1 = '0') then
Z <= B;
elsif (S0 ='0' and S1 = '1') then
Z <= C;
else
Z <= D;
end if;

end process;
end bhv;
Structural Model

VHDL Code for 2 to 1 Mux


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2_1 is
port(A,B : in STD_LOGIC;
S: in STD_LOGIC;
Z: out STD_LOGIC);
end mux2_1;

architecture Behavioral of mux2_1 is

begin

process (A,B,S) is
begin
if (S ='0') then
Z <= A;
else
Z <= B;
end if;
end process;

end Behavioral;

Structural Model for 4: 1 Mux

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4_1 is
port(

A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux4_1;

architecture Behavioral of mux4_1 is


component mux2_1
port( A,B : in STD_LOGIC;
S: in STD_LOGIC;
Z: out STD_LOGIC);
end component;
signal temp1, temp2: std_logic;

begin
m1: mux2_1 port map(A,B,S0,temp1);
m2: mux2_1 port map(C,D,S0,temp2);
m3: mux2_1 port map(temp1,temp2,S1,Z);

end Behavioral;

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