Developing and Assessinginexact

Multiplierarchitectures for Imageprocessing

Parthibaraj Anguraj

Thiruvenkadam Krishnan

Research Article

Keywords: Approximate computing, inexact multiplier, Partial product reduction circuitry, Design
parameter, picture multiplication and picture sharpening

Posted Date: June 6th, 2024

DOI: https://doi.org/10.21203/rs.3.rs-4476303/v1

License:   This work is licensed under a Creative Commons Attribution 4.0 International License.
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Additional Declarations: No competing interests reported.

 Springer Nature 2021 LATEX template

DEVELOPING AND ASSESSING

INEXACT MULTIPLIER
ARCHITECTURES FOR IMAGE
PROCESSING
Parthibaraj ANGURAJ1* and Thiruvenkadam KRISHNAN1*
1* Department
of Electronics and Communication Engineering,
K.Ramakrishnan College of Technology, Samayapuram, Trichy,
621112, TamilNadu, INDIA.

*Corresponding author(s). E-mail(s): [email protected];

[email protected];

Abstract
In the realm of approximate computing, the inexact multiplier archi-
tecture stands out as a cornerstone, playing a pivotal role across
error-tolerated applications. This article delves into the intricacies of
three distinct inexact multiplier architectures tailored specifically for
image processing tasks. The study revolves around efficiently par-
titioning the partial product stage into smaller modules and then
employing decoder algorithms/truncation techniques, to obtain the
suggested multiplier’s final result. The resulting 8×8 imprecise mul-
tipliers are engineered with reduced design overhead and reasonable
error metrics. Through simulation with the Cadence RTL compiler
using TSMC 90 nm technology, the realization showcases substantial
area and power savings compared to conventional imprecise multipli-
ers. Comparing one of the proposed approximate models to precise
multipliers reveals significant reductions in both the area and the
power requirement, amounting to 37.19% and 46.14%, respectively, all
while ensuring acceptable error metrics. Furthermore, in comparison to
alternative approximation multiplier designs, the suggested 8×8 mul-
tiplier showcases superior performance metrics. It achieves justifiable
mean Structural Similarity Index (SSI) values, making it particularly
advantageous for tasks such as picture multiplication and sharpening.

1
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2 Research paper

Keywords: Approximate computing, inexact multiplier, Partial product

reduction circuitry, Design parameter, picture multiplication and picture
sharpening.

1 Introduction
Approximate computing has indeed captured significant attention due to
its potential advantages in error-tolerant applications [1], especially within
arithmetic circuits [2]. By embracing approximate computing methodolo-
gies, systems can potentially achieve faster operation, improved efficiency,
and reduced power consumption. These benefits are particularly appealing in
domains such as human vision or hearing, where a certain level of imprecision
can be tolerated without significantly impacting the user experience. In the
context of arithmetic circuits, approximate computing techniques offer various
strategies for optimizing performance and resource utilization. These strate-
gies may involve trading off computational accuracy for gains in efficiency.
For instance, reducing the precision of arithmetic operations or employing
approximation algorithms can lead to computational savings with somewhat
compromising overall system functionality. In applications like human vision,
where perception is inherently tolerant to certain degrees of error or impreci-
sion, approximate computing can be leveraged to exploit these characteristics.
Systems can achieve the desired functionality with reduced computational
overhead by judiciously introducing controlled errors or simplifications in com-
putational processes. In arithmetic circuits, approximate computing techniques
may involve trading off between circuit parameters and the overall performance
of the system. This can be achieved through various means, such as reducing
the precision of computations, employing approximation algorithms, or even
introducing controlled errors in computations [3]. In the study by [4], three
innovative designs of approximately 4-2 compressors are presented, seamlessly
integrated into the partial product reduction circuit of a multiplier. Each sys-
tem demonstrates remarkable precision while upholding a rigorous standard for
allowable error metrics. The multiplier’s architecture intelligently amalgamates
truncation and approximation methods to realize additional enhancements in
power efficiency, area minimization, and reduction in delay. Comparative eval-
uation against precise methodologies and alternative approximation strategies
highlights substantial benefits in power consumption, latency reduction, and
improved area utilization specifically tailored for image-sharpening applica-
tions. In letter [5], a novel design is introduced, which integrates an error
correction unit, based on a previous inexact 4-2 compressor concept. Unlike
other suggested 4-2 compressor-based imprecise multiplier systems, this design
showcases superior accuracy, demands fewer hardware resources, and boasts
reduced power consumption, even with the incorporation of the fault-tolerant
mechanism. In this paper [6], produce and propagate signals are harnessed to
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Research paper 3

manipulate the partial products of the multiplier, paving the way for effec-
tive approximation multipliers. Basic OR gates are deployed to implement
approximation for the modified produce partial products. Additionally, to cur-
tail the residual partial products, the paper proposes approximate versions of
the adder blocks. By contrasting with accurate designs, the paper puts forth
two variations of approximate multipliers, which yield substantial reductions
in both area and power consumption. In references [7] and [8], specialized
low-power and energy-efficient approximate arithmetic multipliers have been
meticulously designed to cater to the demands of image sharpening and JPEG
compression applications. The hybrid and high-speed imprecise multiplier has
been purposefully engineered for image multiplication and conventional neural
network-based applications, as detailed in references [9] and [10]. The authors
of [11] have devised an imprecise multiplier that approximates the partial
product reduction and creation steps to reduce computing expenses. Extensive
hardware evaluations demonstrate that the proposed solutions exhibit superior
performance in terms of design parameters compared to existing approaches.
Validation using image sharpening and image multiplication applications indi-
cates that the suggested designs offer a better balance between performance
and image quality. Additionally, it’s worth noting that several imprecise multi-
plier structures have been developed for image filtering [12], edge detection [13],
and neural network applications [14]. These structures offer versatile solutions
to enhance performance across various domains.
Initially, utilizing conventional AND gate logic, the 8×8 exact multiplier (A
and B) produces sixty-four partial product values. Here, A represents the mul-
tiplier, while B represents the multiplicand. These partial products undergo
processing via a combination of the high number of Half-adder (HA) and
Full-adder (FA) blocks to derive the product value, thereby escalating design
complexity. To confront this challenge, a novel approach introduces a 2-bit-
decoder logic-based 8×8 imprecise multiplier, as detailed in [16]. Within this
structure, the 2-bit decoder logic facilitates the grouping of the multiplier
(A) bits on the LSB side (A6-A0), while exact AND logic operates on the
MSB (A8-A7) bits for partial product generation. As a result, this method
effectively reduces the row count for partial products compared to the pre-
cise model. Nonetheless, despite outperforming previous imprecise models, the
2-bit decoder logic-based imprecise multiplier still contends with high design
complexity. To address this further, [15] proposes a 3-bit decoder logic-based
imprecise multiplier. Here, the 8-bit multiplier bits (A) are grouped via 3-
bit decoder logic on the LSB side (A6 -A0 ), with exact AND logic utilized on
the MSB side (A8 -A7 ) for partial product generation. This particular impre-
cise multiplier structure exhibits superior performance in minimizing area
overhead compared to prior inexact multiplier designs presented in the liter-
ature with admissible error metrics. However, despite these advancements, a
notable research gap remains concerning circuit parameters and the quality of
outcomes.
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1.1 The purpose and arrangement of the work

Within this section, the motivation behind exploring imprecise multipli-
ers is provided, and the organization of this work is outlined. The increasing
demand for efficient computing solutions across various domains, including
image processing, neural networks, and digital signal processing, serves as the
primary motivation for exploring approximate multipliers. Traditional multi-
pliers often come with significant computational costs, consuming substantial
power and area resources. However, in numerous applications, there exists
flexibility to balance precision for improvements in performance, power effi-
ciency, and resource utilization, especially in scenarios where a certain level
of error tolerance is deemed acceptable. The adoption of approximate mul-
tipliers, which introduce controlled errors during the multiplication process,
offers a promising solution to address these challenges. By reducing precision
requirements, approximate multipliers can significantly decrease power con-
sumption and area overhead, while still delivering satisfactory performance
across a diverse set of error-tolerated applications. Additionally, there is a
growing demand for area- and power-efficient multiplier models to meet the
requirements of emerging research applications. This study aims to build
three different 8 × 8 inexact multiplier structures using decoding and trun-
cation schemes for applications that can accommodate errors. In pursuing
this approach, the proposed models seek to surpass current imprecise mod-
els in terms of circuit parameters, while still upholding justifiable accuracy
standards.
The subsequent sections delve into the presented designs, offering compre-
hensive insights. The organization of this work is outlined as follows: Section
2 introduces the proposed imprecision multipliers. Section 3 delves into the
hardware utilization and analysis of error metrics for different inexact mul-
tiplier configurations, alongside the exact multiplier design. Furthermore,
section 4 provides an elucidation of the error-tolerated application employing
erroneous multiplier models. Finally, section 5 encapsulates the conclusions
drawn from this study, synthesizing the findings into actionable insights.

2 Proposed inexact multiplier structures

Researchers worldwide are motivated to develop a more compact version
of the inexact multiplier with acceptable error metrics. Therefore, this section
introduces three variations of 8×8 inexact multiplier architectures. The novelty
of the work is to effectively divide the single 8×8 multiplier into four 4×4
sub-modules, utilizing decoding and truncation schemes thereafter.
As previously mentioned, the proposed methodology involves decompos-
ing the single 8x8 multiplier structure into four 4x4 multipliers. As depicted
in Figure 1, A and B denote the eight-bit multiplier and multiplicand val-
ues, respectively. The labels p0-p31 signify the values generated during partial
product calculation. Initially, the bits of both multiplier and multiplicand are
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Fig. 1 The general structure of the proposed 8×8 inexact multiplier.

evenly partitioned into Most Significant Bit (MSB) and Least Significant Bit
(LSB) components. Specifically, (A3 -A0 ) and (A7 -A4 ) denote the LSB and
MSB bits of the multiplier, while (B3 -A0 ) and (B7 -A4 ) signify the LSB and
MSB bits of the multiplicand. The partial product values, ranging from p0 to
p7 , result from the multiplication of (B3 -B0 × A3 -A0 ); p15 -p8 arise from (B7 -
B4 × A3 -A0 ); p23 -p16 stem from (B3 -B0 × A7 -A4 ), and p31 -p24 emerge from
(B7 -B4 × A7 -A4 ). Following the production of partial product terms, the par-
tial product reduction circuitry utilizes adder components to derive the final
outcome. The range P15 –P0 signifies the final product value obtained from 8x8
multiplications.

Fig. 2 The proposed 8x8 inexact multiplier Design-1.

The suggested 8x8 inexact multiplier model-1 is depicted in Figure 2.

Within this structure, only three out of the four 4×4 sub-modules are uti-
lized for generating the partial product values. Specifically, the sub-module
(B3 -B0 × A3 -A0 ) is omitted, while the P3 -P0 value is designated as ”1111”.
Notably, the circular representation indicates the multiplication outcome of
(B7 -B4 × A3 -A0 ) and (B7 -B4 × A7 -A4 ), achieved through exact AND logic.
Consequently, these 4×4 sub-modules produce exact partial product values.
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Conversely, the square denotes the partial product generation of the (B3 -B0 ×
A7 -A4 ) sub-module, employing both 3-bit decoder logic and AND logic. This
approach entails grouping the least significant bits of the multiplier (A6 -A4 )
via 3-bit decoder logic, while the most significant bit (A7 ) is utilized in AND
logic to produce imprecise partial product results.

Fig. 3 The proposed 8x8 inexact multiplier Design-2.

The proposed 8x8 inexact multiplier Design-2 is illustrated in Figure 3.

In this configuration, all four 4×4 sub-modules are engaged in generating the
partial product values. Particularly noteworthy, the dot representation signifies
the multiplication outcome of (B7 -B4 × A3 -A0 ), achieved through imprecise
2-bit decoder logic. As a result, this 4×4 sub-module yields inexact partial
product values. Similarly, the square symbolizes the partial product generation
of the (B3 -B0 × A7 -A4 ) sub-module, which utilizes both 3-bit decoder logic
and AND logic. This method involves grouping the least significant bits of
the multiplier (A6 -A4 ) using 3-bit decoder logic while employing AND logic
with the most significant bit (A7 ) to produce imprecise partial product results.
In contrast, the circular representation denotes the multiplication outcome of
(B7 -B4 × A7 -A4 ), achieved through exact AND logic.
The proposed 8x8 inexact multiplier model-3 is illustrated in Figure 4. It
utilizes four 4×4 sub-modules for generating partial product values. Notably,
the square representations indicate the multiplication outcomes of (B3 -B0 ×
A3 -A0 ) and (B3 -B0 × A7 -A4 ), utilizing a 3-bit imprecise decoder and AND
scheme. Consequently, these 4×4 sub-modules produce inexact partial prod-
uct values. Similarly, the circle symbolizes the partial product generation of
the (B7 -B4 × A3 -A0 ) and (B7 -B4 × A7 -A4 ) sub-modules, achieved through
exact AND logic. To facilitate understanding, the numerical calculation of the
presented 8x8 inexact multiplier Design-3 is elucidated in Figure 5.
In Figure 5, both A and B values are 255 (11111111)2 . Initially, the 8×8
multiplication is partitioned into four 4×4 sub-modules to derive the par-
tial product values. A3 -A0 (1111)2 is multiplied by B3 -B0 (1111)2 , resulting
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Research paper 7

Fig. 4 The proposed 8x8 inexact multiplier Design-3.

Fig. 5 The numerical example of the proposed 8x8 inexact multiplier Design-3.

in partial product values p7 -p0 (10110111)2 ; A3 -A0 (1111)2 is multiplied by

B7 -B4 (1111)2 , yielding partial product values p15 -p8 (11100001)2 ; A7 -A4
(1111)2 is multiplied by B3 -B0 (1111)2 , producing partial product values p23 -
p16 (10110111)2 ; A7 -A4 (1111)2 is multiplied by B7 -B4 (1111)2 , generating
partial product values p31 -p24 (11100001)2 . The 3-bit decoder scheme’s oper-
ation is detailed in [15]. To provide clearer insights, we present a numerical
demonstration of a 4×4 module employing the 3-bit decoder in conjunction
with AND logic, depicted in Fig. 6. Furthermore, Fig. 7 illustrates a detailed
numerical example of the 2-bit decoder scheme utilized in the proposed 8x8
inexact multiplier Design-2.
In Fig. 6, employing the 3-bit decoder scheme delineated in [16], when A2 -
A0 is set to 111, the partial product is constructed via the operation (B [3:0]
+ B [3:0], 1’b0 + B [3:0], 1’b0, 1’b0). Thus, in this scenario, (1111 + 11110 +
111100), yielding the result (111111)2 . The symbol ‘+’ denotes the OR opera-
tion. Following this, the second-row outcome, “1111”, is derived by multiplying
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Fig. 6 The numerical example of one of the proposed 4x4 inexact multipliers.

the variables A3 and B3 using AND logic. Subsequent to generating these

values, adder components are employed to obtain the final result, (10110111)2 .

Fig. 7 The numerical example of one of the proposed 4x4 inexact multipliers using 2-bit
decoder logic .

The numerical illustration of a proposed 4x4 inexact multiplier employing

2-bit decoder logic is depicted in Figure 7. In the proposed Design-2 for an
8x8 inexact multiplier, one of the 4x4 sub-modules (designated as B7 -B4 ×
A3 -A0 ) utilizes a 2-bit decoder scheme as described in [16]. To illustrate, let’s
assume both A and B are four-bit values, each set to “1111”. When A1 -A0
is set to 11, the partial product is formed by operating (B [7:4] + B [7:4],
1’b0). Thus, in this instance, (1111 + 11110), yielding the result (11111)2 .
Following this, the second-row outcome, (11111)2 , is obtained by multiplying
the variables A3 -A2 with B7 -B4 using the same logic. After obtaining these
values, adder components are utilized to derive the final result, (10011011)2 .
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Fig. 8 The block diagram of image multiplication.

In these proposed 8x8 inexact multipliers, the generation of partial product

values undergoes a significant reduction compared to both exact and imprecise
multipliers discussed in the existing literature. This reduction in partial prod-
uct values fosters streamlined processes within the multiplier designs, thereby
enhancing overall efficiency. For example, in design 1, partial product val-
ues are generated across three rows, totalling twenty-four values. Conversely,
both design 2 and design 3 produce thirty-two partial product values dis-
tributed among four rows. Consequently, the reduction circuitry necessitates
fewer adders to compute the final product, resulting in a more streamlined
architecture. The proposed 8x8 inexact multipliers are notable for their abil-
ity to reduce design complexity, particularly when contrasted with imprecise
models outlined in current literature. Notably, in the proposed models, the
approximation concept primarily targets the LSB side, enabling them to per-
form adequately with acceptable accuracy degradation. This is further possible
by the precise AND logic applied on the MSB side of computation. Such
deliberate design choices contribute to the promising potential of these multi-
pliers for integration into error-resilient applications such as picture sharpening
and picture multiplication. This quality assurance further bolsters the viabil-
ity of these multipliers for various image-processing tasks. Subsequently, the
following section delves into the hardware realization and explores the image-
processing applications of these imprecise multipliers, providing a deeper
understanding of their capabilities and advantages.

3 Hardware realization
The suggested and existing circuits were developed and implemented using
TSMC 90 nm technology with the aid of the Cadence RTL compiler v7.1 (slow-
normal library). Verilog programming language served as the foundation for
both the existing and proposed approximate multipliers. Table 1 provides an
intricate comparison of 8 × 8 imprecise multipliers based on circuit param-
eters. Additionally, Table 1 presents a comprehensive analysis of accuracy
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Fig. 9 Image multiplication results using different inexact multipliers.

Table 1 Execution results of various 8-bit approximate multipliers

Ref Area
Delay Power ADP MED NMED MRED ER

µm2 (ps) (nW) (10−12 ) (10−3 ) (%)

exact 1261 46038 2.9 3.656 - - - -

[6] 1135 34981 2.7 3.064 101.439 1.56 1.36 77.4
[4] 951 31093 2.6 2.472 35.09 0.48 0.76 83.74
[5] 925 30171 2.5 2.312 28.05 0.43 0.78 82.91
[8] 1017 29654 2.9 2.949 86.483 1.33 1.404 66.45
[10]D1 1153 32104 3.1 3.574 16.256 0.25 0.765 75.00
[10]D2 1036 29436 3.1 3.211 278.30 4.28 5.6 89.36
[10]D3 927 28004 3.1 2.873 339.43 5.22 7.566 96.17
[7]D1 863 28588 2.4 2.071 136.55 2.1 1.7 66.36
[7]D2 776 25458 2.2 1.707 208.08 3.2 2.2 66.43
[9]D1 1117 38146 2.6 2.904 29.91 0.46 0.1 30.47
[9]D2 986 33830 2.6 2.563 106.64 1.64 1.26 48.35
[9]D3 862 27954 2.3 1.982 397.95 6.12 2.83 69.73
[11]D1 742 24568 2.2 1.632 169.06 2.6 2.4 76.86
[11]D2 702 23681 2.1 1.474 188.57 2.9 2.9 75.56
[12]D1 965 21868 1.1 1.061 1742.6 26.8 14.9 97.85
[12]D2 1115 26115 1.6 1.784 663.255 10.2 7.56 97.85
[13] 783 19172 2.2 1.722 110.542 1.7 3.52 99.79
[14] 917 28183 2.3 2.109 26.3828 0.4 0.43 44.26
Design1 625 16395 2.1639 1.352 97.267 1.5 2.10 98.87
Design2 748 22901 2.2470 1.680 124.1875 1.9 1.33 50.92
Design3 792 24792 2.2711 1.798 54.1875 0.8 0.70 40.33
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Table 2 The comprehensive analysis of 8 × 8 multipliers in image processing

Ref Image Sharpening Image Multiplication

Lena moon Cameraman×moon Resolution
chart×Clock
[6] 0.9133 0.9186 0.9643 0.9236
[4] 0.8406 0.8558 0.9189 0.9168
[5] 0.8701 0.8825 0.9301 0.9143
[8] 0.9301 0.9414 0.9785 0.9275
[10]D1 0.9984 0.9987 0.9981 0.9864
[10]D2 0.9475 0.9582 0.9953 0.9802
[10]D3 0.8941 0.9064 0.9486 0.9135
[7]D1 0.9702 0.9692 0.9857 0.9247
[7]D2 0.9673 0.9715 0.9893 0.9351
[9]D1 0.9992 0.9990 0.9993 0.9973
[9]D2 0.9836 0.9887 0.9893 0.9378
[9]D3 0.9568 0.9641 0.9706 0.9275
[11]D1 0.9681 0.9708 0.9794 0.9301
[11]D2 0.9620 0.9697 0.9764 0.9294
[12]D1 0.8504 0.8723 0.9150 0.9126
[12]D2 0.8763 0.8814 0.9207 0.9284
[13] 0.9698 0.9725 0.9801 0.9239
[14] 0.9989 0.9988 0.9990 0.9986
Design1 0.9960 0.9971 0.9985 0.9957
Design2 0.9982 0.9984 0.9987 0.9969
Design3 0.9986 0.9987 0.9988 0.9971

metrics, including Mean Error Distance (MED), Normalized MED (NMED),

Mean Relative Error Distance (MRED), Error Rate (ER), and Number of
Accuracy Conditions (NAC), computed using MATLAB software as detailed
in [17]. This thorough examination encompassed 65,536 conditions (256 ×
256). Analysing Table 1 for 8-bit multipliers, based on delay, it’s evident that
the proposed multiplier outpaces all existing designs except for [12]. However,
the research referenced as [12] encounters accuracy issues, achieving results
with notably high error metrics. The proposed multiplier design 1 shows a sig-
nificant 21.68% increase in speed compared to the exact multiplier. As well,
both design 2 and design 3 of the 8 × 8 multiplier demonstrate substantial
speed enhancements of 22.51% and 21.68%, respectively, while comparing with
the precise multiplier. The proposed multiplier model 1 exhibits a remarkable
50.43% reduction in area overhead compared to the exact multiplier. Addition-
ally, both design 2 and design 3 of the 8 × 8 multiplier demonstrate notable
reductions in area, with percentages of 40.68% and 37.19%, respectively, in
comparison to the precise multiplier. Moreover, the proposed multiplier design
1 demonstrates a significant 64.38% minimisation in power requirement com-
pared to the precise multiplier. Similarly, both model 2 and model 3 of the 8
× 8 multiplier illustrate substantial power reductions of 50.25% and 46.14%,
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12 Research paper

respectively, while comparing with the precise multiplier. Compared to other

inexact circuits discussed in the literature, the proposed 8 × 8 inexact design 1
demonstrated superior performance in both area and power parameters. Sim-
ilarly, design 2 and design 3 performed well in terms of area, except for [11]
and [7] [11]. Regarding power, when compared to imprecise models in the cur-
rent research landscape, design 2 and design 3 outperformed most, except for
[12] D2 , [13], and [11], [12] D2 , [13], respectively. However, it’s worth noting
that the research papers [12] D2 , [11], and [13] suffer from accuracy issues.
Moreover, the proposed model 1 exhibits an impressive 63.01% improvement
in ADP (Area-Delay Product) when contrasted with the exact multiplier. This
surpasses most existing designs, except D1 [12], which fall short in accuracy.
Based on the findings presented in Table 1, it becomes clear that the proposed
multiplier designs strike a superior equilibrium between complexity overhead
and acceptable error metrics. This suggests that not only do these designs excel
in performance metrics such as speed, area, and power, but they also manage
to keep error metrics within acceptable bounds. This underscores their poten-
tial practical applicability in real-world scenarios where both performance and
accuracy are crucial considerations.

4 The application that tolerates errors: image

processing
This session delves deeply into assessing the efficacy of the proposed 8
× 8 inexact multipliers across various error-tolerated schemes, encompassing
image sharpening and multiplication. Specifically, for the image sharpening
application, two standard images—Lena and Moon—both sized at 256 × 256
and in black and white, were meticulously chosen as benchmarks. The sharp-
ening methodology, elaborated upon in [1], was meticulously implemented on
these selected images. Moreover, it’s essential to note that the calculations
were performed using MATLAB software R2017b (64-bit), ensuring accuracy
and reliability in the analysis. Table 2 enriches this study by presenting a
comprehensive mean SSI metric analysis of diverse approximate multipliers.
This analysis illuminates the degree of similarity between output and refer-
ence images, assessed on a scale from 0 to 1. Such evaluation stands as a
pivotal benchmark for assessing image quality across a spectrum of processing
schemes. Expanding our exploration into image multiplication, two distinct
combinations—Cameraman × Moon and Resolution Chart × Clock—were
meticulously chosen to showcase the versatility of the proposed approaches.
Image multiplication is carried out using MATLAB System Simulink software,
version R2017b (64-bit).
Figure 8 illustrates the block diagram of image multiplication, while Figure
9 presents the corresponding outcomes. This illustration offers valuable insights
into the structural intricacies underlying the proposed methodology. The sug-
gested 8 × 8 approximate multiplier design 3, as demonstrated, exhibited
superior performance based on the mean SSI metric when juxtaposed against
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Research paper 13

existing designs, excluding [9] D1 and [14]. In terms of circuit parameters, when
compared to [9] D1 , the suggested multiplier D3 showcased reductions in area,
delay, power, and ADP by 29.09%, 35.00%, 12.65%, and 38.08%, respectively.
Similarly, in comparison to [14] based on circuit parameters, the suggested
multiplier D3 displayed reductions in area, delay, power, and ADP by 13.63%,
12.03%, 1.25%, and 14.74%, respectively. Upon analysis of Table 2, it was
deduced that the suggested approximate multipliers prowess lies in its capacity
to achieve an approving equilibrium between ADP and image quality.

5 Conclusion
Within this paper, we have devised three distinct types of proposed
8×8 approximate multiplier structures, employing decoding and truncation
schemes. The primary aim of this endeavour is to refine the design param-
eters by effectively minimizing the partial product rows. Furthermore, upon
juxtaposing with precise and existing inexact multipliers, the presented 8 × 8
model mitigates design variables while upholding justifiable accuracy metrics.
Likewise, comparing one of the provided 8 × 8 approximate multipliers with
accurate multipliers reveals substantial reductions in area, delay, power, and
ADP by 37.19%, 21.68%, 46.14%, and 50.82%, respectively. Considering the
adeptness of the proposed models in attaining an optimal equilibrium between
design parameters and image quality, they stand out as promising candidates
for many image-processing applications.

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