HY57V641620HG

4 Banks x 1M x 16Bit Synchronous DRAM

D E S C R IP T IO N

The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.

HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES
• Single 3.3± 0 . 3 V power supply
Note) • Auto refresh and self refresh

• All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms

• JEDEC standard 400mil 54pin TSOP-II with 0.8mm • Programmable Burst Length and Burst Type

of pin pitch
- 1, 2, 4, 8 or Full page for Sequential Burst

• All inputs and outputs referenced to positive edge of

system clock - 1, 2, 4 or 8 for Interleave Burst

• Data mask function by UDQM or LDQM • Programmable CAS Latency ; 2, 3 Clocks

• Internal four banks operation

O R D E R IN G IN F O R M A T IO N

Part No. C lock Frequency Power Organization Interface Package

HY57V641620HGT-5/55/6/7 200/183/166/143MHz

HY57V641620HGT-K 133MHz

HY57V641620HGT-H 133MHz
Normal
HY57V641620HGT-8 125MHz

HY57V641620HGT-P 100MHz

HY57V641620HGT-S 100MHz 4Banks x 1Mbits

LVTTL 400mil 54pin TSOP II
HY57V641620HGLT-5/55/6/7 200/183/166/143MHz x16

HY57V641620HGLT-K 133MHz

HY57V641620HGLT-H 133MHz
Low power
HY57V641620HGLT-8 125MHz

HY57V641620HGLT-P 100MHz

HY57V641620HGLT-S 100MHz

N o t e : V D D ( M in ) o f H Y 5 7 V 6 4 1 6 2 0 H G ( L ) T - 5 /5 5 / 6 i s 3 . 1 3 5 V

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.5/Jun.01
 HY57V641620HG

P IN C O N F IG U R A T IO N

VDD 1 54 V SS
DQ0 2 53 DQ15
VDDQ 3 52 V SSQ
DQ1 4 51 DQ14
DQ2 5 50 DQ13
VSSQ 6 49 V DDQ
DQ3 7 48 DQ12
DQ4 8 47 DQ11
VDDQ 9 46 V SSQ
DQ5 10 45 DQ10
DQ6 11 44 DQ9
VSSQ 12 43 V DDQ
DQ7 13 54pin TSOP II 42 DQ8
VDD 14 400mil x 875mil 41 V SS
LDQM 15 0.8mm pin pitch 40 NC
/WE 16 39 UDQM
/CAS 17 38 CLK
/RAS 18 37 CKE
/CS 19 36 NC
BA0 20 35 A11
BA1 21 34 A9
A10/AP 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
VDD 27 28 V SS

P IN D E S C R IP T IO N

PIN P I N N A M E D E S C R IPTION

The system clock input. All other inputs are registered to the SDRAM on the
CLK Clock
rising edge of CLK

Controls internal clock signal and when deactivated, the SDRAM will be one
CKE Clock Enable
of the states among power down, suspend or self refresh

CS Chip Select Enables or disables all inputs except CLK, CKE and DQM

S e l e c t s b a n k t o b e a c t i v a t e d d u r i n g R A S activity
BA0,BA1 Bank Address
S e l e c t s b a n k t o b e r e a d / w r i t t e n d u r i n g C A S activity

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7

A0 ~ A11 Address
Auto-precharge flag : A10

Row Address Strobe,

R A S , C A S and W E define the operation
R A S , C A S, W E Column Address Strobe,
Refer function truth table for details
Write Enable

LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin

V D D /V S S Power Supply/Ground Power supply for internal circuits and input buffers

V D D Q /V S S Q Data Output Power/Ground Power supply for output buffers

NC No Connection No connection

Rev. 0.5/Jun.01 2
 HY57V641620HG

F U N C T IO N A L B L O C K D IA G R A M

1Mbit x 4banks x 16 I/O Synchronous DRAM

Self refresh logic Internal Row

& timer counter

CLK 1Mx16 Bank 3

Row active Row 1Mx16 Bank 2

Pre
X decoders
C K E
Decoders 1Mx16 Bank 1
X decoders

C S 1Mx16 Bank 0
State Machine

X decoders

R A S D Q 0

Sense AMP & I/O Gate

X decoders

D Q 1

I/O Buffer & Logic

Memory
C A S refresh Cell
Array
W E Column
Column
Active
Pre
U D Q M Decoders DQ14

DQ15
L D Q M Y decoders

Column Add
Bank Select
Counter

A 0 Address
A 1 Registers
Address buffers

Burst
Counter

A11
B A 0
CAS Latency
B A 1 Mode Registers Data Out Control
Pipe Line Control

Rev. 0.5/Jun.01 3
 HY57V641620HG

A B S O L U T E M A X IM U M R A T IN G S

P a r a m e ter Symbol Rating Unit

Ambient Temperature TA 0 ~ 70 °C

Storage Temperature TS T G -55 ~ 125 °C

Voltage on Any Pin relative to V S S V IN, V O U T -1.0 ~ 4.6 V

Voltage on V D D relative to V S S VDD, VD D Q -1.0 ~ 4.6 V

Short Circuit Output Current IO S 50 mA

Power Dissipation PD 1 W

Soldering Temperature ⋅ T i m e TSOLDER 260 ⋅ 10 °C ⋅ S e c

N o te : O p e r a t i o n a t a b o v e a b s o l u t e m a x i m u m r a t i n g c a n a d v e r s e l y a f f e c t d e v i c e r e l i a b i l i t y

D C O P E R A T IN G C O N D IT IO N ( T A = 0 t o 7 0 °C )

P a r a m e ter Symbol M in Typ. Max U n it N o te

Power Supply Voltage VD D , VDDQ 3.0 3.3 3.6 V 1,2

Input High Voltage V IH 2.0 3.0 V DDQ + 2.0 V 1,3

Input Low Voltage V IL V S S Q - 2.0 0 0.8 V 1,4

N o te :
1.All voltages are referenced to VSS = 0 V
2.VDD(min) of HY57V641620HG(L)T-5/55/6 is 3.135V
3.V IH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration
4.V IL (min) is acceptable -2.0V AC pulse width with ≤ 3ns of duration

A C O P E R A T IN G C O N D IT IO N ( T A = 0 t o 7 0 ° C , V D D = 3 . 3 ± 0 . 3 VN o t e 2 , V S S = 0 V )

P a r a m e ter S y m b o l Value U n it Note

AC Input High / Low Level Voltage V I H / V IL 2.4/0.4 V

Input Timing Measurement Reference Level Voltage Vtrip 1.4 V

Input Rise / Fall Time tR / tF 1 ns

Output Timing Measurement Reference Level Voutref 1.4 V

Output Load Capacitance for Access Time Measurement CL 50 pF 1

N o te :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
2.VDD(min) of HY57V641620HG(L)T-5/55/6 is 3.135V

Rev. 0.5/Jun.01 4
 HY57V641620HG

C A P A C IT A N C E ( T A = 2 5° C , f = 1 M H z )

Parameter P in S y m b o l M in Max Unit

Input capacitance CLK C I1 2 4 pF

A0 ~ A11, BA0, BA1, CKE, C S, RAS, CI 2 2.5 5 pF

CAS, W E, UDQM, LDQM

Data input / output capacitance DQ0 ~ DQ15 C I/O 2 6.5 pF

O U T P U T L O A D C IR C U IT

Vtt=1.4V

RT=250 Ω

Output Output

50pF
50 pF

DC Output Load Circuit AC Output Load Circuit

D C C H A R A C T E R IS T IC S I ( T A = 0 t o 7 0 ° C , V DD =3.3 ± 0 . 3 V Note3)

P a r a m e ter Symbol M in. Max Unit Note

Input Leakage Current IL I -1 1 uA 1

Output Leakage Current IL O -1 1 uA 2

Output High Voltage VOH 2.4 - V IO H = - 4 m A

Output Low Voltage VOL - 0.4 V IO L = + 4 m A

N o te :
1 . V I N = 0 t o 3 . 6 V , A l l o t h e r p i n s a r e n o t t e s t e d u n d e r V IN = 0 V
2.DO U T is disabled, V O U T =0 to 3.6

Rev. 0.5/Jun.01 5
 HY57V641620HG

t o 7 0 °C , V D D = 3 . 3 ± 0 . 3 V
Note5
D C C H A R A C T E R IS T IC S II ( T A = 0 , VSS =0V)

Speed
Parameter S y m b o l Test Condition Unit N o te
-5 -55 -6 -7 -K -H -8 -P -S

Burst length=1, One bank active

Operating Current ID D 1 100 95 90 85 85 85 80 80 80 mA 1
tRC ≥ tRC ( m i n ) , I O L = 0 m A

Precharge Standby ID D 2 P C K E ≤ V IL(max), tC K = min 2 mA

Current
in Power Down Mode ID D 2 P S C K E ≤ V IL(max), tC K = ∞ 2 mA

C K E ≥ V IH ( m i n ) , C S ≥ V I H ( m i n ) , t C K
= min
ID D 2 N Input signals are changed one time 15 mA
Precharge Standby
during 2clks. All other pins ≥ V DD -
Current
0.2V or ≤ 0.2V
in Non Power Down Mode

C K E ≥ V IH ( m i n ) , t C K = ∞
ID D 2 N S 12 mA
Input signals are stable.

ID D 3 P C K E ≤ V IL(max), tC K = min 6 mA
Active Standby Current
in Power Down Mode
ID D 3 P S C K E ≤ V IL(max), tC K = ∞ 5 mA

C K E ≥ V IH ( m i n ) , C S ≥ V I H ( m i n ) , t C K
= min
ID D 3 N Input signals are changed one time 30 mA
Active Standby Current during 2clks. All other pins ≥ V DD -
in Non Power Down Mode 0.2V or ≤ 0.2V

C K E ≥ V IH ( m i n ) , t C K = ∞
ID D 3 N S 20 mA
Input signals are stable.

CL=3 170 160 150 150 150 150 120 120 120 mA 1
Burst Mode Operating tC K ≥ tC K ( m i n ) , I O L = 0 m A
ID D 4
Current All banks active
CL=2 NA NA NA NA 120 mA

Auto Refresh Current ID D 5 t R R C ≥ tR R C ( m i n ) , A l l b a n k s a c t i v e 160 mA 2

1 mA 3
Self Refresh Current ID D 6 C K E ≤ 0.2V
400 uA 4

N o te :
1.ID D 1 a n d I D D 4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh R A S cycle time) is shown at AC CHARACTERISTICS II
3.HY57V641620HGT-6/7/K/H/P/S
4.HY57V641620HGLT-6/7/K/H/P/S

Rev. 0.5/Jun.01 6
 HY57V641620HG
A C C H A R A C T E R IS T IC S I ( A C operating conditions unless otherwise noted)

-5 -55 -6 -7 -K -H -8 -P -S
Parameter Symbol Unit Note
M in Max Min M a x M in Max Min Max M in M a x M in Max M in Max M in Max Min Max

C A S Latency =
tCK3 55 55 6 7 7.5 7.5 8 10 10 ns
3
System clock 100
1000 1000 1000 1000 1000 1000 1000 1000
cycle time 0
C A S Latency =
tCK2 10 10 10 10 7.5 10 10 10 12 ns
2

Clock high pulse width tCHW 2.5 - 2.75 - 2.5 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1

Clock low pulse width tCLW 2.5 - 2.75 - 2.5 - 2.5 - 2.5 - 2.5 - 3 - 3 - 3 - ns 1

C A S Latency =
tAC3 - 5.4 - 5.4 - 5.4 - 5.4 - 5.4 5.4 - 6 6 - 6 ns
3
Access time
2
from clock
C A S Latency =
tAC2 - 6 - 6 - 6 - 6 - 5.4 6 - 6 - 6 - 8 ns
2

Data-out hold time tOH 2.5 - 2.5 - 2.7 - 2.7 - 2.7 - 2.7 - 3 - 3 - 3 - ns

Data-Input setup time tDS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1

Data-Input hold time tDH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1

Address setup time tAS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1

Address hold time tAH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1

CKE setup time tCKS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1

CKE hold time tCKH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1

Command setup time tCS 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 2 - 2 - 2 - ns 1

Command hold time tCH 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 0.8 - 1 - 1 - 1 - ns 1

CLK to data output in low Z-time tOLZ 1 - 1 - 1 - 1.5 - 1.5 - 1.5 - 1 - 1 - 2 - ns

C A S Latency =
tOHZ3 3 6 ns
CLK to data 3
output in high 5.4 5.4 5.4 5.4 5.4 5.4 6 6
Z-time C A S Latency =
tOHZ2 3 6 ns
2

Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate

Rev. 0.5/Jun.01 7
 HY57V641620HG

A C C H A R A C T E R IS T IC S I

-5 -55 -6 -7 -K -H -8 -P -S
S y m b o
Parameter Unit Note
l
M in Max M in Max M in Max M in Max M in Max M in Max M in Max Min Max M in Max

Operation tRC 55 - 55 - 60 - 62 - 65 - 65 - 68 - 70 - 70 - ns
R A S Cycle
Time
Auto Refresh tR R C 60 - 60 - 60 - 62 - 65 - 65 - 68 - 70 - 70 - ns

R A S to C A S Delay tR C D 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns

100 100
R A S Active Time tR A S 38.5 100K 38.5 100K 42 42 120K 45 120K 45 120K 48 50 120K 50 120K ns
K K

RAS Precharge Time tR P 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns

R A S to R A S Bank Active
tR R D 10 - 11 - 12 - 14 - 15 - 15 - 16 - 20 - 20 - ns
Delay

C A S to C A S Delay tC C D 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK

Write Command to Data-In

tW T L 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK
Delay

Data-In to Precharge
tD P L 2 - 2 - 2 - 1 - 1 - 1 - 2 - 1 - 1 - CLK
Command

Data-In to Active Command tD A L 5 - 5 - 5 - 4 - 4 - 4 - 5 - 3 - 3 - CLK

DQM to Data-Out Hi-Z tD Q Z 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK

DQM to Data-In Mask tD Q M 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK

MRS to New Command tM R D 2 - 2 - 2 - 1 - 1 - 1 - 2 - 1 - 1 - CLK

CAS Latency tP R O Z
3 - 3 - 3 - 3 - 3 - 3 - 3 - 3 - 3 - CLK
Precharge to = 3 3
Data Output
Hi-Z CAS Latency tP R O Z
2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK
= 2 2

Power Down Exit Time tP D E 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK

Self Refresh Exit Time tS R E 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK 1

Refresh Time tR E F - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms

N o te :
1. A new command can be given tRRC after self refresh exit

Rev. 0.5/Jun.01 8
 HY57V641620HG

D E V IC E O P E R A T IN G O P T IO N T A B L E

H Y 5 7 V 6 4 1 6 2 0 H G (L)T-5

C A S Latency tRCD tRAS tRC tRP tAC tO H

200MHz(5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.5ns

183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.5ns

166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns

H Y 5 7 V 6 4 1 6 2 0 H G (L)T-55

C A S Latency tRCD tRAS tRC tRP tAC tO H

183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.5ns

166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns

143MHz(7ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns

H Y 5 7 V 6 4 1 6 2 0 H G (L)T-6

C A S Latency tRCD tRAS tRC tRP tAC tO H

166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.4ns 2.7ns

143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns

133MHz(7.5ns) 2CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns

H Y 5 7 V 6 4 1 6 2 0 H G (L)T-7

C A S Latency tRCD tRAS tRC tRP tAC tO H

143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns

133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

H Y 5 7 V 6 4 1 6 2 0 H G (L)T-K

C A S Latency tRCD tRAS tRC tRP tAC tO H

133MHz(7.5ns) 2CLKs 2CLKs 6CLKs 8CLKs 2CLKs 5.4ns 2.7ns

125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

H Y 5 7 V 6 4 1 6 2 0 H G (L)T-H

C A S Latency tRCD tRAS tRC tRP tAC tO H

133MHz(7.5ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.4ns 2.7ns

125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 3ns

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

Rev. 0.5/Jun.01 9
 HY57V641620HG
4 Banks x 1M x 16Bit Synchronous DRAM

H Y 5 7 V 6 4 1 6 2 0 H G (L)T-8

C A S Latency tRCD tRAS tRC tRP tAC tO H

125MHz(8ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 6ns 3ns

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 3CLKs 6ns 3ns

83MHz(12ns) 3CLKs 3CLKs 6CLKs 9CLKs 2CLKs 6ns 3ns

H Y 5 7 V 6 4 1 6 2 0 H G (L)T-P

C A S Latency tRCD tRAS tRC tRP tAC tO H

100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns

H Y 5 7 V 6 4 1 6 2 0 H G (L)T-S

C A S Latency tRCD tRAS tRC tRP tAC tO H

100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 3ns

66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 3ns

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.5/Jun.01
 HY57V641620HG

COMMAND TRUTH TABLE

A10/
C o m m a n d CKEn-1 C K E n C S R A S C A S W E D Q M A D D R BA Note
AP

Mode Register Set H X L L L L X OP code

H X X X
No Operation H X X X
L H H H

Bank Active H X L L H H X RA V

Read L
H X L H L H X CA V
Read with Autoprecharge H

Write L
H X L H L L X CA V
Write with Autoprecharge H

Precharge All Banks H X

H X L L H L X X
Precharge selected Bank L V

Burst Stop H X L H H L X X

DQM H X V X

Auto Refresh H H L L L H X X

Entry H L L L L H X

Self Refresh1 H X X X X
Exit L H X
L H H H

H X X X
Entry H L X
L H H H
Precharge
X
power down
H X X X
Exit L H X
L H H H

H X X X
Entry H L X
Clock
L V V V X
Suspend

Exit L H X X

N o te :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2 . X = D o n′ t c a r e , H = L o g i c H i g h , L = L o g i c L o w . B A = B a n k A d d r e s s , R A = R o w A d d r e s s , C A = C o l u m n A d d r e s s ,
Opcode = Operand Code, NOP = No Operation

Rev. 0.5/Jun.01 11
 HY57V641620HG

P A C K A G E IN F O R M A T IO N

4 0 0 m i l 5 4 p i n T h i n S m all O u t l i n e P a c k a g e

UNIT : mm(inch)

11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720) 10.262(0.4040)
10.058(0.3960)

0.150(0.0059) 1.194(0.0470)
0.050(0.0020) 0.991(0.0390)

0.400(0.016) 5deg 0.597(0.0235) 0.210(0.0083)

0.80(0.0315)BSC 0deg 0.406(0.0160) 0.120(0.0047)
0.300(0.012)

Rev. 0.5/Jun.01 12