1. Explain the different layers in the PCIe protocol stack.

How does each layer contribute to

Answer:
PCIe consists of the following layers:

• Transaction Layer (TL): Generates and processes Transaction Layer Packets (TLPs) for
reads, writes, and messages.

• Data Link Layer (DLL): Adds sequence numbers and a Link CRC (LCRC) for data
integrity. Also handles acknowledgments (ACK/NAK).

• Physical Layer (PHY): Transmits and receives data over the serial link. Includes
electrical signaling, encoding, and equalization mechanisms.

2. What is the role of DLLP and TLP in PCIe? How are they different?

Answer:

• TLP (Transaction Layer Packet): Used for actual data transfer (memory reads/writes,
I/O transactions, configuration, and messages).

• DLLP (Data Link Layer Packet): Used for link maintenance (ACK/NAK for error
recovery, flow control credits, power management messages).

3. How does PCIe handle flow control, and what are the different types of flow control
mechanisms?

Answer:
PCIe uses credit-based flow control, where a receiver advertises available buffer credits
before a sender transmits data.
The three types of credits are:

• Posted (P) – Memory writes, messages.

• Non-Posted (NP) – Memory reads, I/O transactions.

• Completion (Cpl) – Responses to read requests.

4. What is an MRd vs. MWr TLP? How does PCIe differentiate between memory read and
write transactions?

Answer:
 • MRd (Memory Read Request): A PCIe device requests data from memory or another
device.

• MWr (Memory Write Request): A PCIe device writes data to memory or another
device.

• PCIe differentiates them using TLP Header Type fields:

o MRd = Type 00000b

o MWr = Type 00001b

5. How does PCIe support virtualization? Explain SR-IOV and MR-IOV.

Answer:
PCIe supports Single Root I/O Virtualization (SR-IOV) and Multi-Root I/O Virtualization
(MR-IOV) to allow multiple virtual machines (VMs) to share a PCIe device.

• SR-IOV: Creates Virtual Functions (VFs) that VMs can use while a single Physical
Function (PF) remains for management.

• MR-IOV: Extends SR-IOV to support multiple Root Complexes sharing a PCIe device.

6. What are the key differences between a Root Complex, Endpoint, Switch, and Bridge in
PCIe?

Answer:

• Root Complex (RC): Connects the CPU to PCIe devices.

• Endpoint (EP): A device (GPU, SSD, NIC) that communicates with the Root Complex.

• Switch: Provides connectivity between multiple PCIe devices.

• Bridge: Connects legacy PCI/PCI-X devices to PCIe.

7. Describe the concept of ‘Replay Buffer’ in PCIe. How does it improve data integrity?

Answer:
Each transmitter stores recently sent TLPs in a Replay Buffer. If the receiver detects an error
(via LCRC check) and sends a NAK, the transmitter retransmits the stored TLPs, ensuring data
integrity.
8. Explain how PCIe performs error detection and correction. What are the different types
of errors?

Answer:
PCIe uses:

• LCRC (Link CRC): Detects transmission errors.

• ACK/NAK Mechanism: Retransmits corrupted data.

• Advanced Error Reporting (AER): Reports and handles errors at the OS level.

Types of errors:

• Correctable Errors: Automatically fixed (e.g., bit flips).

• Uncorrectable Errors: Fatal errors requiring system intervention.

9. What is the role of LCRC in PCIe? At which layer is it used?

Answer:
LCRC (Link CRC) is a checksum added by the Data Link Layer to detect transmission errors. If
an error is found, the receiver sends a NAK to request a retransmission.

10. How does PCIe implement ordering rules? Explain the concept of relaxed ordering.

Answer:
PCIe normally maintains strict ordering for transactions, but Relaxed Ordering (RO) allows
certain transactions (e.g., writes) to bypass others for improved performance.

11. What is a Non-Posted vs. Posted transaction in PCIe?

Answer:

• Posted Transaction (P): No response required (e.g., Memory Write).

• Non-Posted Transaction (NP): Requires a response (e.g., Memory Read).

12. How does PCIe support atomic operations?

Answer:
PCIe supports AtomicOps (e.g., Atomic Compare & Swap, Atomic Fetch & Add) to ensure
thread-safe operations across multiple devices.
13. What is the function of a Completion TLP?

Answer:
A Completion TLP (Cpl) is used to return data from a Non-Posted Request (e.g., memory
read response).

14. How does PCIe handle latency-sensitive data, such as real-time audio/video streams?

Answer:
PCIe supports Traffic Classes (TC) and Virtual Channels (VC) to prioritize latency-sensitive
transactions.

15. Explain the concept of Max Payload Size (MPS) and Max Read Request Size (MRRS).

Answer:

• MPS (Max Payload Size): Defines the largest TLP payload a device can send.

• MRRS (Max Read Request Size): Limits the maximum data a single read request can
fetch.

Larger values improve throughput but may increase latency.

16. Why does PCIe use credit-based flow control instead of traditional ACK/NACK?

Answer:
Credit-based flow control prevents buffer overflow and eliminates the need for per-packet
ACKs, reducing overhead.

17. How does PCIe handle congestion?

Answer:
If a receiver runs out of buffer space, it stops advertising credits, preventing further data
transmission.

18. Explain the role of ACK/NAK DLLPs in PCIe.

Answer:

• ACK: Confirms correct reception of a TLP.

19. What are the major enhancements in PCIe Gen4 and Gen5 compared to Gen3?

Answer:

• PCIe Gen4: Doubled bandwidth (16 GT/s per lane), better signal integrity.

• PCIe Gen5: Further doubled speed (32 GT/s per lane), enhanced equalization.

20. How does PCIe handle QoS (Quality of Service)?

Answer:
PCIe uses Traffic Classes (TC) and Virtual Channels (VC) to ensure high-priority data gets
transmitted first.

21. What is the significance of equalization in PCIe?

Answer:
PCIe uses Tx and Rx equalization to compensate for signal loss over long traces, improving
signal integrity.