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Assignment_1_24_Detailed_Solution

The document provides detailed solutions to an assignment on System Design through Verilog from IIT Guwahati, covering various questions related to FPGA characteristics, Verilog syntax, and operations. It includes explanations for correct answers and references to video timestamps for further clarification. Key topics include FPGA design flow, number representation in Verilog, module functionality, and binary operations.

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Eswar Adithya
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10 views

Assignment_1_24_Detailed_Solution

The document provides detailed solutions to an assignment on System Design through Verilog from IIT Guwahati, covering various questions related to FPGA characteristics, Verilog syntax, and operations. It includes explanations for correct answers and references to video timestamps for further clarification. Key topics include FPGA design flow, number representation in Verilog, module functionality, and binary operations.

Uploaded by

Eswar Adithya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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NPTEL Online Certification Course

System Design Through VERILOG


Assignment 1: Detailed Solution
Indian Institute of Technology Guwahati

1. Which of the following statement is FALSE with respect to FPGA?


(A) FPGA design flow is simpler compared to ASIC
(B) FPGA production cost is higher than ASIC
(C) FPGA design is less optimized compared to ASIC
(D) FPGA design is less energy-efficient
Answer: B
Detailed Solution: Refer @12:49 https://youtu.be/gaESpBmDsoQ?t=769

2. Which of the following syntax is correct for the representation of numbers in Verilog
(A) <size>’<radix><value>
(B) <size><radix>’<value>
(C) <radix>’<size><value>
(D) <value>’<radix><size>
Answer: A
Detailed Solution: Refer @ 16:45 https://youtu.be/gaESpBmDsoQ?t=1005

3. Which of the following is correct regarding the modules in Verilog


(A) Basic building blocks
(B) Collection of lower-level design blocks
(C) Provides functionality to the higher-level blocks
(D) All of the above.
Answer: D
Detailed Solution: Refer @ 31:44 https://youtu.be/gaESpBmDsoQ?t=1904

4. The number 4’ha in Verilog is equivalent to


(A) 4’o12
(B) 4’b1010
(C) 4’d10
(D) All of the above
Answer: D
Detailed Solution: Refer @ 16:45 https://youtu.be/gaESpBmDsoQ?t=1005
NPTEL Online Certification Course
System Design Through VERILOG
Assignment 1: Detailed Solution
Indian Institute of Technology Guwahati

5. What is the binary value of p in the Verilog operation 5’bz0x10 !== 5’bz0010=p?
(A) 0
(B) 1
(C) z
(D) x
Answer: B
Detailed Solution: a !== b represents a is not equal to b (case inequality). So the value
of p is 1.
6. Which of the following is FALSE?
(A) 5'bz0x11 !== 5'bz0011 = 1
(B) 5'bx0x11 !== 5'bx0001 = 1
(C) 5'bx0x11 === 5'bx0011 = 0
(D) 5 == 5 = 1
Answer: C
Detailed Solution: ===, !== are case equality operators where operands are compared
bit by bit including x and z. Hence, 4'bx0x1 === 4'bx001 is FALSE(= 0).

7. If a=5’b11011; d=a >> 1; then the value of d is


(A) 01101
(B) 01110
(C) 10011
(D) 10110
Answer: A
Detailed Solution: >> is a binary right shift operation adding 0’s to the MSB. Hence, >>1
shifts the binary 11011 to right by 1 bit and pads the MSB with 0’s giving the result
01101.
NPTEL Online Certification Course
System Design Through VERILOG
Assignment 1: Detailed Solution
Indian Institute of Technology Guwahati

8. What will be the output of the following code?


always (@ X or Y)
begin
X = 2;
Y =3;
#10;
X <= Y;
Y<=X;
end
(A) X = 2, Y = 2
(B) X = 3, Y = 3
(C) X = 3, Y =2
(D) X = 2, Y = 3
Answer: C
Detailed Solution: The operator “< =” represents non-blocking statement
assignments. After the execution of the given Verilog code, X will get assigned the
value of Y and Y will get assigned the value of X.

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