UNIT-I

DIGITAL LOGIC CIRCUITS

1.DIGITAL COMPUTERS:

A Digital computer can be considered as a digital system that performs

various computational tasks.

The first electronic digital computer was developed in the late 1940s and was used
primarily for numerical computations.

By convention, the digital computers use the binary number system, which has two
digits: 0 and 1. A binary digit is called a bit.

A computer system is subdivided into two functional entities: Hardware and Software.

The hardware consists of all the electronic components and electromechanical devices
that comprise the physical entity of the device.

The software of the computer consists of the instructions and data that the computer
manipulates to perform various data-processing tasks.

 The Central Processing Unit (CPU) contains an arithmetic and logic unit for
manipulating data, a number of registers for storing data, and a control
circuit for fetching and executing instructions.
  The memory unit of a digital computer contains storage for instructions and
data.
 The Random Access Memory (RAM) for real-time processing of the data.
 The Input-Output devices for generating inputs from the user and displaying
the final results to the user.
 The Input-Output devices connected to the computer include the keyboard,
mouse, terminals, magnetic disk drives, and other communication devices.

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2.LOGIC GATES:
 The logic gates are the main structural part of a digital system.
 Logic Gates are a block of hardware that produces signals of binary 1 or 0
when input logic requirements are satisfied.
 Each gate has a distinct graphic symbol, and its operation can be described
by means of algebraic expressions.
 The seven basic logic gates includes: AND, OR, XOR, NOT, NAND, NOR,
and XNOR.
 The relationship between the input-output binary variables for each gate can
be represented in tabular form by a truth table.
 Each gate has one or two binary input variables designated by A and B and
one binary output variable designated by x.

(i)AND GATE: The AND gate is an electronic circuit which gives a high output only if
all its inputs are high. The AND operation is represented by a dot (.) sign.

(ii)OR GATE: The OR gate is an electronic circuit which gives a high output if one or
more of its inputs are high. The operation performed by an OR gate is represented by a
plus (+) sign.
 (iii)NOT GATE: The NOT gate is an electronic circuit which produces an inverted
version of the input at its output. It is also known as an Inverter.

(iv)NAND GATE: The NOT-AND (NAND) gate which is equal to an AND gate
followed by a NOT gate. The NAND gate gives a high output if any of the inputs are low.
The NAND gate is represented by a AND gate with a small circle on the output. The small
circle represents inversion.

(v)NOR GATE: The NOT-OR (NOR) gate which is equal to an OR gate followed by a
NOT gate. The NOR gate gives a low output if any of the inputs are high. The NOR
gate is represented by an OR gate with a small circle on the output. The small circle
represents inversion.
 (vi)Exclusive-OR/ XOR GATE: The 'Exclusive-OR' gate is a circuit which will give a
high output if one of its inputs is high but not both of them. The XOR operation is
represented by an encircled plus sign.

(vii)EXCLUSIVE-NOR/Equivalence GATE: The 'Exclusive-NOR' gate is a circuit

that does the inverse operation to the XOR gate. It will give a low output if one of its
inputs is high but not both of them. The small circle represents inversion.

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3.Boolean algebra:

Boolean algebra can be considered as an algebra that deals with binary variables
and logic operations. Boolean algebraic variables are designated by letters such as
A, B, x, and y. The basic operations performed are AND, OR, and complement.

The Boolean algebraic functions are mostly expressed with binary

variables, logic operation symbols, parentheses, and equal sign. For a given value of
variables, the Boolean function can be either 1 or 0. For instance, consider the
Boolean function:
 F = x + y'z

The logic diagram for the Boolean function F = x + y'z can be represented as:

 The Boolean function F = x + y'z is transformed from an algebraic

expression into a logic diagram composed of AND, OR, and inverter gates.
 Inverter at input 'y' generates its complement y'.
 There is an AND gate for the term y'z, and an OR gate is used to combine
the two terms (x and y'z).
 The variables of the function are taken to be the inputs of the circuit, and the
variable symbol of the function is taken as the output of the circuit.
 The truth table for the Boolean function F = x + y'z can be represented as:

The truth table for the Boolean function F = x + y'z can be represented as:
Examples of Boolean algebra simplifications using logic gates:

In this section, we will look at some of the examples of Boolean algebra

simplification using Logic gates.

1.F1 = xyz'

2. F2 = x + y'z

3. F3 = xy' + x'z

4. F4 = x'y'z + x'yz + xy'

Laws of Boolean algebra:

The basic Laws of Boolean Algebra can be stated as follows:

 Commutative Law states that the interchanging of the order of operands in a
Boolean equation does not change its result. For example:

 OR operator → A + B = B + A
 AND operator → A * B = B * A

 Associative Law of multiplication states that the AND operation are done on
two or more than two variables. For example:
A * (B * C) = (A * B) * C
 Distributive Law states that the multiplication of two variables and adding the
result with a variable will result in the same value as multiplication of addition
of the variable with individual variables. For example:
A + BC = (A + B) (A + C).
 Annulment law:
A.0 = 0
A+1=1
 Identity law:
A.1 = A
A+0=A
 Idempotent law:
A+A=A
A.A = A
 Complement law:
A + A' = 1
A.A'= 0
 Double negation law:
((A)')' = A
 Absorption law:
A.(A+B) = A
A + AB = A

De Morgan's Law is also known as De Morgan's theorem, works

depending on the concept of Duality. Duality states that interchanging the operators
and variables in a function, such as replacing 0 with 1 and 1 with 0, AND operator
with OR operator and OR operator with AND operator.
 De Morgan stated 2 theorems, which will help us in solving the
algebraic problems in digital electronics. The De Morgan's statements are:

1."The negation of a conjunction is the disjunction of the negations", which means that
the complement of the product of 2 variables is equal to the sum of the compliments of
individual variables. For example, (A.B)' = A' + B'.

2."The negation of disjunction is the conjunction of the negations", which means that
compliment of the sum of two variables is equal to the product of the complement of
each variable. For example, (A + B)' = A'B'.

Simplification using Boolean algebra:

Let us consider an example of a Boolean function: AB+A (B+C) + B (B+C)

The logic diagram for the Boolean function AB+A (B+C) + B (B+C) can be
represented as:

We will simplify this Boolean function on the basis of rules given by Boolean algebra.

AB + A (B+C) + B (B+C)

AB + AB + AC + BB + BC {Distributive law; A (B+C) = AB+AC, B (B+C) = BB+BC}

AB + AB + AC + B + BC {Idempotent law; BB = B}

AB + AC + B + BC {Idempotent law; AB+AB = AB}

AB + AC +B {Absorption law; B+BC = B}

B + AC {Absorption law; AB+B = B}

Hence, the simplified Boolean function will be B + AC.

 The logic diagram for Boolean function B + AC can be represented as:

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4.Map Simplification:
The Map method involves a simple, straightforward procedure for
simplifying Boolean expressions.

Map simplification may be regarded as a pictorial arrangement of the truth table which
allows an easy interpretation for choosing the minimum number of terms needed to
express the function algebraically. The map method is also known as Karnaugh map
or K-map.

Each combination of the variables in a truth table is called a mid-term.

There are four min-terms in a two variable map. Therefore, the map
consists of four squares, one for each min-term. The 0's and 1's marked for each row,
and each column designates the values of variable x and y, respectively.

Two-variable map:

Representation of functions in the two-variable map:

Three variable map: There are eight min-terms in a three-variable map. Therefore,
the map consists of eight squares.

Three variable map:

 The map was drawn in part (b) in the above image is marked with numbers in
each row and each column to show the relationship between the squares and the
three variables.
 Any two adjacent squares in the map differ by only one variable, which is
primed in one square and unprimed in the other. For example, m5 and m7 lie in
the two adjacent squares. Variable y is primed in m5 and unprimed in m7,
whereas the other two variables are the same in both the squares.
 From the postulates of Boolean algebra, it follows that the sum of two min-
terms in adjacent squares can be simplified to a single AND term consisting of
only two literals. For example, consider the sum of two adjacent squares say m5
and m7:
m5+m7 = xy'z+xyz= xz(y'+y)= xz.

Examples of Boolean algebra simplifications using the map method

1. F(x,y,z) = Σ (2,3,4,5)

First, 1 is marked in each min-term that represents the function. Hence,

010, 011, 100, 101 are marked with 1's.

Subsequently, we have to find possible adjacent squares. These are

indicated in the map by two rectangles, each enclosing two 1's.
The upper right rectangle represents the area enclosed by x'y.

The lower left rectangle represents the product term xy'.

The sum of these two terms gives the simplified expression:

F= x'y+ xy'

Algebraically verification:

m0+m2 = x'y'z'+ x'yz'= x'z'(y'+y) = x'z'

m4+m6 = xy'z' + xyz'= xz' + (y'+y) = xz'

2. F(x,y,z) = Σ(3,4,6,7)

As you can see, there are four squares marked with 1's, one for each min-
term of the function.

The other two adjacent squares are combined in the third column to give a
two-literal term yz.

The remaining two squares with 1's are shown in the above diagram
with their values enclosed in half rectangles. When these two half rectangles are
combined, it yields two literal term xz'.

The simplified function becomes F= yz+xz'.

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5.Combinational Circuits:
A combinational circuit comprises of logic gates whose outputs at any
time are determined directly from the present combination of inputs without any
regard to previous inputs.

A combinational circuit performs a specific information-processing

operation fully specified logically by a set of Boolean functions.

The basic components of a combinational circuit are: input variables,

logic gates, and output variables.

The 'n' input variables come from an external source whereas the 'm'
output variables go to an external destination. In many applications, the source or
destination are storage registers.

The combinational circuit that performs the addition of two bits is

called a half adder and the one that performs the addition of three bits (two
significant bits and a previous carry) is a full adder.

Half – Adder:

A Half-adder circuit needs two binary inputs and two binary outputs. The input
variable shows the augend and addend bits whereas the output variable produces the
sum and carry. We can understand the function of a half-adder by formulating a truth
table. The truth table for a half-adder is:

 'x' and 'y' are the two inputs, and S (Sum) and C (Carry) are the two outputs.
 The Carry output is '0' unless both the inputs are 1.
  'S' represents the least significant bit of the sum.

The simplified sum of products (SOP) expressions is:

S = x'y+xy', C = xy

The logic diagram for a half-adder circuit can be represented as:

Full – Adder:

This circuit needs three binary inputs and two binary outputs. The
truth table for a full-adder is:

 Two of the input variable 'x' and 'y', represent the two significant bits to be
added.
 The third input variable 'z', represents the carry from the previous lower
significant position.
 The outputs are designated by the symbol 'S' for sum and 'C' for carry.
 The eight rows under the input variables designate all possible combinations of
0's, and 1's that these variables may have.
  The input-output logical relationship of the full-adder circuit may be expressed
in two Boolean functions, one for each output variable.
 Each output Boolean function can be simplified by using a unique map method.

Maps for a full-adder:

The logic diagram for a full-adder circuit can be represented as:

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6.S-R Flip-flop/Basic Flip-Flop:

Flip flops are an application of logic gates. A flip-flop circuit can
remain in a binary state indefinitely (as long as power is delivered to the circuit) until
directed by an input signal to switch states.

S-R flip-flop stands for SET-RESET flip-flops.

 The SET-RESET flip-flop consists of two NOR gates and also two NAND
gates.

These flip-flops are also called S-R Latch.

The design of these flip flops also includes two inputs, called the SET [S] and RESET
[R]. There are also two outputs, Q and Q'.
Clocked S-R Flip-Flop: The operation of a basic flip-flop can be modified by providing an
additional control input that determines when the state of the circuit is to be changed.

The limitation with a S-R flip-flop using NOR and NAND gate is the invalid
state. This problem can be overcome by using a stable SR flip-flop that can change
outputs when certain invalid states are met, regardless of the condition of either the Set
or the Reset inputs.

A clock pulse is given to the inputs of the AND Gate. If the value of
the clock pulse is '0', the outputs of both the AND Gates remain '0'.

D Flip-Flop: D flip-flop is a slight modification of clocked SR flip-flop.

From the above figure, you can see that the D input is connected to the S input and the
complement of the D input is connected to the R input.

When the value of CP is '1' (HIGH), the flip-flop moves to the SET state if it is '0'
(LOW), the flip-flop switches to the CLEAR state.
J-K Flip-flop: J-K flip-flop can be considered as a modification of the S-R flip-flop.

The main difference is that the intermediate state is more refined and precise than that
of an S-R flip-flop.

The characteristics of inputs 'J' and 'K' is same as the 'S' and 'R' inputs of the S-R flip-
flop.

J stands for SET, and 'K' stands for CLEAR.

When both the inputs J and K have a HIGH state, the flip-flop switches to the
complement state, so, for a value of Q = 1, it switches to Q=0, and for a value of Q =
0, it switches to Q=1.
 T Flip-Flop: T flip-flop is a much simpler version of the J-K flip-flop.

Both the J and K inputs are connected and are also called as a single input J-K Flip-
flop.

Triggering of Flip-Flops: The state of the flip-flop is changed by a momentary change in

the input signal. This momentary change is known as Trigger, and the transition it
causes is said to triggering the flip-flop.

Pulses trigger clocked flip-flops.

A pulse start from the initial value of '0', goes momentarily to '1', and after a short
while, returns to its initial '0' value.

A clock pulse is either positive or negative.

A positive clock source remains at '0' during the interval between pulses and goes to
1 during the occurrence of a pulse.
 The pulse goes through two signal transition: from '0' to '1' and return from '1' to '0'.

Definition of clock pulse transition:

The positive transition is defined as a positive edge and the negative

transition as a negative edge.

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DIGITAL COMPONENTS
1.INTEGRATED CIRCUITS:
 Digital circuits are constructed with integrated circuits. An integrated circuit
(abbreviated IC) is a small silicon semiconductor crystal called a chip
containing the electronic components for the digital gates.
 The various gates are interconnected inside the chip to form the required
circuit.

 The chip is mounted in a ceramic or plastic container, and connections are

welded by thin gold wires to external pins to form the integrated circuit.
 The number of pins may range from 14 in a small IC package to 100 or more
in a larger package. Each IC has a numeric designation printed on the surface of
the package for identification.
  Small-scale integration (SSI) devices contain several independent gates in a
single package. The inputs and outputs of the gates are connected directly to the
pins in the package. The number of gates is usually less than 10 and is limited
by the number of pins available in the IC.
 Medium-scale integration (MSI) devices have a complexity of approximately
10 to 200 gates in a single package. They usually perform specific elementary
digital functions such as decoders, adders, and registers.
 Large-scale integration (LSI) devices contain between 200 and a few thousand
gates in a single package. They include digital systems, such as processors,
memory chips, and programmable modules.
 Very-large-scale integration (VLSI) devices contain thousands of gates within
a single package. Examples are large memory arrays and complex
microcomputer chips.
 Many different logic families of integrated circuits have been introduced
commercially. The following are the most popular.
1. Transistor-transistor logic
2. Emitter-coupled logic
3. Metal-oxide semiconductor
4. Complementary metal-oxide semiconductor

 TTL is a widespread logic family that has been in operation for many years
and is considered as standard. ECL has an advantage in systems requiring high-
speed operation. MOS is suitable for circuits that need high component density,
and CMOS is preferable in systems requiring low power consumption.

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2.Decoders:
 Discrete quantities of information are represented in digital computers with
binary codes. A binary code of n bits is capable of representing up to 2n distinct
elements of the coded information.
 A decoder is a combinational circuit that converts binary information from the
n coded inputs to a maximum of 2n unique outputs.
 If the n-bit coded information has unused bit combinations, the decoder may
have less than 2n outputs.
 The decoders presented in this section are called n-to-m-line decoders, where
m ≤ 2n. Their purpose is to generate the 2n (or fewer) binary combinations of the
 n input variables. A decoder has n inputs and m outputs and is also referred to
as an n x m decoder.
 The logic diagram of a 3-to-8-line decoder is shown in Fig. below The three
data inputs, A0, A1 and A2, are decoded into eight outputs, each output.

 representing one of the combinations of the three binary input variables. The
three inverters provide the complement of the inputs, and each of the eight AND
gates generates one of the binary combination.

 A particular application of this decoder is a binary-to-octal conversion. The

input variables represent a binary number and the outputs represent the eight
digits of the octal number system.
 However, a 3-to-8-line decoder can be used for decoding any 3-bit code to
provide eight outputs, one for each combination of the binary code. Commercial
decoders include one or more enable inputs to control the operation of the
circuit. The decoder of Fig. 2-1 has one enable input, E.
 The decoder is enabled when E is equal to 1 and disabled when E is equal to
0. The operation of the decoder can be clarified using the truth table listed in
Table 2-1 . When the enable input E is equal to 0, all the outputs are equal to 0
regardless of the values of the other three data inputs.
 The three x's in the table designate don't-care conditions. When the enable
input is equal to I, the decoder operates in a normal fashion. For each possible
input combination, there are seven outputs that are equal to 0 and only one that
is equal to I.
 The output variable whose value is equal to 1 represents the octal number
equivalent of the binary number that is available in the input data lines.
NAND Gate Decoder:
 Some decoders are constructed with NAND instead of AND gates. Since a
NAND gate produces the AND operation with an inverted output,it becomes
more economical to generate the decoder outputs in their complement form.
 A 2-to-4-line decoder with an enable input constructed with NAND gates is
shown in Fig. below. The circuit operates with complemented outputs and a
complemented enable input E.
 The decoder is enabled when E is equal to 0. As indicated by the truth table,
only one output is equal to 0 at any given time; the other three outputs are equal
to 1.
 The output whose value is equal to 0 represents the equivalent binary number
in inputs A1 and A0. The circuit is disabled when E is equal to 1, regardless of
the values of the other two inputs.

 When the circuit is disabled, none of the outputs are selected and all outputs
are equal to 1.
 In general, a decoder may operate with complemented or uncomplemented
outputs. The enable input may be activated with a 0 or with a 1 signal level.
  Some decoders have two or more enable inputs that must satisfy a given logic
condition in order to enable the circuit.

Encoders:
 An encoder is a digital circuit that performs the inverse operation of a
decoder.
 An encoder has 2n (or less) input lines and n output lines. The output lines
generate the binary code corresponding to the input value. An example of an
encoder is the octal-to-binary encoder, whose truth table is given in Table
below.
 It has eight inputs, one for each of the octal digits, and three outputs that
generate the corresponding binary number. It is assumed that only one input
has a value of 1 at any given time; otherwise, the circuit has no meaning.

 The encoder can be implemented with OR gates whose inputs are

determined directly from the truth table. Output A0 = 1 if the input octal digit
is 1 or 3 or 5 or 7.
 Similar conditions apply for the other two outputs. These conditions can be
expressed by the following Boolean functions:
 A0 = D1 + D3 + D5 + D7
 A1 = D2 + D3 + D6 + D7
 A2 = D4 + D5 + D6 + D7
 The encoder can be implemented with three OR gates.
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3.Multiplexers:
 A multiplexer is a combinational circuit that receives binary information
from one of 2n input data lines and directs it to a single output line.
 The selection of a particular input data line for the output is determined
by a set of selection inputs.
 A 2n-to-1 multiplexer has 2n input data lines and n input selection lines
whose bit combinations determine which input data are selected for the
output.
 A 4-to-1-line multiplexer is shown in Fig. below. Each of the four data
inputs I0 through I3 is applied to one input of an AND gate. The two
selection inputs S1 and S0 are decoded to select a particular AND gate. The
outputs of the AND gates are applied to a single OR gate to provide the
single output.
 To demonstrate the circuit operation, consider the case when S1S0 = 10.
The AND gate associated with input I2 has two of its inputs equal to 1. The
third input of the gate is connected to I2 The other three AND gates have at
least one input equal to 0, which makes their outputs equal to 0.
 The OR gate output is now equal to the value of I2, thus providing a path
from the selected input to the output. The 4-to-1 line multiplexer of Fig.
below has six inputs and one output.
 A truth table describing the circuit needs 64 rows since six input variables
can have 26 binary combinations. This is an excessively long table and will
not be shown here.
 A more convenient way to describe the operation of multiplexers is by
means of a function table. The function table for the multiplexer is shown in
Table below. The table demonstrates the relationship between the four data
inputs and the single output as a function of the selection inputs S1 and S0.

 When the selection inputs are equal to 00, output Y is equal to input I0
When the selection inputs are equal to 01, input I1 has a path to output Y,
and similarly for the other two combinations.
  The multiplexer is also called a data selector, since it selects one of many
data inputs and steers the binary information to the output.

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4.Registers:
 A register is a group of flip-flops with each flip-flop capable of storing one bit
of information.
 An n-bit register has a group of n flip-flops and is capable of storing any
binary information of n bits. In addition to the flip-flops, a register may have
combinational gates that perform certain data-processing tasks.
 In its broadest definition, a register consists of a group of flip-flops and gates
that effect their transition. The flip-flops hold the binary information and the
gates control when and how new information is transferred into the register.
  Various types of registers are available commercially. The simplest register is
one that consists only of flip-flops, with no external gates. Figure below shows
such a register constructed with four D flip-flops.
 The common clock input triggers all flip-flops on the rising edge of each
pulse, and the binary data available at the four inputs are transferred into the 4-
bit register. The four outputs can be sampled at any time to obtain the binary
information stored in the register.
 The clear input goes to a special terminal in each flip-flop. When this input
goes to 0, all flip-flops are reset asynchronously. The clear input is useful for
clearing the register to all 0's prior to its clocked operation.
 The clear input must be maintained at logic 1 during normal clocked
operation. Note that the clock signal enables the D input but that the clear. input
is independent of the clock.
 The transfer of new information into a register is referred to as loading the
register.
 If all the bits of the register are loaded simultaneously with a common clock
pulse transition, we say that the loading is done in parallel.
 A clock transition applied to the C inputs of the register of Fig. above will
load all four inputs I0 through I3 in parallel.
 In this configuration, the clock must be inhibited from the circuit if the content
of the register must be left unchanged.
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5.Shift Registers:
 A register capable of shifting its binary information in one or both directions is
called a shift register.
 The logical configuration of a shift register consists of a chain of flip-flops in
cascade, with the output of one flip-flop connected to the input of the next flip-
flop.
 All flip-flops receive common clock pulses that initiate the shift from one stage
to the next.
 The simplest possible shift register is one that uses only flip-flops, as shown
in Fig. below. The output of a given flip-flop is connected to the D input of the
flip-flop at its right.
  The clock is common to all flip-flops. The serial input determines what goes
into the leftmost position during the shift. The serial output is taken from the
output of the rightmost flip-flop.
 Sometimes it is necessary to control the shift so that it occurs with certain
clock pulses but not with others. This can be done by inhibiting the clock from
the input of the register if we do not want it to shift. When the shift register of
Fig below is used, the shift can be controlled by connecting the clock to the
input of an AND gate, and a second input of the AND gate can then control the
shift by inhibiting the clock.
 However, it is also possible to provide extra circuits to control the shift operation
through the D inputs of the flip-flops rather than the clock input.

Bidirectional Shift Register with Parallel Load:

 A register capable of shifting in one direction only is called a unidirectional
shift register.
 A register that can shift in both directions is called a bidirectional shift
register. Some shift registers provide the necessary input and output
terminals for parallel transfer.
 The most general shift register has all the capabilities listed below. Others
may have some of these capabilities, with at least one shift operation.
o An input for clock pulses to synchronize all operations.
o A shift-right operation and a serial input line associated with the
shiftright.
o A shift-left operation and a serial input line associated with the shift-left.
o A parallel load operation and n input lines associated with the parallel
transfer.
o n parallel output lines.
o A control state that leaves the information in the register unchanged
even though clock pulses are applied continuously.
 *****

6.Binary Counters
 A register that goes through a predetermined sequence of states upon the
application of input pulses is called a counter.
 The input pulses may be clock pulses or may originate from an external
source. They may occur at uniform intervals of time or at random.
 Counters are found in almost all equipment containing digital logic. They
are used for counting the number of occurrences of an event and are useful for
generating timing signals to control the sequence of operations in digital
computers.
 Of the various sequences a counter may follow, the straight binary sequence
is the simplest and most straightforward. A counter that follows the binary
number sequence is called a binary counter. An n-bit binary counter is a register
of n flip-flops and associated gates that follows a sequence of states according
to the binary count of n bits, from 0 to 2n - 1.
 A counter circuit will usually employ flip-flops with complementing
capabilities. Both T and JK flip-flops have this property. Remember that a JK
flip-flop is complemented if both its J and K inputs are 1 and the clock goes
through a positive transition. The output of the flip-flop does not change if J = K
= 0.
 Synchronous binary counters have a regular pattern, as can be seen from the
4-bit binary counter shown in Fig. below. The C inputs of all flip-flops receive
the common clock.
 If the count enable is 0, all J and K inputs are maintained

at 0 and the output of the counter does not change.

 The first stage A0 is complemented when the counter is enabled and the
clock goes through a positive transition. Each of the other three flip-flops are
complemented when all previous least significant flip-flops are equal to 1 and
the count is enabled.
 The chain of AND gates generate the required logic for the J and K inputs. The
output carry can be used to extend the counter to more stages, with each stage
having an additional flip-flop and an AND gate.

*****
7.Memory Unit:
 A memory unit is a collection of storage cells together with associated circuits
needed to transfer information in and out of storage.
 The memory stores binary information in groups of bits called words. A
word in memory is an entity of bits that move in and out of storage as a unit.
 A memory word is a group of 1's and 0's and may represent a number, an
instruction code, one or more alphanumeric characters, or any other binary-
coded information.
 A group of byte eight bits is called a byte. Most computer memories use
words whose number of bits is a multiple of 8. Thus a 16-bit word contains two
bytes, and a 32-bit word is made up of four bytes. The capacity of memories in
commercial computers is usually stated as the total number of bytes that can be
stored.
 Two major types of memories are used in computer systems: random access
memory (RAM) and read-only memory (ROM).

Random-Access Memory
 In random-access memory (RAM) the memory cells can be accessed for
information transfer from any desired random location.
 That is, the process of locating a word in memory is the same and requires an
equal amount of time no matter where the cells are located physically in
memory: thus the name "random access."
 The two operations that a random-access memory can perform are the write
and read operations.
 The write signal specifies a transfer-in operation and the read signal specifies a
transfer-out operation. On accepting one of these control signals, the internal
circuits inside the memory provide the desired function.
  The memory unit will then take the bits presently available in the input data
lines and store them in the word specified by the address lines. The steps that
must be taken for the purpose of transferring a stored word out of memory are
as follows:
 The memory unit will then take the bits from the word that has been selected
by the address and apply them into the output data lines. The content of the
selected word does not change after reading.

Read-Only Memory:
 As the name implies, a read-only memory (ROM) is a memory unit that
performs the read operation only; it does not have a write capability.
 This implies that the binary information stored in a ROM is made permanent
during the hardware production of the unit and cannot be altered by writing
different words into it.
 Whereas a RAM is a general-purpose device whose contents can be altered
during the computational process, a ROM is restricted to reading words that are
permanently stored within the unit.
 The binary information to be stored, specified by the designer, is then
embedded in the unit to form the reqttired interconnection pattern.

*****
 UNIT-II
DATA REPRESENTATION
1.DATA TYPES:
Computer programs or application may use different types of data based
on the problem or requirement.

Given below is different types of data that computer uses:

 Numeric data – Integer and Real numbers
 Non-numeric data – Character data, address data, logical data
Numeric data
It can be of the following two types:
 Integers
 Real Numbers
Real numbers can be represented as:
1. Fixed point representation
2. Floating point representation
Character data
A sequence of character is called character data.
A character may be alphabetic (A-Z or a-z), numeric (0-9), special character (+, #, *,
@, etc.) or combination of all of these. A character is represented by group of bits.
When set of multiple character are combined together they form a
meaningful data. A character is represented in standard ASCII format.Another popular
format is EBCDIC used in large computer systems.

Example of character data

 Rajneesh1#
 229/3, xyZ
 Mission Milap – X/10
Logical data
A logical data is used by computer systems to take logical decisions.
Logical data is different from numeric or alphanumeric data in the way that numeric
and alphanumeric data may be associated with numbers or characters but logical data
is denoted by either of two values true (T) or false.
You can see the example of logical data in construction of truth table in logic gates.
A logical data can also be statement consisting of numeric or character data with
relational symbols (>, <, =, etc.).
Character set
Character sets can of following types in computers:
 Alphabetic characters- It consists of alphabet characters A-Z or a-z.
 Numeric characters- It consists of digits from 0 to 9.
  Special characters- Special symbols are +, *, /, -, ., <, >, =, @, %, #, etc.

*****
2.COMPLEMENTS:
Complements are used in the digital computers in order to simplify the
subtraction operation and for the logical manipulations. For each radix-r system
(radix r represents base of number system) there are two types of complements.

S.N. Complement Description

1 Radix Complement The radix complement is referred to

as the r's complement

2 Diminished Radix The diminished radix complement is

Complement referred to as the (r-1)'s complement

Binary system complements:

As the binary system has base r = 2. So the two types of complements for the
binary system are 2's complement and 1's complement.
1's complement
The 1's complement of a number is found by changing all 1's to 0's and all
0's to 1's. This is called as taking complement or 1's complement. Example of 1's
Complement is as follows.

2's complement
The 2's complement of binary number is obtained by adding 1 to the Least Significant
Bit (LSB) of 1's complement of the number.
2's complement = 1's complement + 1
Example of 2's Complement is as follows.
 *****
3.FIXED-POINT REPRESENTATION:
Digital Computers use Binary number system to represent all types
of information inside the computers. Alphanumeric characters are represented using
binary bits (i.e., 0 and 1). Digital representations are easier to design, storage is easy,
accuracy and precision are greater.
There are various types of number representation techniques for
digital number representation, for example: Binary number system, octal number
system, decimal number system, and hexadecimal number system etc. But Binary
number system is most relevant and popular for representing numbers in digital
computer system.
There are two major approaches to store real numbers (i.e., numbers
with fractional component) in modern computing. These are (i) Fixed Point Notation
and (ii) Floating Point Notation. In fixed point notation, there are a fixed number of
digits after the decimal point, whereas floating point number allows for a varying
number of digits after the decimal point.
Fixed-Point Representation:
This representation has fixed number of bits for integer part and for
fractional part. For example, if given fixed-point representation is IIII.FFFF, then you
can store minimum value is 0000.0001 and maximum value is 9999.9999. There are
three parts of a fixed-point number representation: the sign field, integer field, and
fractional field.

We can represent these numbers using:

 Signed representation: range from -(2(k-1)-1) to (2(k-1)-1), for k bits.

  1’s complement representation: range from -(2(k-1)-1) to (2(k-1)-1), for k bits.
 2’s complementation representation: range from -(2(k-1)) to (2(k-1)-1), for k bits.
2’s complementation representation is preferred in computer system, easier
for arithmetic operations.
Example −Assume number is using 32-bit format which reserve 1 bit for the sign, 15
bits for the integer part and 16 bits for the fractional part.
Then, -43.625 is represented as following

Where, 0 is used to represent + and 1 is used to represent.

000000000101011 is 15 bit binary value for decimal 43 and 1010000000000000 is 16
bit binary value for fractional 0.625.
The advantage of using a fixed-point representation is performance and
disadvantage is relatively limited range of values that they can represent. A number
whose representation exceeds 32 bits would have to be stored inexactly.

These are above smallest positive number and largest positive number
which can be store in 32-bit representation as given above format. Therefore, the
smallest positive number is 2-16≈ 0.000015 approximate and the largest positive
number is (215-1)+(1-2-16)=215(1-2-16) =32768, and gap between these numbers is 2-16.
We can move the radix point either left or right with the help of only integer
field is 1.
*****
4.FLOATING-POINT REPRESENTATION:
This representation does not reserve a specific number of bits for
the integer part or the fractional part. Instead it reserves a certain number of bits for
the number (called the mantissa or significand) and a certain number of bits to say
where within that number the decimal place sits (called the exponent).
 The floating number representation of a number has two part: the first
part represents a signed fixed point number called mantissa. The second part of
designates the position of the decimal (or binary) point and is called the exponent. The
fixed point mantissa may be fraction or an integer. Floating -point is always
interpreted to represent a number in the following form: Mxre.
Only the mantissa m and the exponent e are physically represented in
the register (including their sign). A floating-point binary number is represented in a
similar manner except that is uses base 2 for the exponent. A floating-point number is
said to be normalized if the most significant digit of the mantissa is 1.

So, actual number is (-1)s(1+m)x2(e-Bias), where s is the sign bit, m is the mantissa, e is
the exponent value, and Bias is the bias number.
The floating point representation is more flexible. Any non-zero
number can be represented in the normalized form of ±(1.b1b2b3 ...)2x2n .This is
normalized form of a number x.
Example −Suppose number is using 32-bit format: the 1 bit sign bit, 8 bits for signed
exponent, and 23 bits for the fractional part. The leading bit 1 is not stored (as it is
always 1 for a normalized number) and is referred to as a “hidden bit”.
Then −53.5 is normalized as -53.5=(-110101.1)2=(-
1.101011)x25 , which is represented as following below,

Where 00000101 is the 8-bit binary value of exponent value +5.

*****
 REGISTER TRANSFER & MICRO OPERATIONS
1.Register transfer language:
In symbolic notation, it is used to describe the micro-operations transfer
among registers. It is a kind of intermediate representation (IR) that is very close to
assembly language, such as that which is used in a compiler.The term “Register
Transfer” can perform micro-operations and transfer the result of operation to the
same or other register.
Micro-operations : The operation executed on the data store in registers are called
micro-operations. They are detailed low-level instructions used in some designs to
implement complex machine instructions.
Register Transfer: The information transformed from one register to another
register is represented in symbolic form by replacement operator is called Register
Transfer.
Replacement Operator : In the statement, R2 <- R1, <- acts as a replacement
operator. This statement defines the transfer of content of register R1 into register
R2.
There are various methods of RTL –
1. General way of representing a register is by the name of the register inclosed in a
rectangular box as shown in (a).

2. Register is numbered in a sequence of 0 to (n-1) as shown in (b).

3. The numbering of bits in a register can be marked on the top of the box as shown
in (c).

4. A 16-bit register PC is divided into 2 parts- Bits (0 to 7) are assigned with lower
byte of 16-bit address and bits (8 to 15) are assigned with higher bytes of 16-bit
address as shown in (d).

Basic symbols of RTL :

Symbol Description Example

Letters and MAR, R1,

Numbers Denotes a Register R2

R1(8-bit)
R1(0-7)
() Denotes a part of register

<- Denotes a transfer of information R2 <- R1

R1 <- R2
R2 <- R1
Specify two micro-operations of Register
, Transfer

P : R2 <- R1
if P=1
: Denotes conditional operations

Naming Operator Denotes another name for an already existing

(:=) register/alias Ra := R1

Register Transfer Operations:

The operations performed on the data stored in the registers are
referred to as register transfer operations.
There are different types of register transfer operations:
1. Simple Transfer – R2 <- R1:
The content of R1 are copied into R2 without affecting the content of
R1. It is an unconditional type of transfer operation.
2. Conditional Transfer:
 It indicates that if P=1, then the content of R1 is transferred to R2. It
is a unidirectional operation.
3. Simultaneous Operations: If 2 or more operations are to occur simultaneously
then they are separated with comma (,).

If the control function P=1, then load the content of R1 into R2 and at the same clock
load the content of R2 into R1.
*****

2.Register Transfer:
Information transferred from one register to another is designated in symbolic
form by means of replacement operator.

R2 ← R1

It denotes the transfer of the data from register R1 into R2.

Normally we want the transfer to occur only in predetermined control condition. This
can be shown by following if-then statement: if (P=1) then (R2 ← R1)
 Here P is a control signal generated in the control section.

Control Function: A control function is a Boolean variable that is equal to 1 or 0. The

control function is shown as:

P: R2 ← R1

The control condition is terminated with a colon. It shows that transfer operation can
be executed only if P=1.

Micro-Operations: The operations executed on data stored in registers are called

micro-operations. A micro-operation is an elementary operation performed on the
information stored in one or more registers.

Example: Shift, count, clear and load.

Types of Micro-Operations:
The micro-operations in digital computers are of 4 types:

1. Register transfer micro-operations transfer binary information from one register

to another.
2. Arithmetic micro-operations perform arithmetic operations on numeric data
stored in registers.
3. Logic micro-operations perform bit manipulation operation on non-numeric
data stored in registers.
4. Shift micro-operations perform shift micro-operations performed on data.

Arithmetic Micro-Operations: Some of the basic micro-operations are addition,

subtraction, increment and decrement.

(i)Add micro-operation: It is defined by the following statement:

R3 → R1 + R2

The above statement instructs the data or contents of register R1 to be added to data or
content of register R2 and the sum should be transferred to register R3.

(ii)Subtract micro-operation: Let us again take an example:

R3 → R1 + R2' + 1
 In subtract micro-operation, instead of using minus operator we take 1's
compliment and add 1 to the register which gets subtracted, i.e R1 - R2 is equivalent
to R3 → R1 + R2' + 1

(iii)Increment/decrement micro-operation: Increment and decrement micro-

operations are generally performed by adding and subtracting 1 to and from the
register respectively.

R1 → R1 + 1

R1 → R1 – 1

Symbolic Designation Description

R3 ← R1 + R2 Contents of R1+R2 transferred to R3.

R3 ← R1 - R2 Contents of R1-R2 transferred to R3.

R2 ← (R2)' Compliment the contents of R2.

R2 ← (R2)' + 1 2's compliment the contents of R2.

R3 ← R1 + (R2)' + 1 R1 + the 2's compliment of R2 (subtraction).

R1 ← R1 + 1 Increment the contents of R1 by 1.

R1 ← R1 - 1 Decrement the contents of R1 by 1.

(iv)Logic Micro-Operations: These are binary micro-operations performed on the

bits stored in the registers. These operations consider each bit separately and
treat them as binary variables. Let us consider the X-OR micro-operation with
the contents of two registers R1 and R2.

P: R1 ← R1 X-OR R2

In the above statement we have also included a Control Function.

Assume that each register has 3 bits. Let the content of R1 be 010 and R2 be 100. The
X-OR micro-operation will be:
Shift Micro-Operations: These are used for serial transfer of data. That means we
can shift the contents of the register to the left or right. In the shift left operation
the serial input transfers a bit to the right most position and in shift
right operation the serial input transfers a bit to the left most position.
There are three types of shifts as follows:

a) Logical Shift: It transfers 0 through the serial input. The symbol "shl" is used for
logical shift left and "shr" is used for logical shift right.

R1 ← she R1

R1 ← she R1

The register symbol must be same on both sides of arrows.

b) Circular Shift: This circulates or rotates the bits of register around the two ends
without any loss of data or contents. In this, the serial output of the shift register is
connected to its serial input. "cil" and "cir" is used for circular shift left and right
respectively.

c) Arithmetic Shift: This shifts a signed binary number to left or right. An arithmetic
shift left multiplies a signed binary number by 2 and shift left divides the number by
2. Arithmetic shift micro-operation leaves the sign bit unchanged because the signed
number remains same when it is multiplied or divided by 2.

Arithmetic logical unit: Instead of having individual registers performing the micro-
operations, computer system provides a number of registers connected to a common
unit called as Arithmetic Logical Unit (ALU). ALU is the main and one of the most
important unit inisde CPU of computer. All the logical and mathematical operations of
computer are performed here. The contents of specific register is placed in the in the
input of ALU. ALU performs the given operation and then transfer it to the destination
register.
 *****

3.Bus and Memory Transfers:

A digital system composed of many registers, and paths must be provided
to transfer information from one register to another. The number of wires connecting
all of the registers will be excessive if separate lines are used between each register
and all other registers in the system.

A bus structure, on the other hand, is more efficient for transferring

information between registers in a multi-register configuration system.

A bus consists of a set of common lines, one for each bit of register, through
which binary information is transferred one at a time. Control signals determine which
register is selected by the bus during a particular register transfer.

The following block diagram shows a Bus system for four registers. It is
constructed with the help of four 4 * 1 Multiplexers each having four data inputs (0
through 3) and two selection inputs (S1 and S2).

We have used labels to make it more convenient for you to understand the
input-output configuration of a Bus system for four registers. For instance, output 1 of
register A is connected to input 0 of MUX1.
 The two selection lines S1 and S2 are connected to the selection inputs of all
four multiplexers. The selection lines choose the four bits of one register and transfer
them into the four-line common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs
of all four multiplexers are selected and applied to the outputs that forms the bus. This,
in turn, causes the bus lines to receive the content of register A since the outputs of
this register are connected to the 0 data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will
receive the content provided by register B.

The following function table shows the register that is selected by the bus for each of
the four possible binary values of the Selection lines.

A bus system can also be constructed using three-state gates instead of

multiplexers.
The three state gates can be considered as a digital circuit that has three gates, two of
which are signals equivalent to logic 1 and 0 as in a conventional gate. However, the
third gate exhibits a high-impedance state.

The most commonly used three state gates in case of the bus system is a buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state
buffers.

 The outputs generated by the four buffers are connected to form a single bus
line.
 Only one buffer can be in active state at a given point of time.
 The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
  A 2 * 4 decoder ensures that no more than one control input is active at any
given point of time.

Memory Transfer:

Most of the standard notations used for specifying operations on memory

transfer are stated below.

 The transfer of information from a memory unit to the user end is called
a Read operation.
 The transfer of new information to be stored in the memory is called
a Write operation.
 A memory word is designated by the letter M.
 We must specify the address of memory word while writing the memory
transfer operations.
 The address register is designated by AR and the data register by DR.
 Thus, a read operation can be stated as:

1.Read: DR ← M [AR]

 The Read statement causes a transfer of information into the data register (DR)
from the memory word (M) selected by the address register (AR).
 And the corresponding write operation can be stated as:

2.Write: M [AR] ← R1

 The Write statement causes a transfer of information from register R1 into the
memory word (M) selected by address register (AR).

*****
4.Arithmetic micro operations:
We can perform arithmetic operations on the numeric data which is stored
inside the registers.
Example :
R3 <- R1 + R2
The value in register R1 is added to the value in the register R2 and then the sum is
transferred into register R3. Similarily, other arithmetic micro-operations are
performed on the registers.
Addition:
In addition micro-operation, the value in register R1 is added to the value in
the register R2 and then the sum is transferred into register R3.

Substraction:
In subtraction micro-operation, the contents of register R2 are subtracted
from contents of the register R1, and then the result is transferred into R3.

R3<- R1-R2

There is another way of doing the subtraction. In this, 2’s complement of R2 is added
to R1, which is equivalent to R1 – R2, and then the result is transferred into register
R3.

Increment: In Increment micro-operation, the value inside the R1 register is

increased by 1.

Decrement: In Decrement micro-operation, the value inside the R1 register is

decreased by 1.

1’s Complement: In this micro-operation, the complement of the value inside the
register R1 is taken.
 2’s Complement: In this micro-operation, the complement of the value inside the
register R2 is taken and then 1 is added to the value and then the final result is
transferred into the register R2. This process is also called Negation. It is equivalent
to -R2.

*****

5.Assembly Language Instructions:

Machine Instructions are commands or programs written in machine code of a
machine (computer) that it can recognize and execute.
 A machine instruction consists of several bytes in memory that tells the
processor to perform one machine operation.
 The processor looks at machine instructions in main memory one after
another, and performs one machine operation for each machine instruction.
 The collection of machine instructions in main memory is called a machine
language program.
Machine code or machine language is a set of instructions executed
directly by a computer’s central processing unit (CPU). Each instruction performs a
very specific task, such as a load, a jump, or an ALU operation on a unit of data in a
CPU register or memory. Every program directly executed by a CPU is made up of a
series of such instructions.
The general format of a machine instruction is
 Brackets indicate that a field is optional
 Label is an identifier that is assigned the address of the first byte of the
instruction in which it appears. It must be followed by “:”
 Inclusion of spaces is arbitrary, except that at least one space must be inserted;
no space would lead to an ambiguity.
 Comment field begins with a semicolon “ ; ”

1. Data transfer instructions– move, load exchange, input, output.

 MOV :Move byte or word to register or memory .
 IN, OUT: Input byte or word from port, output word to port.
 LEA: Load effective address
 LDS, LES Load pointer using data segment, extra segment .
 PUSH, POP: Push word onto stack, pop word off stack.
 XCHG: Exchange byte or word.
 XLAT: Translate byte using look-up table.
2. Arithmetic instructions – add, subtract, increment, decrement, convert byte/word
and compare.
 ADD, SUB: Add, subtract byte or word
 ADC, SBB :Add, subtract byte or word and carry (borrow).
 INC, DEC: Increment, decrement byte or word.
 NEG: Negate byte or word (two’s complement).
 CMP: Compare byte or word (subtract without storing).
 MUL, DIV: Multiply, divide byte or word (unsigned).
 IMUL, IDIV: Integer multiply, divide byte or word (signed)
 CBW, CWD: Convert byte to word, word to double word
 AAA, AAS, AAM,AAD: ASCII adjust for add, sub, mul, div .
 DAA, DAS: Decimal adjust for addition, subtraction (BCD numbers)
3. Logic instructions – AND, OR, exclusive OR, shift/rotate and test
 NOT : Logical NOT of byte or word (one’s complement)
 AND: Logical AND of byte or word
 OR: Logical OR of byte or word.
 XOR: Logical exclusive-OR of byte or word
 TEST: Test byte or word (AND without storing).
 SHL, SHR: Logical Shift rotate instruction shift left, right byte or word? by 1or
CL
 SAL, SAR: Arithmetic shift left, right byte or word? by 1 or CL
 ROL, ROR: Rotate left, right byte or word? by 1 or CL .
 RCL, RCR: Rotate left, right through carry byte or word? by 1 or CL.
4.String manipulation instruction – load, store, move, compare and scan for
byte/word
 MOVS: Move byte or word string
 MOVSB, MOVSW: Move byte, word string.
 CMPS: Compare byte or word string.
 SCAS S: can byte or word string (comparing to A or AX)
 LODS, STOS: Load, store byte or word string to AL.
5. Control transfer instructions – conditional, unconditional, call subroutine and
return from subroutine.
 JMP:Unconditional jump .it includes loop transfer and subroutine and interrupt
instructions.
 JNZ:jump till the counter value decreases to zero.It runs the loop till the value
stored in CX becomes zero
6. Loop control instructions-
 LOOP: Loop unconditional, count in CX, short jump to target address.
 LOOPE (LOOPZ): Loop if equal (zero), count in CX, short jump to target
address.
  LOOPNE (LOOPNZ): Loop if not equal (not zero), count in CX, short jump to
target address.
 JCXZ: Jump if CX equals zero (used to skip code in loop).
 Subroutine and Interrupt instructions-
 CALL, RET: Call, return from procedure (inside or outside current segment).
 INT, INTO: Software interrupt, interrupt if overflow.IRET: Return from
interrupt.
7. Processor control instructions-
Flag manipulation:
 STC, CLC, CMC: Set, clear, complement carry flag.
 STD, CLD: Set, clear direction flag.STI, CLI: Set, clear interrupt enable flag.
 PUSHF, POPF: Push flags onto stack, pop flags off stack.

*****

6. 8085 Micro processor Instruction set:

Instruction Set of 8085 An instruction is a binary pattern designed inside
a microprocessor to perform a specific function. The entire group of instructions that
a microprocessor supports is called Instruction Set. 8085 has 246 instructions. Each
instruction is represented by an 8-bit binary value.These 8-bits of binary value is
called Op-Code or Instruction Byte.

Classification of Instruction Set:

• Data Transfer Instruction

• Arithmetic Instructions

• Logical Instructions

• Branching Instructions

• Control Instructions

1. Data transfer instructions– move, load exchange, input, output.

 MOV :Move byte or word to register or memory .
 IN, OUT: Input byte or word from port, output word to port.
 LEA: Load effective address
 LDS, LES Load pointer using data segment, extra segment .
 PUSH, POP: Push word onto stack, pop word off stack.
 XCHG: Exchange byte or word.
 XLAT: Translate byte using look-up table.
2. Arithmetic instructions – add, subtract, increment, decrement, convert byte/word
and compare.
 ADD, SUB: Add, subtract byte or word
 ADC, SBB :Add, subtract byte or word and carry (borrow).
 INC, DEC: Increment, decrement byte or word.
 NEG: Negate byte or word (two’s complement).
 CMP: Compare byte or word (subtract without storing).
 MUL, DIV: Multiply, divide byte or word (unsigned).
 IMUL, IDIV: Integer multiply, divide byte or word (signed)
 CBW, CWD: Convert byte to word, word to double word
 AAA, AAS, AAM,AAD: ASCII adjust for add, sub, mule, div .
 DAA, DAS: Decimal adjust for addition, subtraction (BCD numbers)
3. Logic instructions – AND, OR, exclusive OR, shift/rotate and test
 NOT : Logical NOT of byte or word (one’s complement)
 AND: Logical AND of byte or word
 OR: Logical OR of byte or word.
 XOR: Logical exclusive-OR of byte or word
 TEST: Test byte or word (AND without storing).
 SHL, SHR: Logical Shift rotate instruction shift left, right byte or word? by 1or
CL
 SAL, SAR: Arithmetic shift left, right byte or word? by 1 or CL
 ROL, ROR: Rotate left, right byte or word? by 1 or CL .
 RCL, RCR: Rotate left, right through carry byte or word? by 1 or CL.

4.Branching instructions:Branching instructions refer to the act of switching

execution to a different instruction sequence as a result of executing a branch
instruction.

OPCODE OPERAND EXPLANATION EXAMPLE

JC address Jumps to the address if carry flag is 1 JC 2050

JNC address Jumps to the address if carry flag is 0 JNC 2050

JZ address Jumps to the address if zero flag is 1 JZ 2050

JNZ address Jumps to the address if zero flag is 0 JNZ 2050

 OPCODE OPERAND EXPLANATION EXAMPLE

JPE address Jumps to the address if parity flag is 1 JPE 2050

JPO address Jumps to the address if parity flag is 0 JPO 2050

JM address Jumps to the address if sign flag is 1 JM 2050

JP address Jumps to the address if sign flag 0 JP 2050

5. Control transfer instructions – conditional, unconditional, call subroutine and

return from subroutine.
 JMP:Unconditional jump .it includes loop transfer and subroutine and interrupt
instructions.
 JNZ:jump till the counter value decreases to zero.It runs the loop till the value
stored in CX becomes zero.
*****

7.8085 microprocessor:
Bus is a group of conducting wires which carries information, all the
peripherals are connected to microprocessor through Bus.
Diagram to represent bus organization system of 8085 Microprocessor.

There are three types of buses.

1. Address bus: It is a group of conducting wires which carries address
only.Address bus is unidirectional because data flow in one direction, from
microprocessor to memory or from microprocessor to Input/output devices (That
is, Out of Microprocessor).
Length of Address Bus of 8085 microprocessor is 16 Bit (That is, Four
Hexadecimal Digits), ranging from 0000 H to FFFF H, (H denotes Hexadecimal).
The microprocessor 8085 can transfer maximum 16 bit address which means it
can address 65, 536 different memory location.
The Length of the address bus determines the amount of memory a
system can address.Such as a system with a 32-bit address bus can address 2^32
memory locations.If each memory location holds one byte, the addressable
memory space is 4 GB.However, the actual amount of memory that can be
accessed is usually much less than this theoretical limit due to chipset and
motherboard limitations.
2. Data bus: It is a group of conducting wires which carries Data only.Data bus is
bidirectional because data flow in both directions, from microprocessor to
memory or Input/Output devices and from memory or Input/Output devices to
microprocessor.
Length of Data Bus of 8085 microprocessor is 8 Bit (That is, two
Hexadecimal Digits), ranging from 00 H to FF H. (H denotes Hexadecimal).
When it is write operation, the processor will put the data (to be written) on
the data bus, when it is read operation, the memory controller will get the data
from specific memory block and put it into the data bus.
The width of the data bus is directly related to the largest number that the bus
can carry, such as an 8 bit bus can represent 2 to the power of 8 unique values,
this equates to the number 0 to 255.A 16 bit bus can carry 0 to 65535.
3. Control bus: It is a group of conducting wires, which is used to generate timing
and control signals to control all the associated peripherals, microprocessor uses
control bus to process data, which is what to do with selected memory location.

Some control signals are:

 Memory read
 Memory write
 I/O read
 I/O Write
 Epode fetch
If one line of control bus may be the read/write line.If the wire is low (no
electricity flowing) then the memory is read, if the wire is high (electricity is
flowing) then the memory is written.
8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit
microprocessor designed by Intel in 1977 using NMOS technology.
It has the following configuration:

 8-bit data bus

 16-bit address bus, which can address unto 64KB
 A 16-bit program counter
 A 16-bit stack pointer
 Six 8-bit registers arranged in pairs: BC, DE, HL
 Requires +5V supply to operate at 3.2 MHZ single phase clock
It is used in washing machines, microwave ovens, mobile phones, etc.

8085 Microprocessor -Functional Units

8085 consists of the following functional units:

Accumulator: It is an 8-bit register used to perform arithmetic, logical, I/O &
LOAD/STORE operations. It is connected to internal data bus & ALU.

Arithmetic and logic unit: As the name suggests, it performs arithmetic and logical
operations like Addition, Subtraction, AND, OR, etc. on 8-bit data.

General purpose register: There are 6 general purpose registers in 8085 processor,
i.e. B, C, D, E, H & L. Each register can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing
combination is like B-C, D-E & H-L.
Program counter: It is a 16-bit register used to store the memory address location of
the next instruction to be executed. Microprocessor increments the program whenever
an instruction is being executed, so that the program counter points to the memory
address of the next instruction that is going to be executed.

Stack pointer: It is also a 16-bit register works like stack, which is always
incremented/decremented by 2 during push & pop operations.

Temporary register: It is an 8-bit register, which holds the temporary data of

arithmetic and logical operations.

Flag register: It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or
1 depending upon the result stored in the accumulator.
These are the set of 5 flip-flops:
  Sign (S)
 Zero (Z)
 Auxiliary Carry (AC)
 Parity (P)
 Carry (C)
Instruction register and decoder: It is an 8-bit register. When an instruction is
fetched from memory then it is stored in the Instruction register. Instruction decoder
decodes the information present in the Instruction register.

Timing and control unit: It provides timing and control signal to the microprocessor
to perform operations. Following are the timing and control signals, which control
external and internal circuits.

 Control Signals: READY, RD’, WR’, ALE

 Status Signals: S0, S1, IO/M’
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT
Interrupt control: As the name suggests it controls the interrupts during a process.
When a microprocessor is executing a main program and whenever an interrupt
occurs, the microprocessor shifts the control from the main program to process the
incoming request. After the request is completed, the control goes back to the main
program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5,
RST 5.5, TRAP.
Serial Input/output control: It controls the serial data communication by using these
two instructions: SID (Serial input data) and SOD (Serial output data).

Address buffer and address-data buffer: The content stored in the stack pointer and
program counter is loaded into the address buffer and address-data buffer to
communicate with the CPU. The memory and I/O chips are connected to these buses;
the CPU can exchange the desired data with the memory and I/O chips.

Address bus and data bus: Data bus carries the data to be stored. It is bidirectional,
whereas address bus carries the location to where it should be stored and it is
unidirectional. It is used to transfer the data & Address I/O devices.

8085 Architecture
We have tried to depict the architecture of 8085 with this following image:

*****
 UNIT-III
Basic Computer organization and Design
1.Instruction codes:
While a Program, as we all know, is, A set of instructions that specify the
operations, operands, and the sequence by which processing has to occur.
An instruction code is a group of bits that tells the computer to perform a specific
operation part.

Instruction Code: Operation Code

The operation code of an instruction is a group of bits that define operations such
as add, subtract, multiply, shift and compliment. The number of bits required for the
operation code depends upon the total number of operations available on the
computer. The operation code must consist of at least n bits for a
given 2^n operations. The operation part of an instruction code specifies the operation
to be performed.

Instruction Code: Register Part

The operation must be performed on the data stored in registers. An instruction

code therefore specifies not only operations to be performed but also the registers
where the operands(data) will be found as well as the registers where the result has to
be stored.

Stored Program Organisation: The simplest way to organize a computer is to

have Processor Register and instruction code with two parts. The first part specifies
the operation to be performed and second specifies an address. The memory address
tells where the operand in memory will be found.

Instructions are stored in one section of memory and data in another.

 A computer with a single processor register is known as Accumulator (AC).
The operation is performed with the memory operand and the content of AC.

Common Bus System: The basic computer has 8 registers, a memory unit and a
control unit. Paths must be provided to transfer data from one register to another. An
efficient method for transferring data in a system is to use a Common Bus System.
The output of registers and memory are connected to the common bus.

Load(LD): The lines from the common bus are connected to the inputs of each
register and data inputs of memory. The particular register whose LD input is enabled
receives the data from the bus during the next clock pulse transition.

Before studying about instruction formats lets first study about the operand
address parts.

When the 2nd part of an instruction code specifies the operand, the instruction is said
to have immediate operand. And when the 2nd part of the instruction code specifies
the address of an operand, the instruction is said to have a direct address. And
in indirect address, the 2nd part of instruction code, specifies the address of a
memory word in which the address of the operand is found.

Computer Instructions: The basic computer has three instruction code formats.
The Operation code (opcode) part of the instruction contains 3 bits and remaining 13
bits depends upon the operation code encountered.

There are three types of formats:

1. Memory Reference Instruction: It uses 12 bits to specify the address and 1 bit to
specify the addressing mode (I). I is equal to 0 for direct address and 1 for indirect
address.
2. Register Reference Instruction: These instructions are recognized by the
oppose 111 with a 0 in the left most bit of instruction. The other 12 bits specify the
operation to be executed.
3. Input-Output Instruction: These instructions are recognized by the operation
code 111 with a 1 in the left most bit of instruction. The remaining 12 bits are used to
specify the input-output operation.

Format of Instruction:

The format of an instruction is depicted in a rectangular box symbolizing the

bits of an instruction. Basic fields of an instruction format are given below:
 1. An operation code field that specifies the operation to be performed.
2. An address field that designates the memory address or register.
3. A mode field that specifies the way the operand of effective address is
determined.
Computers may have instructions of different lengths containing varying number of
addresses. The number of address field in the instruction format depends upon the
internal organization of its registers.

*****

2.Computer Register:
Registers are a type of computer memory used to quickly accept, store, and
transfer data and instructions that are being used immediately by the CPU. The
registers used by the CPU are often termed as Processor registers.

A processor register may hold an instruction, a storage address, or any data

(such as bit sequence or individual characters).

The computer needs processor registers for manipulating data and a register for
holding a memory address. The register holding the memory location is used to
calculate the address of the next instruction after the execution of the current
instruction is completed.

Within the processor , there is a set of Registers which are very fast but hold only
small amount of data, in order to speed up its operation by providing quick access to
commonly used values.Because they are semiconductor devices whose contents can be
accessed at extremely high speed.And the most important thing about Registers is that
Registers generally hold data temporarily, during execution of a program.And
Registers are normally measured by the number of bits they can hold.

As an example: An 8-bit register means, it can store 8 bit of data, 32-bit register means
it can store 32 bit of data.

Now, generally, Registers in the processor perform following two roles:

1.Enable the machine or assembly language programmer to minimise main

memory reference by optimizing use of Registers.
2.Used by control unit to control the operation of the processor or by operating
system programs to control the execution of programs.
Now, we will discuss about various type of registers that are commonly used in
processors.
These are:
1.Accumulator Register(AC): Accumulator Register is a general purpose
Register.This Register is required for doing operation on data.As this register holds
the initial data to be operated on, the intermediate result and the final result of
processing operation.Means, the result of arithmetic operation are transfer to AC if no
specific address of result operation is specified.
And the number of bits that accumulator register contain is equal to
the number of bits per word.That is, if word is of n bits, the AC is also of n bits.

2.Program Counter(PC): Program Counter(PC) holds the address of next instruction

to be read from memory after the current instruction is executed.Means, Program
Counter generally acts as a pointer which points to the memory location where the
next instruction is stored.
And the no. of bits in PC, that is, the size of PC is equal to the width of the
memory address.

3.Temporary Register(TR): Temporary Register(TR) is used for holding data during

the processing.And since Temporary Register hold data, so, the no. of bits it contain is
equal to no. of bits of word(data word).
4.Instruction Register(IR): Instruction Register(IR) is used for storing the
instruction.Means the instruction register hold the current instruction that is being
executed.And since it contain instruction, so, the no. of bits(size) of Instruction
Register is equal to the no. of bits of instruction, and the size of instruction is n bit for
n-bit CPU.
5.Data Register(DR): The Data Register hold the operand from memory.Means when
an operand is found, using either direct or indirect addressing, it is placed in Data
Register(DR).The processor then used in this value as data for its operation. Its size is
equal to the size of word in memory.
6.Address Register(AR): The Address Register hold the address of memory word
that is the Address Register contain the address of memory location or Register from
where data is stored or retrieved.Since it contain address, so the size of Address
Register is equal to the width of memory address is directly related to size of memory,
Means, if a memory is of size 2n *m , then, n bits are used to specify address.

7.Input Register(INPR): Input Register(INPR) hold(or receives) data from an input

device.And the size of input register is depend on the alphanumeric code that followed
in computer, that is, if ASCII is followed, then the size of INPR is 7 bits and if
EBCDIC is followed, then the size of INPR is 8 bits.

8.Output Register(OUTR): Output Register(OUTR) hold data that need to be sent to

an output device. Its size is also depend on the alphanumeric code that followed in
computer.
Now, thus, according to Basic computer, whose CPU is of 16 bit and memory
is of 212*16=4096 words, of 16 bits each, and according to definition of each type of
register we discussed, the no. of bits allocated to each register is depicted in Figure
below.Here we assume that EBCDIC code is followed in computer.

*****

3.Computer Instructions:

Computer instructions are a set of machine language instructions that a particular

processor understands and executes. A computer performs tasks on the basis of the
instruction provided.

An instruction comprises of groups called fields. These fields include:

 o The Operation code (Opcode) field which specifies the operation to be
performed.
o The Address field which contains the location of the operand, i.e., register or
memory location.
o The Mode field which specifies how the operand will be located.

A basic computer has three instruction code formats which are:

1. Memory - reference instruction

2. Register - reference instruction
3. Input-Output instruction

1.Memory - reference instruction: In Memory-reference instruction, 12 bits of

memory is used to specify an address and one bit to specify the addressing mode 'I'.

2.Register - reference instruction: The Register-reference instructions are

represented by the Opcode 111 with a 0 in the leftmost bit (bit 15) of the instruction.

A Register-reference instruction specifies an operation on or a test of the

AC (Accumulator) register.

3.Input-Output instruction: Just like the Register-reference instruction, an Input-

Output instruction does not need a reference to memory and is recognized by the
operation code 111 with a 1 in the leftmost bit of the instruction. The remaining 12
bits are used to specify the type of the input-output operation or test performed.

o The three operation code bits in positions 12 through 14 should be equal to 111.
Otherwise, the instruction is a memory-reference type, and the bit in position 15
is taken as the addressing mode I.
o When the three operation code bits are equal to 111, control unit inspects the bit
in position 15. If the bit is 0, the instruction is a register-reference type.
Otherwise, the instruction is an input-output type having bit 1 at position 15.

Instruction Set Completeness: A set of instructions is said to be complete if the

computer includes a sufficient number of instructions in each of the following
categories:

o Arithmetic, logical and shift instructions

o A set of instructions for moving information to and from memory and processor
registers.
 o Instructions which controls the program together with instructions that check
status conditions.
o Input and Output instructions

Arithmetic, logic and shift instructions provide computational capabilities for

processing the type of data the user may wish to employ.

A huge amount of binary information is stored in the memory unit, but all
computations are done in processor registers. Therefore, one must possess the
capability of moving information between these two units.

Program control instructions such as branch instructions are used change the sequence
in which the program is executed.

Input and Output instructions act as an interface between the computer and the user.
Programs and data must be transferred into memory, and the results of computations
must be transferred back to the user.

*****

4.Timing and control:

The timing for all registers in the basic computer is controlled by a master
clock generator. The clock pulses are applied to all flip-flops and registers in the
system, including the flip-flops and registers in the control unit. The clock pulses do
not change the state of a register unless the register is enabled by a control signal. The
control signals are generated in the control unit and provide control inputs for the
multiplexers in the common bus, control inputs in processor registers, and micro
operations for the accumulator.
There are two major types of control organization:

1. hardwired control and

2. microprogrammed control.

In the hardwired organization, the control logic is implemented with gates, flip-
flops, decoders, and other digital circuits. It has the advantage that it can be optimized
to produce a fast mode of operation. In the microprogrammed organization, the
control information is stored in a control memory. The control memory is
programmed to initiate the required sequence of microoperations. A hardwired
control, as the name implies, requires changes in the wiring among the various
components if the design has to be modified or changed.
In the microprogrammed control, any required changes or modifications can be
done by updating the microprogram in control memory.
The block diagram of the control unit is shown in Fig.
It consists of two decoders,

1. a sequence counter, and

2. a number of control logic gates.

The instruction register is shown again in Fig. where it is divided into three parts:

1. the 1 bit,
2. the operation code, and
3. bits 0 through 11.
An instruction read from memory is placed in the instruction register (IR).position of
this register in the common bus system is indicated in Fig.

*****
5.Instruction Cycle:
An instruction cycle, also known as fetch-decode-execute cycle is the basic
operational process of a computer. This process is repeated continuously by CPU from
boot up to shut down of computer.

Following are the steps that occur during an instruction cycle:

1. Fetch the Instruction: The instruction is fetched from memory address that is
stored in PC(Program Counter) and stored in the instruction register IR. At the end of
the fetch operation, PC is incremented by 1 and it then points to the next instruction to
be executed.

2. Decode the Instruction: The instruction in the IR is executed by the decoder.

3. Read the Effective Address: If the instruction has an indirect address, the effective
address is read from the memory. Otherwise operands are directly read in case of
immediate operand instruction.

4. Execute the Instruction: The Control Unit passes the information in the form of
control signals to the functional unit of CPU. The result generated is stored in main
memory or sent to an output device.

The cycle is then repeated by fetching the next instruction. Thus in this
way the instruction cycle is repeated continuously.
 *****

6.Input-Output:

In computer architecture, input-output devices act as an interface between the

machine and the user.

Instructions and data stored in the memory must come from some input device. The
results are displayed to the user through some output device.

The following block diagram shows the input-output configuration for a basic
computer.
 o The input-output terminals send and receive information.
o The amount of information transferred will always have eight bits of an
alphanumeric code.
o The information generated through the keyboard is shifted into an input
register 'INPR'.
o The information for the printer is stored in the output register 'OUTR'.
o Registers INPR and OUTR communicate with a communication interface
serially and with the AC in parallel.
o The transmitter interface receives information from the keyboard and
transmits it to INPR.
o The receiver interface receives information from OUTR and sends it to the
printer serially.

*****

7.Interrupt:
Interrupt is a signal emitted by hardware or software when a process or an
event needs immediate attention. It alerts the processor to a high-priority process
requiring interruption of the current working process. In I/O devices one of the bus
control lines is dedicated for this purpose and is called the Interrupt Service Routine
(ISR).
While the processor is handling the interrupts, it must inform the device
that its request has been recognized so that it stops sending the interrupt request
signal. Also, saving the registers so that the interrupted process can be restored in the
future, increases the delay between the time an interrupt is received and the start of
the execution of the ISR. This is called Interrupt Latency.
Hardware Interrupts:
In a hardware interrupt, all the devices are connected to the Interrupt Request Line.
A single request line is used for all the n devices. To request an interrupt, a device
closes its associated switch. When a device requests an interrupt, the value of INTR
is the logical OR of the requests from individual devices.

Handling Multiple Devices: When more than one device raises an interrupt request
signal, then additional information is needed to decide which device to be considered
first. The following methods are used to decide which device to
select:Polling,Vectored Interrupts, and Interrupt Nesting. These are explained as
followingbelow.
1. Polling: In polling, the first device encountered with the IRQ bit set is the device
that is to be serviced first. Appropriate ISR is called to service the same. It is easy
to implement but a lot of time is wasted by interrogating the IRQ bit of all
devices.

2. Vectored Interrupts: In vectored interrupts, a device requesting an interrupt

identifies itself directly by sending a special code to the processor over the bus.
This enables the processor to identify the device that generated the interrupt. The
special code can be the starting address of the ISR or where the ISR is located in
memory and is called the interrupt vector.

3. Interrupt Nesting: In this method, the I/O device is organized in a priority

structure. Therefore, an interrupt request from a higher priority device is
recognized whereas a request from a lower priority device is not. To implement
this each process/device (even the processor). The processor accepts interrupts
only from devices/processes having priority more than it.
*****

CENTRAL PROCESSING UNIT

1.Introduction:
Central Processing Unit (CPU) consists of the following features:

 CPU is considered as the brain of the computer.

 CPU performs all types of data processing operations.
 It stores data, intermediate results, and instructions (program).
 It controls the operation of all parts of the computer.

CPU itself has following three components.

 Memory or Storage Unit

 Control Unit
  ALU(Arithmetic Logic Unit)

(i).Memory or Storage Unit: This unit can store instructions, data, and intermediate
results. This unit supplies information to other units of the computer when needed. It
is also known as internal storage unit or the main memory or the primary storage or
Random Access Memory (RAM).

Its size affects speed, power, and capability. Primary memory and secondary memory
are two types of memories in the computer. Functions of the memory unit are :
 It stores all the data and the instructions required for processing.
 It stores intermediate results of processing.
 It stores the final results of processing before these results are released to an
output device.
 All inputs and outputs are transmitted through the main memory.

(ii).Control Unit: This unit controls the operations of all parts of the computer but
does not carry out any actual data processing operations.

Functions of this unit are:

 It is responsible for controlling the transfer of data and instructions among other
units of a computer.
 It manages and coordinates all the units of the computer.
 It obtains the instructions from the memory, interprets them, and directs the
operation of the computer.
 It communicates with Input/Output devices for transfer of data or results from
storage.
  It does not process or store data.

(iii).ALU (Arithmetic Logic Unit): This unit consists of two subsections namely,

 Arithmetic Section
 Logic Section
Arithmetic Section: Function of arithmetic section is to perform arithmetic operations
like addition, subtraction, multiplication, and division. All complex operations are
done by making repetitive use of the above operations.

Logic Section: Function of logic section is to perform logic operations such as

comparing, selecting, matching, and merging of data.
*****
2.General Register organization:
When we are using multiple general-purpose registers, instead of a
single accumulator register, in the CPU Organization then this type of organization is
known as General register-based CPU Organization. In this type of organization, the
computer uses two or three address fields in their instruction format. Each address
field may specify a general register or a memory word. If many CPU registers are
available for heavily used variables and intermediate results, we can avoid memory
references much of the time, thus vastly increasing program execution speed, and
reducing program size.

For example:
MULT R1, R2, R3
This is an instruction of an arithmetic multiplication written in assembly language. It
uses three address fields R1, R2, and R3. The meaning of this instruction is:
R1 <-- R2 * R3
This instruction also can be written using only two address fields as:
MULT R1, R2
In this instruction, the destination register is the same as one of the source registers.
This means the operation.
R1 <-- R1 * R2
The use of large number of registers results in short program with limited
instructions.
The advantages of General register based CPU organization :
 Efficiency of CPU increases as there are a large number of registers are used in
this organization.
 Less memory space is used to store the program since the instructions are written
in compact way.

The disadvantages of General register based CPU organization :

 Care should be taken to avoid unnecessary usage of registers. Thus, compilers
need to be more intelligent in this aspect.
 Since large number of registers are used, thus extra cost is required in this
organization.

General register CPU organisation of two type:

1. Register-memory reference architecture (CPU with less register):

In this organisation Source 1 is always required in register, source 2 can

be present either in register or in memory.Here two address instruction formats is the
compatible instruction format.
2. Register-register reference architecture (CPU with more register):

In this organisation ALU operations are performed only on a register

data. So operands are required in the register. After manipulation result is also placed
in register.Here three address instruction formats is the compatible instruction
format.
*****
3.Stack Organization:
The computers which use Stack-based CPU Organization are based on a
data structure called stack. The stack is a list of data words. It uses Last In First
Out (LIFO) access method which is the most popular access method in most of the
CPU. A register is used to store the address of the topmost element of the stack
which is known as Stack pointer (SP). In this organisation, ALU operations are
performed on stack data. It means both the operands are always required on the
stack. After manipulation, the result is placed in the stack.
The main two operations that are performed on the operators of the stack
are Push and Pop. These two operations are performed from one end only.
(i).Push: This operation results in inserting one operand at the top of the stack and it
decrease the stack pointer register. The format of the PUSH instruction is:
PUSH
It inserts the data word at specified address to the top of the stack. It can be
implemented as:
//decrement SP by 1
SP <-- SP - 1
//store the content of specified memory address
//into SP; i.e, at top of stack
SP <-- (memory address)
(ii).Pop: This operation results in deleting one operand from the top of the stack and
it increase the stack pointer register. The format of the POP instruction is:
POP
It deletes the data word at the top of the stack to the specified address. It can be
implemented as:
//transfer the content of SP (i.e, at top most data)
//into specified memory location
(memory address) <-- SP
//increment SP by 1
SP <-- SP + 1
Operation type instruction does not need the address field in this CPU
organization. This is because the operation is performed on the two operands that
are on the top of the stack. For example:
SUB
 This instruction contains the opcode only with no address field. It pops the two
top data from the stack, subtracting the data, and pushing the result into the stack
at the top.
The advantages of Stack based CPU organization:
 Efficient computation of complex arithmetic expressions.
 Execution of instructions is fast because operand data are stored in consecutive
memory locations.
 Length of instruction is short as they do not have address field.
The disadvantages of Stack based CPU organization:
 The size of the program increases.
*****

4.Instruction Formats:
Computer perform task on the basis of instruction provided. An instruction
in computer comprises of groups called fields. These fields contains different
information as for computers every thing is in 0 and 1 so each field has different
significance on the basis of which a CPU decide what to perform. The most common
fields are:
 Operation field which specifies the operation to be performed like addition.
 Address field which contain the location of operand, i.e., register or memory
location.
 Mode field which specifies how operand is to be founded.
An instruction is of various length depending upon the number of
addresses it contain. Generally CPU organizations are of three types on the basis of
number of address fields:
1. Single Accumulator organization
2. General register organization
3. Stack organization
In first organization operation is done involving a special register
called accumulator. In second on multiple registers are used for the computation
purpose. In third organization the work on stack basis operation due to which it does
not contain any address field. It is not necessary that only a single organization is
applied a blend of various organization is mostly what we see generally.
(i).Zero Address Instructions: A stack based computer do not use address field in
instruction.To evaluate a expression first it is converted to revere Polish Notation i.e.
Post fix Notation.
 Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
(ii).One Address Instructions: This use a implied ACCUMULATOR register for
data manipulation.One operand is in accumulator and other is in register or memory
location.Implied means that the CPU already know that one operand is in
accumulator so there is no need to specify it.

(iii).Two Address Instructions: This is common in commercial computers.Here two

address can be specified in the instruction.Unlike earlier in one address instruction
the result was stored in accumulator here result can be stored at different location
rather than just accumulator, but require more number of bit to represent address.

(iv).Three Address Instructions:This has three address field to specify a register or

a memory location. Program created are much short in size but number of bits per
instruction increase. These instructions make creation of program much easier but it
does not mean that program will run much faster because now instruction only
contain more information but each micro operation (changing content of register,
loading address in address bus etc.) will be performed in one cycle only.

*****
5.Adressing Modes:
The operation field of an instruction specifies the operation to be
performed. This operation will be executed on some data which is stored in computer
registers or the main memory. The way any operand is selected during the program
execution is dependent on the addressing mode of the instruction. The purpose of
using addressing modes is as follows:

1. To give the programming versatility to the user.

2. To reduce the number of bits in addressing field of instruction.

Types of Addressing Modes:

Below we have discussed different types of addressing modes one by one:

1.Immediate Mode: In this mode, the operand is specified in the instruction itself. An
immediate mode instruction has an operand field rather than the address field.

For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand
here.

2.Register Mode: In this mode the operand is stored in the register and this register is
present in CPU. The instruction has the address of the Register where the operand is
stored.

3.Register Indirect Mode: In this mode, the instruction specifies the register whose
contents give us the address of operand which is in memory. Thus, the register
contains the address of operand rather than the operand itself.
4.Auto Increment/Decrement Mode: In this the register is incremented or
decremented after or before its value is used.

5.Direct Addressing Mode: In this mode, effective address of operand is present in

instruction itself.

 Single memory reference to access data.

 No additional calculations to find the effective address of the operand.

6.Indirect Addressing Mode: In this, the address field of instruction gives the
address where the effective address is stored in memory. This slows down the
execution, as this includes multiple memory lookups to find the operand.
7.Displacement Addressing Mode: In this the contents of the indexed register is
added to the Address part of the instruction, to obtain the effective address of operand.

EA = A + (R), In this the address field holds two values, A(which is the base
value) and R(that holds the displacement), or vice versa.

8.Relative Addressing Mode: It is a version of Displacement addressing mode.

In this the contents of PC(Program Counter) is added to address part of instruction to

obtain the effective address.

EA = A + (PC), where EA is effective address and PC is program counter.

The operand is A cells away from the current cell(the one pointed to by PC)

9.Base Register Addressing Mode: It is again a version of Displacement addressing

mode.

This can be defined as EA = A + (R), where A is displacement and R

holds pointer to base address.

10.Stack Addressing Mode: In this mode, operand is at the top of the stack. For
example: ADD, this instruction will POP top two items from the stack, add them, and
will then PUSH the result to the top of the stack.

*****
 UNIT-IV
INPUT_OUTPUT ORGANIZATION
1.Peripheral devices:

A Peripheral Device is defined as the device which provides

input/output functions for a computer and serves as an auxiliary computer device
without computing-intensive functionality.

Generally peripheral devices, however, are not essential for the

computer to perform its basic tasks, they can be thought of as an enhancement to the
user’s experience. A peripheral device is a device that is connected to a computer
system but is not part of the core computer system architecture. Generally, more
people use the term peripheral more loosely to refer to a device external to the
computer case.
Classification of Peripheral devices:

It is generally classified into 3 basic categories which are given below:

1. Input Devices:The input devices is defined as it converts incoming data and
instructions into a pattern of electrical signals in binary code that are
comprehensible to a digital computer.
Example:
Keyboard, mouse, scanner, microphone etc.
2. OutputDevices:An output device is generally reverse of the input process and
generally translating the digitized signals into a form intelligible to the user. The
output device is also performed for sending data from one computer system to
another.
Example:
Monitors, headphones, printers etc.,
3. StorageDevices:Storage devices are used to store data in the system which is
required for performing any operation in the system. The storage devices is one of
the most requirement devices and also provide better compatibility.
Example:
Hard disk, magnetic tape, Flash memory etc.
Advantage of Peripherals Devices:

Peripherals devices provides more feature due to this operation of the

system is easy. These are given below:
 It is helpful for taking input very easily.
  It is also provided a specific output.
 It has a storage device for storing information or data
 It also improves the efficiency of the system.

*****

2.INPUT-OUTPUT INTERFACE:
The method that is used to transfer information between internal storage and
external I/O devices is known as I/O interface. The CPU is interfaced using special
communication links by the peripherals connected to any computer system. These
communication links are used to resolve the differences between CPU and
peripheral. There exists special hardware components between CPU and peripherals
to supervise and synchronize all the input and output transfers that are called
interface units.
Mode of Transfer:

The binary information that is received from an external device is usually

stored in the memory unit. The information that is transferred from the CPU to the
external device is originated from the memory unit. CPU merely processes the
information but the source and target is always the memory unit. Data transfer
between CPU and the I/O devices may be done in different modes.
Data transfer to and from the peripherals may be done in any of the three possible
ways
1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA).
Now let’s discuss each mode one by one.
1. Programmed I/O:
It is due to the result of the I/O instructions that are written in the
computer program. Each data item transfer is initiated by an instruction in the
program. Usually the transfer is from a CPU register and memory. In this case it
requires constant monitoring by the CPU of the peripheral devices.

2. Interrupt- initiated I/O:

This mode uses an interrupt facility and special commands to inform the interface
to issue the interrupt command when data becomes available and interface is
ready for the data transfer. In the meantime CPU keeps on executing other tasks
and need not check for the flag. When the flag is set, the interface is informed and
an interrupt is initiated. This interrupt causes the CPU to deviate from what it is
 doing to respond to the I/O transfer. The CPU responds to the signal by storing
the return address from the program counter (PC) into the memory stack and then
branches to service that processes the I/O request. After the transfer is complete,
CPU returns to the previous task it was executing. The branch address of the
service can be chosen in two ways known as vectored and non-vectored interrupt.
In vectored interrupt, the source that interrupts, supplies the branch information to
the CPU while in case of non-vectored interrupt the branch address is assigned to
a fixed location in memory.

Both the methods programmed I/O and Interrupt-driven I/O require the
active intervention of the processor to transfer data between memory and the I/O
module, and any data transfer must transverse
a path through the processor. Thus both these forms of I/O suffer from two inherent
drawbacks.

 The I/O transfer rate is limited by the speed with which the processor
can test and service a
device.
 The processor is tied up in managing an I/O transfer; a number of
instructions must be executed
for each I/O transfer.

3. Direct Memory Access:

The data transfer between a fast storage media such as magnetic disk
and memory unit is limited by the speed of the CPU. Thus we can allow the
peripherals directly communicate with each other using the memory buses,
removing the intervention of the CPU. This type of data transfer technique is
known as DMA or direct memory access. During DMA the CPU is idle and it has
no control over the memory buses. The DMA controller takes over the buses to
manage the transfer directly between the I/O devices and the memory unit.
 Bus Request: It is used by the DMA controller to request the CPU to relinquish
the control of the buses.
Bus Grant: It is activated by the CPU to Inform the external DMA controller that
the buses are in high impedance state and the requesting DMA can take control of
the buses. Once the DMA has taken the control of the buses it transfers the data.
This transfer can take place in many ways.

Types of DMA transfer using DMA controller:

Burst Transfer:DMA returns the bus after complete data transfer. A register is
used as a byte count,being decremented for each byte transfer, and upon the byte
count reaching zero, the DMAC will release the bus. When the DMAC operates
in burst mode, the CPU is halted for the duration of the data
transfer.
Cyclic Stealing:An alternative method in which DMA controller transfers one
word at a time after which it must return the control of the buses to the CPU. The
CPU delays its operation only for one memory cycle to allow the direct memory
I/O transfer to “steal” one memory cycle.

In cycle stealing mode we always follow pipelining concept that when

one byte is getting transferred then Device is parallel preparing the next byte. “The
fraction of CPU time to the data transfer time” if asked then cycle stealing mode is
used.
*****

3.ASYNCHRONOUS DATA TRANSFER:

Asynchronous input output is a form of input output processing that allows
others devices to do processing before the transmission or data transfer is done.
Problem faced in asynchronous input output synchronization :
It is not sure that the data on the data bus is fresh or not as their no time slot for
sending or receiving data.
This problem is solved by following mechanism:
1. Strobe
2. Handshaking
Data is transferred from source to destination through data bus in between.
1.Strobe Mechanism:
1.Source initiated Strobe : When source initiates the process of data transfer.
Strobe is just a signal.

(i) First, source puts data on the data bus and ON the strobe signal.
(ii) Destination on seeing the ON signal of strobe, read data from the data bus.
(iii) After reading data from the data bus by destination, strobe gets OFF.
Signals can be seen as:

It shows that first data is put on the data bus and then strobe signal gets active.

2.Destination initiated signal :When destination initiates the process of data

transfer.

(i) First, the destination ON the strobe signal to ensure the source to put the fresh
data on the data bus.
(ii) Source on seeing the ON signal puts fresh data on the data bus.
(iii) Destination reads the data from the data bus and strobe gets OFF signal.
Signals can be seen as:

1. It shows that first strobe signal gets active then data is put on the data bus.
Problems faced in Strobe based asynchronous input output:

1. In Source initiated Strobe, it is assumed that destination has read the data from the
data bus but their is no surety.
2. In Destination initiated Strobe, it is assumed that source has put the data on the
data bus but their is no surety.

This problem is overcome by Handshaking.

3.Handshaking Mechanism:

1.Source initiated Handshaking : When source initiates the data transfer

process.
It consists of signals:
DATA VALID: if ON tells data on the data bus is valid otherwise invalid.
DATA ACCEPTED: if ON tells data is accepted otherwise not accepted.

(i) Source places data on the data bus and enable Data valid signal.
(ii) Destination accepts data from the data bus and enable Data accepted signal.
(iii) After this, disable Data valid signal means data on data bus is invalid now.
(iv) Disable Data accepted signal and the process ends.
Now there is surety that destination has read the data from the data bus
through data accepted signal.
Signals can be seen as:
It shows that first data is put on the data bus then data valid signal gets active and
then data accepted signal gets active. After accepting the data, first data valid
signal gets off then data accepted signal gets off.
2.Destination initiated Handshaking : When destination initiates the process
of data transfer.

REQUEST FOR DATA: if ON requests for putting data on the data bus.
DATA VALID: if ON tells data is valid on the data bus otherwise invalid data.

(i) When destination is ready to receive data, Request for Data signal gets
activated.
(ii) source in response puts data on the data bus and enabled Data valid signal.
(iii) Destination then accepts data from the data bus and after accepting data,
disabled Request for Data signal.
(iv) At last, Data valid signal gets disabled means data on the data bus is no more
valid data.
Now there is surety that source has put the data on the data bus through data valid
signal.
Signals can be seen as:

It shows that first Request for Data signal gets active then data is put on data bus
then Data valid signal gets active. After reading data, first Request for Data signal
gets off then Data valid signal.

*****
4.MODE OF TRANSFER:
The mode of transferring information between internal storage and external I/O
devices is known as I/O interface or input/output interface. The I/O module diagram is
as follows:

I/O Module Decisions:

 Hide or reveal device properties to CPU

 Support multiple or single devices
 Control device functions or leave for CPU
 Also, O/S decisions – e.g. Unix treats everything it can as a file

Mode of Transfer:

Data transfer between the central computer to I/O devices may be handled in variety
of modes.

 Programmed I/O
 Interrupt Initiated I/O
 Direct Memory Access (DMA)
Let us discuss each in detail:
Programmed I/O:

 CPU requests I/O operation

 I/O module performs operations.
 I/O module sets status bits
 CPU checks status bits periodically
 I/O module does not inform CPU directly
  I/O module does not interrupt CPU
 CPU may wait or come back later
 Under programmed I/O data transfer is very like memory access (CPU
viewpoint)
 Each device is given an unique identifier
 CPU commands contain identifier (address)

Interrupt Driven I/O Basic Operation:

 CPU issues read command

 I/O module gets data from peripheral whilst CPU does other work
 I/O module interrupts CPU
 CPU requests data
 I/O module transfers data

Direct Memory Access (DMA):

 Interrupt driven and programmed I/O require active CPU intervention

 Transfer rate is limited (processor to test and service the device)
 CPU is tied up for managing I/O transfer.
 Additional Module (hardware) on bus
 DMA controller takes over from CPU for I/ODMA is the answer.
  DMA module must use the bus only when the processor does not need it,
 It must force the processor to suspend operation temporarily. This technique is
called cycle stealing

DMA Operation:

 CPU tells DMA controller:-

–Read/Write
–Device address
–Starting address of memory block for data
–Amount of data to be transferred

 CPU carries on with other work

 DMA controller deals with transfer
 DMA controller sends interrupt when finished
Cyclic Stealing :
In this DMA controller transfers one word at a time after which it must return
the control of the buses to the CPU. The CPU merely delays its operation for one
memory cycle to allow the direct memory I/O transfer to “steal” one memory cycle.
*****

5.PRIORITY INTERRUPT:
A priority interrupt is a system which decides the priority at which various
devices, which generates the interrupt signal at the same time, will be serviced by the
CPU. The system has authority to decide which conditions are allowed to interrupt the
CPU, while some other interrupt is being serviced. Generally, devices with high speed
transfer such as magnetic disks are given high priority and slow devices such
as keyboards are given low priority.
When two or more devices interrupt the computer simultaneously, the computer
services the device with the higher priority first.

Types of Interrupts:
Following are some different types of interrupts:

Hardware Interrupts:When the signal for the processor is from an external

device or hardware then this interrupts is known as “hardware interrupt”.
Let us consider an example: when we press any key on our keyboard to
do some action, then this pressing of the key will generate an interrupt signal for the
processor to perform certain action. Such an interrupt can be of two types:

 Maskable Interrupt: The hardware interrupts which can be delayed when a

much high priority interrupt has occurred at the same time.
 Non Maskable Interrupt: The hardware interrupts which cannot be delayed
and should be processed by the processor immediately.

Software Interrupts:The interrupt that is caused by any internal system of the

computer system is known as a software interrupt. It can also be of two types:

 Normal Interrupt: The interrupts that are caused by software instructions are
called normal software interrupts.
  Exception: Unplanned interrupts which are produced during the execution of
some program are called exceptions, such as division by zero.

Daisy Chaining Priority:

In daisy chaining system all the devices are connected in a serial form. The
interrupt line request is common to all devices. If any device has interrupt signal in
low level state then interrupt line goes to low level state and enables the interrupt input
in the CPU. When there is no interrupt the interrupt line stays in high level state. The
CPU respond to the interrupt by enabling the interrupt acknowledge line. This signal is
received by the device 1 at its PI input. The acknowledge signal passes to next device
through PO output only if device 1 is not requesting an interrupt.
The following figure shows the block diagram for daisy chaining priority system.

*****

6.DIRECT MEMORY ACCESS:

Direct memory access (DMA) is a mode of data
transfer between the memory and I/O devices. This happens without the
involvement of the processor. We have two other methods of data transfer,
programmed I/O and Interrupt driven I/O.

The DMA controllers transfer the data ion three modes.

1. Burst Mode: Here, once the DMA controller gains the charge of the system bus, then
it releases the system bus only after completion of data transfer. Till then the CPU has
to wait for the system buses.
2. Cycle Stealing Mode: In this mode, the DMA controller forces the CPU to stop its
operation and relinquish the control over the bus for a short term to DMA controller.
After the transfer of every byte, the DMA controller releases the bus and then again
 requests for the system bus. In this way, the DMA controller steals the clock cycle for
transferring every byte.
3. Transparent Mode: Here, the DMA controller takes the charge of system bus only if
the processor does not require the system bus.

DMA controller is a hardware unit that allows I/O devices to access memory directly
without the participation of the processor. Here, we will discuss the working of the
DMA controller. Below we have the diagram of DMA controller that explains its
working:

1. Whenever an I/O device wants to transfer the data to or from memory, it sends the
DMA request (DRQ) to the DMA controller. DMA controller accepts this DRQ and
asks the CPU to hold for a few clock cycles by sending it the Hold request (HLD).
2. CPU receives the Hold request (HLD) from DMA controller and relinquishes the bus
and sends the Hold acknowledgement (HLDA) to DMA controller.
3. After receiving the Hold acknowledgement (HLDA), DMA controller acknowledges
I/O device (DACK) that the data transfer can be performed and DMA controller takes
the charge of the system bus and transfers the data to or from memory.
4. When the data transfer is accomplished, the DMA raise an interrupt to let know the
processor that the task of data transfer is finished and the processor can take control
over the bus again and start processing where it has left.

Direct Memory Access Diagram:

After exploring the working of DMA controller, let us discuss the block diagram of
the DMA controller. Below we have a block diagram of DMA controller.
 Whenever a processor is requested to read or write a block of data, i.e. transfer a block
of data, it instructs the DMA controller by sending the following information.

1. The first information is whether the data has to be read from memory or the data has to
be written to the memory. It passes this information via read or write control lines that
is between the processor and DMA controllers control logic unit.
2. The processor also provides the starting address of/ for the data block in the memory,
from where the data block in memory has to be read or where the data block has to be
written in memory. DMA controller stores this in its address register. It is also called
the starting address register.
3. The processor also sends the word count, i.e. how many words are to be read or
written. It stores this information in the data count or the word count register.
4. The most important is the address of I/O device that wants to read or write data. This
information is stored in the data register.

*****

7.INPUT-OUTPUT PROCESSOR:
The Input Output Processor (IOP) is just like a CPU that handles the
details of I/O operations. It is more equipped with facilities than those are available
in typical DMA controller. The IOP can fetch and execute its own instructions that
are specifically designed to characterize I/O transfers. In addition to the I/O – related
tasks, it can perform other processing tasks like arithmetic, logic, branching and code
translation. The main memory unit takes the pivotal role. It communicates with
processor by the means of DMA.
The block diagram:
The Input Output Processor is a specialized processor which loads and stores data
into memory along with the execution of I/O instructions. It acts as an interface
between system and devices. It involves a sequence of events to executing I/O
operations and then store the results into the memory.
Advantages –
 The I/O devices can directly access the main memory without the intervention by
the processor in I/O processor based systems.
 It is used to address the problems that are arises in Direct memory access method.
*****

MEMORY ORGANIZATION
1.MEMORY HIERARCHY:
In the Computer System Design, Memory Hierarchy is an enhancement to
organize the memory such that it can minimize the access time. The Memory
Hierarchy was developed based on a program behaviour known as locality of
references.The figure below clearly demonstrates the different levels of memory
hierarchy : In the Computer System Design, Memory Hierarchy is an enhancement
to organize the memory such that it can minimize the access time. The Memory
Hierarchy was developed based on a program behavior known as locality of
references.The figure below clearly demonstrates the different levels of memory
hierarchy
This Memory Hierarchy Design is divided into 2 main types:
1. External Memory or Secondary Memory :Comprising of Magnetic Disk,
Optical Disk, Magnetic Tape i.e. peripheral storage devices which are accessible
by the processor via I/O Module.
2. Internal Memory or Primary Memory :Comprising of Main Memory, Cache
Memory & CPU registers. This is directly accessible by the processor.
We can infer the following characteristics of Memory Hierarchy Design from above
figure:
1. Capacity: It is the global volume of information the memory can store. As we
move from top to bottom in the Hierarchy, the capacity increases.
2. Access Time: It is the time interval between the read/write request and the
availability of the data. As we move from top to bottom in the Hierarchy, the
access time increases.
3. Performance: Earlier when the computer system was designed without Memory
Hierarchy design, the speed gap increases between the CPU registers and Main
Memory due to large difference in access time. This results in lower performance
of the system and thus, enhancement was required. This enhancement was made
in the form of Memory Hierarchy Design because of which the performance of
the system increases. One of the most significant ways to increase system
performance is minimizing how far down the memory hierarchy one has to go to
manipulate data.
4. Cost per bit: As we move from bottom to top in the Hierarchy, the cost per bit
increases i.e. Internal Memory is costlier than External Memory.

*****
2.Main Memory:
The memory unit that communicates directly within the CPU, Auxillary
memory and Cache memory, is called main memory. It is the central storage unit of
the computer system. It is a large and fast memory used to store data during computer
operations. Main memory is made up of RAM and ROM, with RAM integrated
circuit chips holing the major share.
 RAM(Random Access Memory):

 DRAM: Dynamic RAM, is made of capacitors and transistors, and must be

refreshed every 10~100 ms. It is slower and cheaper than SRAM.
 SRAM: Static RAM, has a six transistor circuit in each cell and retains data,
until powered off.
 NVRAM: Non-Volatile RAM, retains its data, even when turned off.
Example: Flash memory.

ROM(Read Only Memory):

ROM is non-volatile and is more like a permanent storage for information. It

also stores the bootstrap loader program, to load and start the operating system when
computer is turned on. PROM(Programmable ROM), EPROM(Erasable PROM)
and EEPROM(Electrically Erasable PROM) are some commonly used ROMs.

*****
3.Auxiliary Memory:
An Auxiliary memory is known as the lowest-cost, highest-capacity and
slowest-access storage in a computer system. It is where programs and data are kept
for long-term storage or when not in immediate use. The most common examples of
auxiliary memories are magnetic tapes and magnetic disks.

Magnetic Disks

A magnetic disk is a type of memory constructed using a circular plate of metal or

plastic coated with magnetized materials. Usually, both sides of the disks are used to
carry out read/write operations. However, several disks may be stacked on one spindle
with read/write head available on each surface.
The following image shows the structural representation for a magnetic disk.

o The memory bits are stored in the magnetized surface in spots along the
concentric circles called tracks.
o The concentric circles (tracks) are commonly divided into sections called
sectors.

Magnetic Tape: Magnetic tape is a storage medium that allows data archiving,
collection, and backup for different kinds of data. The magnetic tape is constructed
using a plastic strip coated with a magnetic recording medium.

The bits are recorded as magnetic spots on the tape along several
tracks. Usually, seven or nine bits are recorded simultaneously to form a character
together with a parity bit.

Magnetic tape units can be halted, started to move forward or in

reverse, or can be rewound. However, they cannot be started or stopped fast enough
between individual characters. For this reason, information is recorded in blocks
referred to as records

*****
4.Associative Memory:
An associative memory can be considered as a memory unit whose stored
data can be identified for access by the content of the data itself rather than by an
address or memory location.

Associative memory is often referred to as Content

Addressable Memory (CAM).

When a write operation is performed on associative memory,

no address or memory location is given to the word. The memory itself is capable of
finding an empty unused location to store the word.

On the other hand, when the word is to be read from an

associative memory, the content of the word, or part of the word, is specified. The
words which match the specified content are located by the memory and are marked
for reading.

The following diagram shows the block representation of an Associative memory.

From the block diagram, we can say that an associative memory consists of a memory
array and logic for 'm' words with 'n' bits per word.

The functional registers like the argument register A and key register K each
have n bits, one for each bit of a word. The match register M consists of m bits, one
for each memory word.

The words which are kept in the memory are compared in parallel with the content of
the argument register.

The following diagram can represent the relation between the memory array and the
external registers in an associative memory.
The cells present inside the memory array are marked by the letter C with two
subscripts. The first subscript gives the word number and the second specifies the bit
position in the word. For instance, the cell Cij is the cell for bit j in word i.

A bit Aj in the argument register is compared with all the bits in column j of the array
provided that Kj = 1. This process is done for all columns j = 1, 2, 3......, n.

If a match occurs between all the unmasked bits of the argument and the bits in word i,
the corresponding bit Mi in the match register is set to 1. If one or more unmasked bits
of the argument and the word do not match, Mi is cleared to 0.

*****

5.Cache Memory:

Cache Memory is a special very high-speed memory. It is used to speed

up and synchronizing with high-speed CPU. Cache memory is costlier than main
memory or disk memory but economical than CPU registers. Cache memory is an
extremely fast memory type that acts as a buffer between RAM and the CPU. It
holds frequently requested data and instructions so that they are immediately
available to the CPU when needed.

Cache memory is used to reduce the average time to access data from
the Main memory. The cache is a smaller and faster memory which stores copies of
the data from frequently used main memory locations. There are various different
independent caches in a CPU, which store instructions and data.
Levels of memory:

 Level 1 or Register: It is a type of memory in which data is stored and accepted

that are immediately stored in CPU. Most commonly used register is accumulator,
Program counter, address register etc.
 Level 2 or Cache memory : It is the fastest memory which has faster access time
where data is temporarily stored for faster access.
 Level 3 or Main Memory :It is memory on which computer works currently. It is
small in size and once power is off data no longer stays in this memory.
 Level 4 or Secondary Memory: It is external memory which is not as fast as
main memory but data stays permanently in this memory.

Cache Performance:
When the processor needs to read or write a location in main memory,
it first checks for a corresponding entry in the cache.

 If the processor finds that the memory location is in the cache, a cache hit has
occurred and data is read from cache
 If the processor does not find the memory location in the cache, a cache
miss has occurred. For a cache miss, the cache allocates a new entry and
copies in data from main memory, then the request is fulfilled from the
contents of the cache.
The performance of cache memory is frequently measured in terms of
a quantity called Hit ratio.

Hit ratio = hit / (hit + miss) = no. of hits/total accesses

We can improve Cache performance using higher cache block size,
higher associativity, reduce miss rate, reduce miss penalty, and reduce the time to hit
in the cache.
Cache Mapping:

There are three different types of mapping used for the purpose of cache
memory which are as follows: Direct mapping, Associative mapping, and Set-
Associative mapping. These are explained below.
1.Direct Mapping:

The simplest technique, known as direct mapping, maps each block of main
memory into only one possible cache line. Or In Direct mapping, assigne each
memory block to a specific line in the cache. If a line is previously taken up by a
memory block when a new block needs to be loaded, the old block is trashed. An
address space is split into two parts index field and a tag field. The cache is used to
store the tag field whereas the rest is stored in the main memory. Direct mapping`s
performance is directly proportional to the Hit ratio.
For purposes of cache access, each main memory address can be
viewed as consisting of three fields.

2.AssociativeMapping:
In this type of mapping, the associative memory is used to store
content and addresses of the memory word. Any block can go into any line of the
cache. This means that the word id bits are used to identify which word in the block
is needed, but the tag becomes all of the remaining bits. This enables the placement
of any word at any place in the cache memory. It is considered to be the fastest and
the most flexible mapping form.
3.Set-associative Mapping: :
Set-associative mapping allows that each word that is present in the
cache can have two or more words in the main memory for the same index address.
Set associative cache mapping combines the best of direct and associative cache
mapping techniques.
Application of Cache Memory:

1. Usually, the cache memory can store a reasonable number of blocks at any given
time, but this number is small compared to the total number of blocks in the main
memory.
2. The correspondence between the main memory blocks and those in the cache is
specified by a mapping function.

Types of Cache :

 Primary Cache : A primary cache is always located on the processor chip. This
cache is small and its access time is comparable to that of processor registers.
 Secondary Cache : Secondary cache is placed between the primary cache and the
rest of the memory. It is referred to as the level 2 (L2) cache. Often, the Level 2
cache is also housed on the processor chip.

Locality of reference :
Since size of cache memory is less as compared to main memory. So to
check which part of main memory should be given priority and loaded in cache is
decided based on locality of reference.

Types of Locality of reference:

1. Spatial Locality of reference: This says that there is a chance that element will
be present in the close proximity to the reference point and next time if again
searched then more close proximity to the point of reference.
2. Temporal Locality of reference: In this Least recently used algorithm will be
used. Whenever there is page fault occurs within a word will not only load word
in main memory but complete page fault will be loaded because spatial locality of
reference rule says that if you are referring any word next word will be referred in
its register that’s why we load complete page table so the complete block will be
loaded.

*****

6.Virtual Memory:

Virtual Memory is a storage allocation scheme in which secondary

memory can be addressed as though it were part of main memory. The addresses a
program may use to reference memory are distinguished from the addresses the
memory system uses to identify physical storage sites, and program generated
addresses are translated automatically to the corresponding machine addresses.
 The size of virtual storage is limited by the addressing scheme of
the computer system and amount of secondary memory is available not by the actual
number of the main storage locations.
It is a technique that is implemented using both hardware and software. It maps
memory addresses used by a program, called virtual addresses, into physical
addresses in computer memory.

Demand Paging :

The process of loading the page into memory on demand (whenever page
fault occurs) is known as demand paging.

The process includes the following steps :

1. If CPU try to refer a page that is currently not available in the main memory, it
generates an interrupt indicating memory access fault.
2. The OS puts the interrupted process in a blocking state. For the execution to
proceed the OS must bring the required page into the memory.
3. The OS will search for the required page in the logical address space.
4. The required page will be brought from logical address space to physical address
space. The page replacement algorithms are used for the decision making of
replacing the page in physical address space.
5. The page table will updated accordingly.
6. The signal will be sent to the CPU to continue the program execution and it will
place the process back into ready state.
Hence whenever a page fault occurs these steps are followed by the
operating system and the required page is brought into memory.

Swapping:
Swapping a process out means removing all of its pages from memory,
or marking them so that they will be removed by the normal page replacement
process. Suspending a process ensures that it is not runnable while it is swapped out.
At some later time, the system swaps back the process from the secondary storage to
main memory. When a process is busy swapping pages in and out then this situation
is called thrashing.

Thrashing :

In the given diagram, initial degree of multi programming up to some extent of

point(lamda), the CPU utilization is very high and the system resources are utilized
100%. But if we further increase the degree of multi programming the CPU
utilization will drastically fall down and the system will spent more time only in the
page replacement and the time taken to complete the execution of the process will
increase. This situation in the system is called as thrashing.

Causes of Thrashing :
1. High degree of multiprogramming : If the number of processes keeps on
increasing in the memory than number of frames allocated to each process will be
decreased. So, less number of frames will be available to each process. Due to
this, page fault will occur more frequently and more CPU time will be wasted in
just swapping in and out of pages and the utilization will keep on decreasing..
2. Lacks of Frames: If a process has less number of frames then less pages of that
process will be able to reside in memory and hence more frequent swapping in
and out will be required. This may lead to thrashing. Hence sufficient amount of
frames must be allocated to each process in order to prevent thrashing.
Recovery of Thrashing :

 Do not allow the system to go into thrashing by instructing the long term
scheduler not to bring the processes into memory after the threshold.
 If the system is already in thrashing then instruct the mid term schedular to
suspend some of the processes so that we can recover the system from thrashing.

***THE END***