DMF690N
DMF690N
htm
References :
1 - Z88 Service Manual - Issue 1, January 1985
(Prepared by BRAVEMAY for Cambridge Computer Ltd.)
Introduction
1 - Integrated circuits
1.1.1 - Version
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1.1.2 - Pinout
+--------------+
A11 |1 +--+ 40| A10
A12 |2 39| A9
A13 |3 38| A8
A14 |4 37| A7
A15 |5 36| A6
CLK |6 35| A5
D4 |7 34| A4
D3 |8 33| A3
D5 |9 32| A2
D6 |10 Z84C00 31| A1
VCC |11 CPU 30| A0
D2 |12 29| GND
D7 |13 28| /RFSH
D0 |14 27| /M1
D1 |15 26| /RST
/INT |16 25| /BUSRQ
/NMI |17 24| /WAIT
/HALT |18 23| /BUSAK
/MREQ |19 22| /WR
/IORQ |20 21| /RD
+--------------+
1.1.3 - Clocks
Two clocks are driving the Z80. MCK, the master clock and SCK, the standby clock.
The MCK (3.2768 MHz) is generated by a 9.8304 Xtal to the Blink and divided by 3, given to the pin 6.
The SCK pulses at 25.6 KHz and is active on COMA state.
1.1.4 - Interrupts
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BUSRQ (Bus Request) : used for DMA (not connected on the Z88)
NMI (Non Maskable Interrupt) : Jumps to $0066 (BatLow, RTC...)
INT (Ordinary Interrupt) : used in mode 1 (IM1)
For dealing with the maskable interruptions (INT), the Z80 can be switch in three modes.
The interrupt mode 0 (IM0) : for 8080 compatibility
The interrupt mode 1 (IM1) : for non-zilog environnemt (our case)
The interrupt mode 2 (IM2) : for zilog environnement
+--------------+
POE |1 +--+ 32| VCC
A16 |2 31| A15
A14 |3 30| VCC
A12 |4 29| WE
A7 |5 28| A13
A6 |6 27| A8
A5 |7 Z88 26| A9
A4 |8 RAM 25| A11
A3 |9 PCB 24| POE
A2 |10 23| A10
A1 |11 22| CE
A0 |12 21| D7
D0 |13 20| D6
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D1 |14 19| D5
D2 |15 18| D4
VSS |16 17| D3
+--------------+
This table describes the 128K chip pinout and Blink signals.
For a 512K upgrade, you will have to wire the A17 and A18 pins with a
link directly to address lines on a slot connector soldier. Only the OZ
version 4 for UK is able to recognise an internal 512K upgrade.
Replacing the old 42832 Rams will spare your battery life time. The
slowest rams have less consumation (120 or 150 ns). For example :
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The serial rom chip is an UV eprom NEC uPD23C1000C for foreign OZ.
The UK version may be an eprom chip for v2.2, the v3.0 supports exactly
the same software but have been put in a ROM which have only 28 pins.
The last v4.0 is fitted on an EPROM chip. The socket layout isn't
standard according to the NEC standard (see below). If you wish to fit
a new eprom, be very careful, pins 2 and 24 must be exchanged according
to the JEDEC standard. Particulary if you want to use actual 128K Eprom
chip, like 27C1001. In theory, you can fit larger eprom (like 27C2000
or 27C4000) if you wire the addresses lines.
+--------------+
VCC |1 +--+ 32| VCC
ROE |2 31| VCC
A15 |3 30| VCC
A12 |4 29| A14
A7 |5 28| A13
A6 |6 27| A8
A5 |7 Z88 26| A9
A4 |8 ROM 25| A11
A3 |9 PCB 24| A16
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This table describes the 128K chip pinout and Blink signals.
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50 LD2 (display)
51 LD3 (display)
The new Flash Eprom cards represent a new way for Z88 storage. Its
main feature is an integrated electrical erasure. The prototype cards
are built with an Intel 28F008SA and the serial cards uses the Intel
28F008S5 (which is fastest). Theyre low relative cost make them the new
media for 1 Megabyte application card and file storage.
They have 44 pins in a PSOP format (0.5 mm between each pin). They
are linked to the slot connector like standard eproms.
+--------------+
VPP |1 +--+ 44| VCC
RP# |2 43| -
A11 |3 42| A12
A10 |4 41| A13
A9 |5 40| A14
A8 |6 39| A15
A7 |7 38| A16
A6 |8 37| A17
A5 |9 36| A18
A4 |10 35| A19
- |11 Intel 34| -
- |12 28F008 33| -
A3 |13 SA/S5 32| -
A2 |14 31| -
A1 |15 30| WE#
A0 |16 29| OE#
D0 |17 28| -
D1 |18 27| D7
D2 |19 26| D6
D3 |20 25| D5
GND |21 24| D4
GND |22 23| VCC
+--------------+
The table below describes the links between the edge connector and the chip.
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4 MA7 A7 7
5 MA6 A6 8
6 MA5 A5 9
7 MA4 A4 10
8 MA3 A3 13
9 MA2 A2 14
10 MA1 A1 15
11 MA0 A0 16
12 MDA D0 17
13 MDB D1 18
14 MDC D2 19
15 SNS
16 GND GND 21
17 GND GND 22
18 MA14 A14 40
19 VPP VPP 1
20 VCC VCC 44,23
21 VCC -
22 PGM WE# 30
23 MA13 A13 41
24 MA8 A8 6
25 MA9 A9 5
26 MA11 A11 3
27 POE -
28 EOE OE# 29
29 MA10 A10 4
30 SE3 CE# 43
31 MDH D7 27
32 MDG D6 26
33 MDD D3 20
34 MDE D4 24
35 MDF D5 25
36 MA17 A17 37
37 MA18 A18 36
38 MA19 A19 35
Other pins:
Pin 1 : Vpp
Pin 23: Vcc
Pin 44: Vcc
Must be connected to a 100nF ceramic capacitor.
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2 - The Connectors
Slot RAM/ROM RAM/ROM Eprom Pins for Pins for Pins for
pins Slot 1 Slot 2 Slot 3 32K 128K 32K
Signals Signals Signals EPROM EPROM RAM
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Component P C B
Side A Edge Side B
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Note : DTR is high when the machine is awake. The machine is always
awake when the screen is active, but even if asleep the machine will
wake every minute or so to carry out various housekeeping tasks, such
as checking for alarms, and at these time DTR will go high. Pin 1 will
show a signal if there is power available to the machine.
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7 --------- 5
8 - 9
The keyboard is just 8 * 8 matrix between the Z80 address and data
buses. It is connected on SK6 and SK7. In theory it is possible to
replace the membrane by a PCB with mechanical keys (and resistors in
serial). The rubber keyboard technology seems to consume a lot of
power.
There are two issues for the keyboard membrane : a red one, the
first, and the green one which is the last and the most common. The
first issue (red) seems to be often unreliable with a lot of short
circuits which sends a lot of unexpected characters... It is impossible
to repair them. The green issues are very good. I have got mine since
ten years and I am actually typing on it...
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The keyboard is probably the only part with which you encountered
troubles. You can keep the same for all your life if you think to clean
the contacts sometimes. After a long time, some carbon particle
agglomerate on the membrane and generate short-circuits. The
only thing to do is to clean the contact surfaces with some
alcohol. Unscrew the case, deconnect the keyboard ribbons. Pull out the
rubber and be very careful of the three slot. Clean all the keys
surfaces on the rubber and the membrane with a tissue with a few
standard alcohol (90°). Dry it before reassembling. Do it carefully
especially on the cursor, tab, diamond, square, enter and shift keys.
Ribbon signals:
14 is the left one, 1 is on the right in top view.
All of these signals are directly managed by the blink. It builts the screen by
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reading directly in the memory the different character set and screen base.
The cursor is hardware managed too.
Conclusion
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