INDEX

Ex.No. Date Name of the Experiment Page No. Sign.

1a. 1
STUDY OF LOGIC GATES

1b. VERIFICATION OF BOOLEAN THEOREM 6

USING DIGITAL LOGIC GATES
DESIGN AND IMPLEMENTATION OF
2 14
COMBINATIONAL CIRCUITS USING GATES
FOR ARBITRARY FUNCTIONS
3a. 16
DESIGN OF HALF ADDER AND FULL ADDER

3b. DESIGN OF HALF SUBTRACTOR AND FULL 19

SUBTRACTOR
3c. 22
4- BIT BINARY ADDER AND SUTRACTOR

4a. D DESIGN AND IMPLEMENTATION OF CODE 26

CONVERTERS ( BINARY TO GRAY CODE &
GRAY CODE TO BINARY )
4b. DESIGN AND IMPLEMENTATION OF CODE 30
CONVERTERS ( BCD TO EXCESS -3 CODE &
EXCESS-3 CODE TO BCD )
5a. D DESIGN AND IMPLEMENTATION OF BCD 34
ADDER
5b. DESIGN AND IMPLEMENTATION OF 36
ENCODER AND DECODER
6 39
MULTIPLEXER AND DEMULTIPLEXER

7 DESIGN AND IMPLEMENTATION 43

SYNCHRONOUS UP AND DOWN COUNTER
8 DESIGN AND IMPLEMENTATION OF 47
SHIFT REGISTERS
9 SIMULATOR BASED STUDY OF COMPUTER 51
ARCHITECTURE
EXP. NO : 1a STUDY OF LOGIC GATES
DATE :

AIM :
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SLNo. COMPONENT SPECIFICATION QTY

1. AND GATE IC7408 1
2. OR GATE IC7432 1
3. NOTGATE IC7404 1
4. NAND GATE2I/P IC7400 1
5. NOR GATE IC7402 1
6. X-ORGATE IC7486 1
7. NAND GATE 3I/P IC7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - As required

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate has
one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR
are known as universal gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs
is low.
ORGATE:
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The output is
low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.
The output is low when one or both inputs are high.
X-OR GATE :
The output is high when any one of the inputs is high. The output is low when both the
inputs are low and both the inputs are high.
PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:
NOT GATE:

SYMBOL: PIN DIAGRAM:

X-OR GATE:

SYMBOL: PIN DIAGRAM :

2- INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3- INPUT NAND GATE :

 5

NOR GATE:

RESULT :

5
 6

EXP. NO :1b. VERIFICATION OF BOOLEAN THEOREM USING DIGITAL

DATE : LOGIC GATES

AIM :
To verify the truth table of basic Boolean algebraic laws by using logic gates.

APPARATUS REQUIRED:

SLNo. COMPONENT SPECIFICATION QTY

1. AND GATE IC7408 1
2. OR GATE IC7432 1
3. NOT GATE IC7404 1
4. IC TRAINERKIT - 1
5. CONNECTING WIRES - As required
THEORY:
BOOLEAN LAWS
Boolean algebra is a mathematical system consisting of a set of two or more distinct
elements, two binary operators denoted by the symbols (+) and (.) and one unary operator
denoted by the symbol either bar (-) or prime (‘). They satisfy the commutative, associative,
distributive and absorption properties of the Boolean algebra.
PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

COMMUTATIVE LAW :
Binary variables in Boolean Algebra follow the commutative law. This law states that
operating Boolean variables A and B is similar to operating Boolean variables B and A. That is,
1. A+B = B+A

Truth Table:
Input Output
A B A+B B+A
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1
 7

2. A B = B A

A 1 B 1
7408 3 AB = 3 BA
7408
B 2 A 2
Truth Table:

Input Output
A B A.B B.A
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1

ASSOCIATIVE LAW :
Associative law state that the order of performing Boolean operator is illogical as their
result is always the same. This can be understood as,
1. ( A + B ) + C = A + ( B + C)

Truth Table:
Input Output
A B C A+B (A+B)+C B+C A+(B+C)
0 0 0 0 0 0 0
0 0 1 0 1 1 1
0 1 0 1 1 1 1
0 1 1 1 1 1 1
1 0 0 1 1 0 1
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1
 8

2. ( A B ) C = A ( B C )

Truth Table
Input Output
A B C A.B (A.B).C B.C A.(B.C)
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 0 0 0 0
1 0 1 0 0 0 0
1 1 0 1 0 0 0
1 1 1 1 1 1 1

DISTRIBUTIVE LAW :

Boolean Variables also follow the distributive law and the expression for Distributive law is given
as:
1. A ( B + C) = (A . B) + (A . C)
 9

Truth Table

Input Output
A B C B+C A.(B+C) A.B A.C A.B+A.C
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1

2. A + ( B C) = (A + B) . (A + C)

Truth Table

Input Output
A B C B.C A+(BC) A+B A+C A+B.A+`C
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1
-
 10

ABSORPTION LAW :
The Absorption Law in Boolean Algebra consists of two fundamental identities that simplify
expressions using the "absorbing" terms. These laws are:
1.A+(A.B)=A

Truth Table

INPUT OUTPUT
A B A.B A+(AB) A
0 0 0 0 0
0 1 0 0 0
1 0 0 1 1
1 1 1 1 1

2.A.(A+B)=A

Truth Table

INPUT OUTPUT
A B A+B A(A+B) A
0 0 0 0 0
0 1 1 0 0
1 0 1 1 1
1 1 1 1 1
 11

IDEMPOTENT LAW :
1. A + A = A

Truth Table

INPUT OUTPUT
A A+A A
0 0 0
1 1 1

2.A . A = A

Truth Table

INPUT OUTPUT
A A.A A
0 0 0
1 1 1
 12

INVOLUTION OR DOUBLE COMPLEMENTS LAW:

A=A

Truth Table

INPUT OUTPUT
A A’ A’ A
0 1 0 0
1 0 1 1

COMPLEMENT LAW :
The Complementary Theorem deals with the behavior of Boolean expressions involving
variables and their complements.
1. A + A’ = 1

Truth Table

INPUT
OUTPUT
A A’ A+A’
0 1 1 1
1 0 1 1

2. A . A’ = 0

Truth Table

INPUT
OUTPUT
A A’ A.A’
0 1 0 0
1 0 0 0
 13

DE MORGAN’S THEOREM :

The complement of the sum is equal to the sum of product of the individual complements
1.A+B = A . B

The complement of the product is equal to the sum of the individual complements

2.A . B = A+B

RESULT :
 14

EXP. NO :2 DESIGN AND IMPLEMENTATION OF COMBINATIONAL

DATE : CIRCUITS USING GATES FOR ARBITRARY FUNCTIONS

AIM :
To Design and implementation of combinational circuits using gates for arbitrary functions

APPARATUS REQUIRED:

SLNo. COMPONENT SPECIFICATION QTY

1. AND GATE IC7408 1
2. OR GATE IC7432 1
3. NOT GATE IC7404 1
4. NAND GATE IC7400 1
5. NOR GATE IC7402 1
6. IC TRAINERKIT - 1
7. CONNECTING WIRES - As required

THEORY:

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.
 15

RESULT :
 16

EXP. NO :3a. DESIGN OF HALF ADDER AND FULL ADDER

DATE :

AIM :

To design and construct Half Adder & Full Adder circuits and verify the truth table using
logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC7408 1
2. X-OR GATE IC7486 1
3. NOT GATE IC7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - As required
THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one
from the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above
circuit is called as a carry signal from the addition of the less significant bits sum from
the X-OR Gate the carry out from the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a
time but a half adder cannot do so. In full adder sum output will be taken from X-OR
Gate ,carry output will be taken from OR Gate.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

 17

LOGIC DIAGRAM OF HALF ADDER:

TRUTH TABLE:
A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM=A’B +AB’ CARRY= AB

LOGIC DIAGRAM OF FULL ADDER USING TWO HALF ADDER:

 18

TRUTH TABLE:

A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
K-Map for SUM:

SUM=A’B’C+A’BC’+ABC’+AB

K-Map for CARRY

CARRY=AB+BC+AC

RESULT :
 19

EXP. NO :3b. DESIGN OF HALF SUBTRACTOR AND FULL SUBTRACTOR

DATE :

AIM :

To design and construct Half subtractor and full subtractor circuits and verify the truth table
using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC7408 1
2. X-OR GATE IC7486 1
3. NOT GATE IC7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - As required
THEORY:
HALF SUBTRACTOR :
The half subtractor is constructed using X-OR and AND Gate. The half
subtractor has two input and two outputs. The outputs are difference and borrow. The
difference can be applied using X-OR Gate, borrow output can be implemented using
an AND Gate and an inverter.
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half
subtractor put together gives a full subtractor .The first half subtractor will be C and A
B. The output will be difference output of full subtractor. The expression AB assembles
the borrow output of the half subtractor and the second term is the inverted difference
output of first X- OR.
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

 20

HALF SUBTRACTOR

TRUTH TABLE:

A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-MAP FOR DIFFERENCE: K-MAP FOR BORROW:

DIFFERENCE=A’B+AB’ BORROW=A’B

LOGIC DIAGRAM FULL SUBTRACTOR

 21

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:
A B C BORROW DIFFERENCE
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1

1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-MAP FOR DIFFERENCE: K-MAP FOR BORROW:

DIFFERENCE=A’B’C+A’BC’+AB’C’+ABC BORROW=A’B+BC+A’C

RESULT :
 22

EXP. NO : 3c 4- BIT BINARY ADDER AND SUTRACTOR

DATE :

AIM :
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SLNo. COMPONENT SPECIFICATION QTY

1. IC IC7483 1
2. EX-OR GATE IC7486 1
3. NOT GATE IC7404 1
4. IC TRAINERKIT - 1
5. PATCH CORDS - As required
 23

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.
24
 25

RESULT :
 26

EXP. NO : 4a DESIGN AND IMPLEMENTATION OF CODE CONVERTERS

DATE : ( BINARY TO GRAY CODE & GRAY CODE TO BINARY )

AIM :
To design and implement 4-bit
Binary to gray code converter
Gray to binary code converter

APPARATUS REQUIRED:

SLNo. COMPONENT SPECIFICATION QTY

1. EX-OR GATE IC7486 1
2. AND GATE IC7408 1
OR GATE IC74032 1
3. NOT GATE IC7404 1
4. IC TRAINERKIT - 1
5. PATCH CORDS - As required

THEORY:
The availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be inserted
between the two systems if each uses different codes for same information. Thus, code
converter is a circuit that makes the two systems compatible even though each uses different
binary code.
The bit combination assigned to binary code to gray code. Since each code uses four bits
to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-
weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, Combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though each uses a
different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit
combination of elements asspecifiedbycodeandtheoutputlinesgeneratethecorrespondingbitcombination of
code. Each one of the four maps represents one of the four outputs of the circuit as a function of the four
input variables. A two-level logic diagram may be obtained directly from the Boolean expressions derived by
the maps. These are various other possibilities for a logic diagram that implements this circuit. Now the OR
gate whose output has been used to implement partially each of three outputs.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

 27

LOGIC DIAGRAM BINARY TO GRAY CODE CONVERTOR

K-Map for G3: K-Map for G2:

G3=B3

K-Map for G1: K-Map for G0:

 28

TRUTH TABLE:
| Binary input | Gray code output |
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

LOGIC DIAGRAM GRAY CODE TO BINARY CONVERTOR

K-Map forB3: K-Map forB2:

B3=G3
 29

K-Map for B1: K-Map for B0:

TRUTH TABLE:
| Gray Code | Binary Code |
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

RESULT :
 30

EXP. NO : 4b. DESIGN AND IMPLEMENTATION OF CODE CONVERTERS

DATE : ( BCD TO EXCESS -3 CODE & EXCESS-3 CODE TO BCD )

AIM :
To design and implement 4-bit
BCD to Excess-3 code converter
Excess-3 code to BCD converter

APPARATUS REQUIRED:

SLNo. COMPONENT SPECIFICATION QTY

1. EX-OR GATE IC7486 1
2. AND GATE IC7408 1
OR GATE IC74032 1
3. NOT GATE IC7404 1
4. IC TRAINERKIT - 1
5. PATCH CORDS - As required

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

LOGIC DIAGRAM FOR BCD TO EXCESS-3 CODE CONVERTER

 31

K-Map for E3: K-Map for E2:

E3=B3+B2(B0+B1)

K-Map for E1: K-Map for E0:

TRUTH TABLE:

| BCD input | Excess–3 output |

B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x X
1 0 1 1 x x x X
1 1 0 0 x x x X
1 1 0 1 x x x X
1 1 1 0 x x x X
1 1 1 1 x x x X
 32

LOGIC DIAGRAM FOR EXCESS – 3 CODE TO BCD CONVERTER

K-Map for A: K-Map for B:

A=X1X2+X3X4X1

K-Map for C: K-Map for D:

`
 33

TRUTH TABLE:

| Excess–3 Input | BCD Output |

E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

RESULT :
 34

EXP. NO : 5a. DESIGN AND IMPLEMENTATION OF BCD ADDER

DATE :

AIM :

To design and implementation of BCD Adder circuit

APPARATUS REQUIRED:

SLNo. COMPONENT SPECIFICATION QTY

1. IC IC7483 2
2. AND GATE IC7408 1
3. OR GATE IC74032 1
4. IC TRAINERKIT - 1
5. PATCH CORDS - As required

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.
 35

TRUTH TABLE:

RESULT :
 36

EXP. NO : 5b DESIGN AND IMPLEMENTATION OF

DATE : ENCODER AND DECODER

AIM :
To design and implement Encoder and Decoder circuit

APPARATUS REQUIRED:

SLNo. COMPONENT SPECIFICATION QTY

1. 3 I/P NAND GATE IC7410 2
2. OR GATE IC7432 3
3. NOT GATE IC7404 1
4. IC TRAINERKIT - 1
5. PATCH CORDS - As required

THEORY:
ENCODER:

An encoder is a digital circuit that perform inverse operation of a decoder. An encoder has
n
2 input lines and n output lines. In encoder the output lines generates the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each
octal digit and three output that generate the corresponding binary code. In encoder it is
assumed that only one input has a value of one at any given time otherwise the circuit is
meaningless. It has an ambiguil a that when all inputs are zero the outputs are zero. The zero
outputs can also be generated when D0 = 1.

DECODER:

A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has
fewer bits than the output code. Each input code word produces a different output code word i.e
there is one to one mapping can be expressed in truth table. In the block diagram of decoder
n n
circuit the encoded information is present as on input producing 2 possible outputs. 2 output
n
values are from 0 throughout2 –1.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

37
 38

RESULT :
 39

EXP. NO : 6 MULTIPLEXER AND DEMULTIPLEXER

DATE :

AIM :
To design and implement multiplexer and de multiplexer using logic gates and study of IC 74150
and IC 74154.

APPARATUS REQUIRED:

SLNo. COMPONENT SPECIFICATION QTY

1. 3 I/PANDGATE IC7411 2
2. OR GATE IC7432 1
3. NOTGATE IC7404 1
4. ICTRAINERKIT - 1
5. PATCHCORDS - As required

THEORY:
MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a smaller

number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of
n
a particular input line is controlled by a set of selection lines. Normally there are 2 input line
and n selection lines whose bit Combination determine which input is selected.

DEMULTIPLEXER:

The function of De multiplexer is in contrast to multiplexer function. It takes

information from one line and distributes it to a given number of output lines. For this
reason, the de multiplexer is also known as a data distributor. Decoder can also be used as de
multiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.
 40

BLOCK DIAGRAM FOR4:1 MULTIPLEXER:

FUNCTIONTABLE:
S1 S0 INPUTSY
0 0 D0→D0S1’S0’
0 1 D1→D1S1’S0
1 0 D2→D2S1S0’
1 1 D3→D3S1S0

Y=D0S1’S0’+D1S1’S0+D2S1S0’+D3S1S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y= OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
 41

BLOCK DIAGRAM FOR1:4 DEMULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUT
0 0 X→D0=XS1’S0’
0 1 X→D1=XS1’S0
1 0 X→D2=XS1S0’
1 1 X→D3=XS1S0

Y=XS1’S0’+XS1’S0+XS1S0’+XS1S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:

`
 42

TRUTH TABLE:

INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

PIN DIAGRAM IC 74150 PIN DIAGRAM IC 74154

RESULT :

`
 43

EXP. NO : 7 DESIGN AND IMPLEMENTATION

DATE : SYNCHRONOUS UP AND DOWN COUNTER

AIM :
To design and implement 3bit synchronous up/down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIPFLOP IC7476 2
2. 3 I/P ANDGATE IC7411 1
3. OR GATE IC7432 1
4. XORGATE IC7486 1
5. NOTGATE IC7404 1
6. ICTRAINERKIT - 1
7. PATCHCORDS - As required

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. An up/down counter is one
that is capable of progressing in increasing order or decreasing order
throughacertainsequence.Anup/downcounterisalsocalledbidirectionalcounter. Usually
up/down operation of the counter is controlled by up/down signal. When this signal is high
counter goes through up sequence and when up/down signal is low counter follows reverse
sequence.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

K MAP :

`
 44

STATE DIAGRAM :

CHARACTERISTICS TABLE:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
 45

LOGIC DIAGRAM:

TRUTH TABLE:

Input PresentState NextState A B C

Up/Down QA QB QC QA+1QB+1QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
 46

RESULT :
 47

EXP. NO : 8 DESIGN AND IMPLEMENTATION OF

DATE : SHIFT REGISTERS

AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out Shift Register

APPARATUSREQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIPFLOP IC7474 2
2. OR GATE IC7432 1
3. IC TRAINERKIT - 1
4. PATCH CORDS - As required
THEORY:

A register is capable of shifting its binary information in one or both directions is known
as shift register. The logical configuration of shift register consist of a D-Flipflop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common clock
pulses which causes the shift in the output of the flip flop.

The simplest possible shift register is one that uses only flip flop. The output of a given
flip flop is connected to the input of next flip flop of the register. Each clock pulse shifts the
content of register one bit position to right.

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.
 48

PIN DIAGRAM:

LOGIC DIAGRAM SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK Serial in Serial out

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
 49

LOGIC DIAGRAM SERIAL IN PARALLEL OUT:

TRUTH TABLE:

OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

LOGIC DIAGRAM PARALLEL IN SERIAL OUT:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
 50

LOGIC DIAGRAM PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

DATAINPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

RESULT :
 51

EXP. NO : 9 SIMULATOR BASED STUDY OF COMPUTER ARCHITECTURE

DATE :

AIM:

THEORY:
Computer architecture is one of the important subjects offered at universities across the
world. Teaching in traditional way can be insufficient if the teaching focus is solely on the textbook
materials. One of the most critical aspects on teaching this discipline is how to support the
theoretical concepts of the subject with appropriate practical experience, usually organized as
laboratory experiments. But practically, students are unable to understand the subject. For this
reason, may educators have begun using different computer architecture simulators based on
hardware and software to solve this problem. There are minly about three simulators: Logism,
CEDAR and CPT sim.
LOGISM:
Logi sim is a simple software which can be used for implementing circuits with basic basic
gates. Users of this simulator can draw the circuits using the tool box available. The circuit
automatically propagates circuit values through the circuit by selecting the suitable tool and the
user can toggle the input conditions to learn how the circuit behaves in other situations. Student
themselves were able to understand how to connect basic gates to make simple as wll as complex
circuits with the help of Logisim.

CEDAR

CEDAR is a power simulator in which the student can implement a complete computer and will be
able to understand the internal details of a computer more clearly. Using CEDAR simulator student
can 1) build the entire computer hardware using fundamental logic gates; 2) write an assembler to
translate the test program into machine level program; 3) load the program into the memory of
the computer; and 4) run the test program on these hardware. After the implementation students
can see how a computer executes a program and what are the signals generated during each clock
pulse.
 52

CPU Sim

CPU Sim is an interactive simulation tool in which the user can specify the details of the
CPU to be simulated, such as register set, of microinstructions, set of machine instructions and set
of assembly language instructions. Users of the tool can write their own machine or assembly
language program and run on the CPU they have created. It simulates the computer architecture at
register transfer level so that the students will get a better understanding about the system. User of
the simulator has to specify the hardware units and the microinstructions for the CPU and then
create the set of machine instructions. Corresponding to each machine instruction a sequence of
microinstructions is to be formed.

RESULT :