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Nanosystems

Prof. Markus Becherer

Dipl.-Ing. Johannes Greil

Technische Universität München

School of Computation, Information and Technology

Professorship of
Chip-based Magnetic Sensor Technology

Discover the world of

Nanoelectronics

With this document, I want to provide notes on my slides and give some additional
information. Yes, indeed, a real script would be beneficial. However, I try to combine
the slides with these notes, where I try to add the comments needed to explain the topic.
Whether you print or not, the document is up to you, but I think it might be useful for
your studies at home. First explanation: on the right, you see the Uhrenturm of TUM
:-)
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Milestones in Nanotechnology → watch the typos

The milestones that are picked are neither complete nor fair, I provide some of the
many highlights. Without Richard Feynman and his visionary talk, one cannot think of
Nanotechnology, and without the Scanning Tunneling Microscope (STM) of Binnig and
Rohrer, the list would indeed be incomplete. However, I copied this list from an older
lecture of the Chair of Nanoelectronics that was established at TUM in 2002, and only a
.gif file remained. Unfortunately, I discovered at least 3 typos marked in red. I decided
to go with the errors because they are typical for nanostructures and nanosystems. One
has to deal with errors, defects, and shortcomings. Nothing is perfect, especially when it
comes to very small structures, and without having control of errors and deviation, there
is hardly a Nanosystem to be envisioned.
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Scale of Things

What is Nano?

At least one dimension in the

Nanometer range.

It is a simple definition, easy to remember.

http://www.asu.edu/clas/csss/NUE/img/Scale-of-Things.jpg 3

The scale of things. If you search the web for this, you will find tons of material. The
scales of things vary over many orders of magnitude, and this image covers scales below
1 m down to the size of atoms. Here, my very personal definition of Nanosystems comes
into play: if we deal with objects where one (spatial) dimension is in the nm range,
we deal with nanotechnology and with the toolbox of nanotechnology, we aim to solve
different kinds of problems in so-called more complex arrangements (settings) that we call
nanosystems. Another simple definition taken from the Wiktionary says: ‘Any physical
system that is engineered at the nanoscale.’ Again, simple and easy.
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Scale
of
Things

http://www.asu.edu/clas/csss/NUE/img/Scale-of-Things.jpg
4

Just a zoom-in for you, where the nanoworld is between 1 nm and 1 µm, but the definition
of Nano does not have to be that strict.
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Top
down

Bottom
up
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This is a well-known graph explaining the down and bottom-up approach in nanotech-
nology. It plots the complexity of a technical system or a living animal over the size of
its ‘components’ . Even though it is very popular, I do not know if it is of much help
– or maybe I am missing the respective classes in philosophy. Maybe the explanation
could go in such a way that often living animals, and biological entities are self-organized,
starting from a single cell, and by dividing and specializing them for various tasks, an
organism forms. It is different in technical systems like integrated circuits because we
start from something very simple, like a transistor (it is not simple at all, but anyway),
and scale it down to the nanometer regime to form complex integrated circuits. But isn’t
it intriguing that in electronic design automation, we talk about standard cells and put
them together and form something complex like a microprocessor? Is this bottom up or
top down?
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Silicon CMOS is the most mature Nanotechnology

Let’s dive into a topic you might be bored of because you heard about it so many times.
But give me the chance to convince you that silicon CMOS technology is an advanced
nanotechnology. Unfortunately, when it comes to device fabrication, far too costly for
University research. Instead, it is a billion-dollar industry and started with Moore’s law.
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Moore‘s Law --- as you might know it 2 16 = 65536 Components

Original drawing of Gordon Moore (1965)

Relative manufacturing cost/component

Number of components per integrated circuit

➔ There is an optimum number of transistors per chip.

Proc. IEEE, Vol 86., 1998 (Reprint of Orig. Paper)
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Moore’s law is not a ‘physical law,’ but simply a relation Gordon Moore found when
analyzing the cost of manufacturing data. It was an economic fact, discovered by Gordon
Moore in the 60s of the last century. He looked at the cost to fabricate integrated circuits
on chip and, by plotting the relative manufacturing cost per component (transistors) over
the number of components per integrated circuit, he got curves with a minimum. There is
a minimum in cost per device because if you put too small several devices on a chip, you
still have all the processing costs, substrate costs, etc., making one device expensive. But
if you put too many devices in a circuit, the yield drops, and you cannot sell the chip.
The chips do not work because of defective devices and low yield or reliability. Moore
recognized this, and from the trend over a couple of years, he made the bold prediction
(extrapolation) that there would be an exponential growth of the number of components
(transistors) on a chip because the cost per function drops when scaling the components
to smaller dimensions.
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With 10 cores and up to 30 MByte L3-Cache and estimated 2,9

Billion transistors is Intel‘s new Procesor Westmere-EX after
Nvidias Fermi the secondlargest Chip on the market.
Source: www.heise.de ,2011.
This is the famous
predictions of Moore:
exponential growth of
transistors per chip. 8

Here, you see how bold the extrapolation was or how good it worked. I am unsure if
the predicted growth rate of Moore matches the achieved trend, but it was exponential
growth over more than 50 years, and it worked for memory, processors, and even in the
hard-drive industry.
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→ see pdf Version

This is an even newer trend I found in Wikipedia. The message is the same, just a
bit more detailed. Additionally, I put the 2019 Top Semiconductor Sales Leaders data
into the graph. The semiconductor industry is a billion-dollar industry, and only a few
big companies and foundries can pick up with significant investment in fabrication sites
(fabs). Sometimes, governments invest a lot in such companies to keep them going. Please
note, the ranking is done by ‘growth’ rate rather than the turnover of the company —
this may, at first glance, appear misleading.
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Source: http://www.intel.com
Moore‘s law contd.
1971 Intel 4004 processor
2010 Intel Core-i processor
(Westmere)
Initial clock speed Initial clock speed
108 kHz >3.0 GHz
Number of transistors Number of transistors
2,300 560,000,000
Manufacturing technology Manufacturing technology
10µm 32nm

Cost: 1056 $* Cost: 200 $

0.46 $ per transistor 0.36 ·10-6 $ per transistor

*adjusted for inflation (1971 price: $200)

➔ In 2010, a transistor was 1.000.000 X cheaper than in 1971 10

This is another hopefully good example of Moore’s law and our difficulties with expo-
nential growth behavior. A transistor in a processor chip of 1971 was almost 0.5 USD,
whereas in 2010 it dropped to 0.36 µUSD or 360 nUSD :-). I haven’t seen this behavior,
let’s say, in the car industry yet;-). Scaling to a small physical volume does the trick.
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Headline: Transistor cheaper than printed letter in book!

Westmere-Processor

560 Million 6 Million

transistors characters

Cost: $ 200 Cost: $ 31

USD 0.360 · 10-6 USD 5.16 · 10-6
per transistor per character

→ A printed character is 10 X the cost of one Transistor! 11

A further comparison of the category ‘useless’ : a transistor in a microprocessor is 10 X

cheaper than a printed character in a book.
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1016
109
100 109 Chips per day manufacutured
Transistors produced per day
(all in a row would reach
= 1m = 1 Billion (~20 soccer fields per day) the distance earth --- moon)
Bunch of flowers = 1´000´000´000 m
= 1 Gigameter
Earth with moon orbit

The 45 nm

universe 10-9 www.chipworks.com

= 1/1´000´000´000 m
of 1 Nanometer
~ Size of approx. 4 Si-atoms
Transistor( INTEL Penrynn 2007)
With gate length of 45nm
silicon = 200 Atoms !
Thickness of gate dielectric: 1.2 nm
= 3 molecules! 12

Now you are used to useless categories; hence, I can go on. Even if the numbers are not
entirely correct (who on earth knows the number of transistors produced per day), if we
start to scale things, big numbers are possible. You cannot scale cars a lot; therefore,
the earth is packed with cars. We could scale transistors; therefore, 1 × 1016 transistors
per day can be fabricated without being drowned.
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2D Roadmap at the end of the last century is now history

Prediction and forecast

Year 2012 → 50 nm Generation

Supply Voltage: (0.5 - 0.6) V
Oxide thickness normalized to SiO2

Ioff < 10 nA/µm

I = 5 decades
Ion : 600 µA/µm

VG = 315 mV
(with ideal S = 63 mV/dec)

Starting Yield: 60 %

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For a long time, so-called ‘roadmap’ dictated the annual growth in the semiconductor
industry — or, more precisely, Moore’s Law was fulfilled by sticking to more or less strict
scaling predictions summarized in ‘roadmaps’ . Organizations like IEEE, research insti-
tutions, the semiconductor industry, and suppliers were sitting ‘together’ and writing
down documents and tables called ITRS (International Technology Roadmap for Semi-
conductors). A part of the roadmap from the end of the 90th is given in the slide. It
predicted exactly what would happen until 2012 to follow Moore’s Law. However, some-
times solutions were pursued, sometimes not known, and in retrospect, some predictions
were simply wrong. Nevertheless, I am unaware of other industries with joint agreement
on the following goals. This is a very peculiar thing when thinking about Moore’s law.
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20 Billion switches!
Moore‘s law:
„ Anything that can go well will go well!“
Murphy´s law:
„Anything that can go wrong will go wrong!”
Semiconductor industry:
„Somewhere in between“

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Here, you see the story of great success. Twenty billion transistors on a microprocessor
chip, and despite some parameters like frequency or power that saturated, others did
not, and difficulties in increasing single core performance were compensated by, e.g., the
introduction of logical cores. The lesson we learned: one has to look at the overall system
‘microprocessor’ and not at, e.g., the switching speed of one transistor only. It is not
the nanodevice that matters alone; it is the nanosystem.
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Emerging Research Devices (ERD) Roadmap

end of New devices, new architectures, new concepts.
traditional → Beyond CMOS
roadmap

Nanomagnetic Logic Single

Electronics 0
Quantum
Molecular switch computation

Nanotubes

2000 2020 2040 15

There was a distinct moment in the history of Moore’s law when, in 2016, the traditional
ITRS roadmap was stopped. Until then, people were researching novel materials, devices,
and computing concepts in the Emerging Research Devices (ERD) Roadmap. It was
a lengthy document parallel to the ITRS, published every two years and filled with
novel devices for computation and memory. We contributed with Nanomagnetic Logic
Devices (NML) to this roadmap, where we tried to do computation with field-coupled
ferromagnetic islands. However, suddenly, the ERD stopped — but not too scary for
universities because we always aim to think about novel concepts and methods. Hence,
one can say that the ERD continues, but not in such a clear and ‘organized’ way as
before. One successor of the ITRS is the International Roadmap for Devices and Systems
(IRDS), hosted by the IEEE. https://irds.ieee.org/
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Emerging Research Devices (ERD) Roadmap

end of
traditional
roadmap

Nanomagnetic Logic

2000 2020 2040

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I plotted a nice (albeit a little too colorful) graph called Taxonomy for Nano Information
Processing Technologies from the former ERD. On different levels of abstraction, new
technologies are envisioned. In our case of nanomagnetic logic, we had spin orienta-
tion as a state variable, nanostructured ferromagnetic material for devices, digital data
representation, and pipelined systolic architectures.
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See next slide

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People were always very innovative in the search for funding or public attention. One
example (I do not know its impact, but its look is severe) is the so-called Gartner Hype
Cycle. Innovation is said to always (I should not say always because that is not true)
follow a trend like the one given above. Innovation triggers the peak of inflated expec-
tations, a trough of disillusionment, the slope of enlightenment, and finally, a plateau
of productivity. Please do not take it too seriously (others will do it for you), but it is
fun to read the buzzwords. And if I would put some of the buzzwords in the title of my
lecture, maybe we would’ve been more people today.
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2017 2019

Is there a single emerging technology

that survived? 18

Now I thought, let’s compare the two Gartner Hype cycles for Emerging Technologies
of 2017 and 2019. Do you find a single one-by-one match? Strange. Neuromorphic
hardware should’ve moved further on the cycle. It seems that hypes will not last long.
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The evolution of CMOS technology

Planar MOSFET

RibbonFET

Stacked CMOS

FinFET

3D-Stacked CMOS Takes Moore’s Law to New Heights, IEEE Spectrum, 2022. 19

This slide, composed of pictures from IEEE Spectrum 2022, shows the evolution of FET
transistors from a planar to a complex, fully 3D object.
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S3S
Conference

San
Francisco
Burlingame,
Oct. 2017

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This is my future prediction for Moore’s Law; it might now become true. This decade
is all about real 3D integration and hybrid integration of different technologies. Have
you ever considered bringing your nonvolatile memory close to your microprocessor core?
Are you combining CPU, nonvolatile memory, and optical or radio-frequency channels
on a single chip? Here is one example, and without understanding all the coded details:
300 mm wafers, thinned to about 10 µm and aligned with a precision of 300 nm are put
on top of each other and form a monolithic block with parallel ‘data buses’ created by
interconnects. People claim that a 1000 X improvement in computational power might
be possible. That’s a lot. Moore’s law forever.
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Silicon, silicon, silicon …

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— no comment —
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What is coming next?

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This is the preliminary plan for this semester. We might have to rearrange things a bit,
but in principle, it should work.
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Course Organization
A)
Two hours of lectures/week up to the end of the semester.

There will be a written exam on 13.02.2025.

The exam will count for 100% of the final grade. Exam registration is necessary!
→ Exam registration is NOT the course registration in TUM-Online or MOODLE.

B)
You can sign in for a lab course taking place in Garching. A grade bonus of 0.3 will be applied to the final
grade for completing the voluntary assignment. i.e., hands-on experience, data processing, and summary of
essential aspects → measurement report

Groups are formed via MOODLE. An introductory course will be given via an uploaded video in MOODLE.

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A MUST to read: follow the MOODLE course

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Q 1:
After reading the article of R. P. Feynman: What is – in your opinion – so visionary
about Richard Feynnman’s talk ‘There is plenty of room at the bottom’ ? How would
you continue his ideas with all your background knowledge on Nanotechnology? If you
compare with the 3D integration technology of Silicon CMOS chips — how close did we
(Homo Sapiens) get to R. Feynmans’s vision?
Q 2:
Explain the somewhat contradicting approaches of Top-down and Bottom-up. Pick some
topics in Gartner’s Hype Cycle where Top-down or Bottom-up technologies are emerging.
What is the frustrating/exciting thing about the Hype Cycle?
Q 3:
What is Moore’s law? Explain, in simple words, what Gordon Moore postulated. What
is the link between Moore’s law and the ITRS roadmap? Check the web for the IRDS
roadmap and explain in your own words the new goals.
Q 4:
How could one define a ‘Nanosystem’ ? What makes the difference in complexity to, e.g.,
a physical effect that gives some electrical response due to heat, humidity, or light?