2025-01-05

FPGA/ASIC Design with Verilog

Chapter 2: Combinational Logic Design
Duong Ngoc Phap, Ph.D
Faculty of Computer Engineering and Electronics
Slides to accompany the textbook Digital Design, First Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2007.
http://www.ddvahid.com

January 5, 2025

2.1

Introduction

Digital circuit
 Let’s learn to design digital circuits 1
a 1
 We’ll start with a simple form of circuit: b
0
Combinational
digital circuit
F

• Combinational circuit
 A digital circuit whose outputs depend solely on 1
a ?
the present combination of the circuit inputs’ 0
Sequential
F
values b digital circuit

Note: Slides with animation are denoted with a small red "a" near the animated items
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2.2

Switches
 Electronic switches are the basis
of binary digital circuits
• Electrical terminology
Voltage: Difference in electric 4.5 A
– +
9V
potential between two points 4.5 A
• Analogous to water pressure
2 ohms
 Current: Flow of charged particles
• Analogous to water flow 0V 9V
Resistance: Tendency of wire to
resist current flow 4.5 A
• Analogous to water pipe diameter
V = I * R (Ohm’s Law)

Switches
 A switch has three parts control
input
• Source input, and output
 Current wants to flow from source “off”
input to output
• Control input source output
input a
 Voltage that controls whether that control
current can flow input
“on”
 The amazing shrinking switch
source output
• 1930s: Relays input
• 1940s: Vacuum tubes (b)
• 1950s: Discrete transistor
• 1960s: Integrated circuits (ICs)
 Initially just a few transistors on IC
 Then tens, hundreds, thousands...
discrete
transistor
IC
relay vacuum tube

quarter
(to see the relative size)

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Moore’s Law
 IC capacity doubling about every 18 months for
several decades
• Known as “Moore’s Law” after Gordon Moore, co-
founder of Intel
 Predicted in 1965 predicted that components per
IC would double roughly every year or so
• Book cover depicts related phenomena
 For a particular number of transistors, the IC
shrinks by half every 18 months
• Notice how much shrinking occurs in just about 10
years
• Enables incredibly powerful computation in
incredibly tiny devices
• Today’s ICs hold billions of transistors
 The first Pentium processor (early 1990s) needed
only 3 million

An Intel Pentium processor IC

having millions of transistors

2.3

The CMOS Transistor

 CMOS transistor
• Basic switch in modern ICs a

nMOS
A positive ...attracts electrons here, 1 0
voltage here... turning the channel gate
between source and drain
into a conductor.

gate conducts does not

oxide conduct
IC package
source drain

pMOS
1 0
gate

(a) IC

Silicon -- not quite a conductor or insulator: does not conducts

conduct
Semiconductor

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Boolean Logic Gates

2.4

Building Blocks for Digital Circuits

(Because Switches are Hard to Work With)

 “Logic gates” are better digital circuit building blocks than switches (transistors)
• Why?...

Boolean Algebra and its Relation to Digital

Circuits
 To understand the benefits of “logic gates” vs.
switches, we should first understand Boolean
algebra
 “Traditional” algebra
• Variable represent real numbers
• Operators operate on variables, return real
numbers
 Boolean Algebra a b AND
• Variables represent 0 or 1 only 0
0
0
1
0
0
• Operators return 0 or 1 only 1 0 0
a b OR
• Basic operators
1 1 1
0 0 0
0 1 1
AND: a AND b returns 1 only when both a=1 and b=1 1 0 1

OR: a OR b returns 1 if either (or both) a=1 or b=1 0a NOT

1
1 1 1

NOT: NOT a returns the opposite of a (1 if a=0, 0 if a=1)

1 0

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Boolean Algebra and its Relation to Digital

Circuits
 Developed mid-1800’s by George Boole to formalize human thought
• Ex: “I’ll go to lunch if Mary goes OR John goes, AND Sally does not go.”
 Let F represent my going to lunch (1 means I go, 0 I don’t go)
 Likewise, m for Mary going, j for John, and s for Sally a b AND
0 0 0
 Then F = (m OR j) AND NOT(s) 0 1 0
• Nice features 1 0 0
1 1 1
 Formally evaluate
• m=1, j=0, s=1 --> F = (1 OR 0) AND NOT(1) = 1 AND 0 = 0 a b OR
0 0 0
 Formally transform
0 1 1
• F = (m and NOT(s)) OR (j and NOT(s)) 1 0 1
• Looks different, but same function 1 1 1

• We’ll show transformation techniques soon

a NOT
0 1
1 0

Evaluating Boolean Equations

a
 Evaluate the Boolean equation F = (a AND b)
OR (c AND d) for the given values of
variables a, b, c, and d: a
0
b
0
AND
0

• Q1: a=1, b=1, c=1, d=0. 0

1
1
0
0
0
1 1 1
Answer: F = (1 AND 1) OR (1 AND 0) = 1 OR 0 = 1.
• Q2: a=0, b=1, c=0, d=1.
a b OR
0 0 0
0 1 1
Answer: F = (0 AND 1) OR (0 AND 1) = 0 OR 0 = 0. 1
1
0
1
1
1

• Q3: a=1, b=1, c=1, d=1. a NOT

Answer: F = (1 AND 1) OR (1 AND 1) = 1 OR 1 = 1. 01 1

0

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Converting to Boolean Equations

a
 Convert the following English
statements to a Boolean equation
• Q1. a is 1 and b is 1.
Answer: F = a AND b
• Q2. either of a or b is 1.
Answer: F = a OR b
• Q3. both a and b are not 0.
Answer:
• (a) Option 1: F = NOT(a) AND NOT(b)
• (b) Option 2: F = a OR b
• Q4. a is 1 and b is 0.
Answer: F = a AND NOT(b)

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Converting to Boolean Equations

a  Q1. A fire sprinkler system should spray water if high heat
is sensed and the system is set to enabled.
• Answer: Let Boolean variable h represent “high heat is
sensed,” e represent “enabled,” and F represent “spraying
water.” Then an equation is: F = h AND e.
 Q2. A car alarm should sound if the alarm is enabled, and
either the car is shaken or the door is opened.
• Answer: Let a represent “alarm is enabled,” s represent “car is
shaken,” d represent “door is opened,” and F represent
“alarm sounds.” Then an equation is: F = a AND (s OR d).
• (a) Alternatively, assuming that our door sensor d represents
“door is closed” instead of open (meaning d=1 when the door
is closed, 0 when open), we obtain the following equation: F =
a AND (s OR NOT(d)).

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Relating Boolean Algebra to Digital

Design NOT OR AND
Boolean Boole’s intent: formalize x x
algebra human thought Symbol x F F F
y y
(mid-1800s)
x F x y F x y F
Switches For telephone Truth table 0 1 0 0 0 0 0 0
(1930s) switching and other 1 0 0 1 1 0 1 0
electronic uses 1 0 1 1 0 0
1 1 1 1 1 1

Showed application 1 0 0

Shannon (1938) of Boolean algebra y

x y
to design of switch-
based circuits Transistor
x F
x F
circuit F y

x y
Digital design x
0
1 1
 Implement Boolean operators using transistors
Note: These OR/AND
• Call those implementations logic gates. implementations are inefficient;
• Let’s us build circuits by doing math -- powerful we’ll show why, and show better
concept ones later.

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NOT/OR/AND Logic Gate Timing

Diagrams

1 1
1 x x
x 0 0
0 1 1
y y
1 0 0
F 1 1
0 F F
0 0
time
time time

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Building Circuits Using Gates

 Recall Chapter 1 motion-in-dark example

• Turn on lamp (F=1) when motion sensed (a=1) and no light
(b=0)
• F = a AND NOT(b)
• Build using logic gates, AND and NOT, as shown
• We just built our first digital circuit!

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Example: Converting a Boolean Equation

to a Circuit of Logic Gates
 Q: Convert the following equation to logic gates:
F = a AND NOT( b OR NOT(c) )
a
F

(a)
a

a
b F
c
(b)

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Example: Seat Belt Warning Light System

 Design circuit for warning light
 Sensors
• s=1: seat belt fastened
• k=1: key inserted
• p=1: person in seat
 Capture Boolean equation
• person in seat, and seat belt not
fastened, and key inserted w = p AND NOT(s) AND k
 Convert equation to circuit
 Notice k BeltWarn
• Boolean algebra enables easy capture as
equation and conversion to circuit p w
 How design with switches?
 Of course, logic gates are built from
switches, but we think at level of logic s
gates, not switches

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Some Circuit Drawing Conventions

no yes
x
F
y

no yes

ok

not ok

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2.5

Boolean Algebra
 By defining logic gates based on Boolean algebra, we can use algebraic methods
to manipulate circuits
• So let’s learn some Boolean algebraic methods
 Start with notation: Writing a AND b, a OR b, and NOT(a) is cumbersome
• Use symbols: a * b, a + b, and a’ (in fact, a * b can be just ab).
 Original: w = (p AND NOT(s) AND k) OR t
 New: w = ps’k + t
• Spoken as “w equals p and s prime and k, or t”
• Or even just “w equals p s prime k, or t”
• s’ known as “complement of s”
 While symbols come from regular algebra, don’t say “times” or “plus”
Boolean algebra precedence, highest precedence first.
Symbol Name Description
() Parentheses Evaluate expressions nested in parentheses first
’ NOT Evaluate from left to right
* AND Evaluate from left to right
+ OR Evaluate from left to right

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Boolean Algebra Operator Precendence

 Evaluate the following Boolean equations, assuming a=1, b=1, c=0, d=1.
• Q1. F = a * b + c.
 Answer: * has precedence over +, so we evaluate the equation as F = (1 *1) + 0 = (1) + 0 =
1 + 0 = 1.
• Q2. F = ab + c.
 Answer: the problem is identical to the previous problem, using the shorthand notation
for *.
• Q3. F = ab’.
a
 Answer: we first evaluate b’ because NOT has precedence over AND, resulting in F = 1 *
(1’) = 1 * (0) = 1 * 0 = 0.
• Q4. F = (ac)’.
 Answer: we first evaluate what is inside the parentheses, then we NOT the result, yielding
(1*0)’ = (0)’ = 0’ = 1.
• Q5. F = (a + b’) * c + d’.
 Answer: Inside left parentheses: (1 + (1’)) = (1 + (0)) = (1 + 0) = 1. Next, * has precedence
over +, yielding (1 * 0) + 1’ = (0) + 1’. The NOT has precedence over the OR, giving (0) + (1’)
= (0) + (0) = 0 + 0 = 0.

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Boolean Algebra Terminology

 Example equation: F(a,b,c) = a’bc + abc’ + ab + c
 Variable
• Represents a value (0 or 1)
• Three variables: a, b, and c
 Literal
• Appearance of a variable, in true or complemented form
• Nine literals: a’, b, c, a, b, c’, a, b, and c
 Product term
• Product of literals
• Four product terms: a’bc, abc’, ab, c
 Sum-of-products
• Equation written as OR of product terms only
• Above equation is in sum-of-products form. “F = (a+b)c + d” is not.

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Boolean Algebra Properties

• Commutative Example uses of the properties
• a+b=b+a
• a*b=b*a • Show abc’ equivalent to c’ba.
• Use commutative property:
• Distributive
• a*b*c’ = a*c’*b = c’*a*b = c’*b*a = c’ba.
• a * (b + c) = a * b + a * c
• a + (b * c) = (a + b) * (a + c) • Show abc + abc’ = ab.
• (this one is tricky!) • Use first distributive property
• abc + abc’ = ab(c+c’).
• Associative • Complement property
• (a + b) + c = a + (b + c) • Replace c+c’ by 1: ab(c+c’) = ab(1).
• (a * b) * c = a * (b * c) • Identity property
• Identity • ab(1) = ab*1 = ab.
• 0+a=a+0=a • Show x + x’z equivalent to x + z.
• 1*a=a*1=a • Second distributive property
• Complement • Replace x+x’z by (x+x’)*(x+z).
• a + a’ = 1 • Complement property
• Replace (x+x’) by 1,
• a * a’ = 0
• Identity property
• To prove, just evaluate all possibilities • replace 1*(x+z) by x+z.

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Example that Applies Boolean Algebra

• WantProperties
automatic door opener circuit
(e.g., for grocery store)
• Found inexpensive chip that
computes:
• Output: f=1 opens door • f = c’hp + c’hp’ + c’h’p
• Inputs: • Can we use it?
• p=1: person detected • Is it the same as f = c’(p+h)?
• h=1: switch forcing hold open • Use Boolean algebra:
• c=1: key forcing closed
• Want open door when
• h=1 and c=0, or f = c’hp + c’hp’ + c’h’p
• h=0 and p=1 and c=0
f = c’h(p + p’) + c’h’p (by the distributive property)
• Equation: f = hc’ + h’pc’
f = c’h(1) + c’h’p (by the complement property)
DoorOpener f = c’h + c’h’p (by the identity property)
h
f
c f = hc’ + h’pc’ (by the commutative property)
p
Same!

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Boolean Algebra: Additional Properties

 Null elements Aircraft lavatory sign example
• a+1=1 • Behavior • Alternative: Instead of
• a*0=0 • Three lavatories, each with lighting “Available,”
sensor (a, b, c), equals 1 if light “Occupied”
 Idempotent Law door locked
– Opposite of
• a+a=a • Light “Available” sign (S) if “Available” function S
any lavatory available
• a*a=a = a’ + b’ + c’
• Equation and circuit
 Involution Law – So S’ = (a’ + b’ + c’)’
• S = a’ + b’ + c’
• S’ = (a’)’ * (b’)’ * (c’)’
• (a’)’ = a • Transform (by DeMorgan’s
 DeMorgan’s Law • (abc)’ = a’+b’+c’ (by Law)
DeMorgan’s Law) • S’ = a * b * c (by
• (a + b)’ = a’b’
• S = (abc)’ Involution Law)
• (ab)’ = a’ + b’
• New equation and circuit – Makes intuitive sense
• Very useful!
• Occupied if all doors
 To prove, just Circuit are locked
evaluate all a Circuit
possibilities S
a
b
S
b
c
c

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2.6

Representations of Boolean Functions

English 1: F outputs 1 when a is 0 and b is 0, or when a is 0 and b is 1.
English 2: F outputs 1 when a is 0, regardless of b’s value
(a)
a
a b F
b
0 0 1
Equation 1: F(a,b) = a’b’ + a’b F
0 1 1
Equation 2: F(a,b) = a’
1 0 0
(b) (c)
1 1 0
Circuit 1
Truth table
a F (d)
Circuit 2

The function F

 A function can be represented in different ways

• Above shows seven representations of the same functions F(a,b), using four
different methods: English, Equation, Circuit, and Truth Table

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Truth Table Representation of Boolean

Functions
 Define value of F for each a
0
b
0
F a
0
b
0
c
0
F a
0
b
0
c
0
d
0
F

possible combination of 0 1 0 0 1 0 0 0 1

input values 1
1
0
1
0
0
1
1
0
1
0
0
0
0
1
1
0
1
• 2-input function: 4 rows (a) 1 0 0 0 1 0 0
1 0 1 0 1 0 1
• 3-input function: 8 rows 1 1 0 0 1 1 0
• 4-input function: 16 1 1 1 0
1
1
0
1
0
1
0
rows (b)
1 0 0 1
1 0 1 0
 Q: Use truth table to a
0
b
0
c
0
F
0 1 0 1 1
define function F(a,b,c) 0 0 1 0 1
1
1
1
0
0
0
1
that is 1 when abc is 5 or a 0
0
1
1
0
1
0
0 1 1 1 0
greater in binary 1 0 0 0 1 1 1 1
1 0 1 1 (c)
1 1 0 1
1 1 1 1

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Converting among Representations

 Can convert from any representation to any Inputs Outputs Term
other a b F F = sum of
0 0 1 a’b’
 Common conversions 0 1 1 a’b
• Equation to circuit (we did this earlier) 1 0 0
• Truth table to equation (which we can 1 1 0
convert to circuit)
 Easy -- just OR each input term that should F = a’b’ + a’b
output 1
• Equation to truth table Q: Convert to equation
 Easy -- just evaluate equation for each input
combination (row) a b c F
0 0 0 0
 Creating intermediate columns helps
0 0 1 0
0 1 0 0
0 1 1 0
Q: Convert to truth table: F = a’b’ + a’b 1 0 0 0
Inputs Output 1 0 1 1 ab’c
a b a' b' a' b F
1 1 0 1 abc’
a
0 0 1 0 1
1 1 1 1 abc a

0 1 0 1 1 F = ab’c + abc’ + abc

1 0 0 0 0
1 1 0 0 0

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Standard Representation: Truth Table

 How can we determine if two f = c’hp + c’hp’ + c’h’
functions are the same?
f = c’h(p + p’) + c’h’p
• Recall automatic door example
 Same as f = hc’ + h’pc’? f = c’h(1) + c’h’p
 Used algebraic methods f = c’h + c’h’p
 But if we failed, does that prove (what if we stopped here?)
not equal? No.
f = hc’ + h’pc’
 Solution: Convert to truth tables
• Only ONE truth table representation
of a given function Q: Determine if F=ab+a’ is same
 Standard representation -- for function as F=a’b’+a’b+ab, by converting
given function, only one version in each to truth table first
standard form exists
F = ab + a' F = a’b’ +
a’b + ab
a b F a b F
0 0 1 0 0 1 a

0 1 1 0 1 1
1 0 0 1 0 0
1 1 1 1 1 1

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Canonical Form -- Sum of Minterms

 Truth tables too big for numerous inputs
 Use standard form of equation instead
• Known as canonical form
• Regular algebra: group terms of polynomial by power
ax2 + bx + c (3x2 + 4x + 2x2 + 3 + 1 --> 5x2 + 4x + 4)
• Boolean algebra: create sum of minterms
Minterm: product term with every function literal appearing
exactly once, in true or complemented form
Just multiply-out equation until sum of product terms
Then expand each term until all terms are minterms
Q: Determine if F(a,b)=ab+a’ is same function as F(a,b)=a’b’+a’b+ab, by
converting first equation to canonical form (second already in canonical
form)
F = ab+a’ (already sum of products)
a F = ab + a’(b+b’) (expanding term)
F = ab + a’b + a’b’ (SAME -- same three terms as other equation)

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Multiple-Output Circuits
 Many circuits have more than one output
 Can give each a separate circuit, or can share gates
 Ex: F = ab a+ c’, G = ab + bc a
b
b
F
F
c
c

G
G

(b)
(a)

Option 1: Separate circuits Option 2: Shared gates

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Multiple-Output Example:
BCD to 7-Segment Converter

a
f
b
g
e
c
d

abcdefg = 1111110 0110000 1101101

(a) (b)

a = w’x’y’z’ + w’x’yz’ + w’x’yz + w’xy’z +

w’xyz’ + w’xyz + wx’y’z’ + wx’y’z

b = w’x’y’z’ + w’x’y’z + w’x’yz’ + w’x’yz +

w’xy’z’ + w’xyz + wx’y’z’ + wx’y’z

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2.7

Combinational Logic Design Process

Step Description

Step 1 Capture the Create a truth table or equations, whichever is

function most natural for the given problem, to describe
the desired behavior of the combinational logic.
Step 2 Convert to This step is only necessary if you captured the
equations function using a truth table instead of equations.
Create an equation for each output by ORing all the
minterms for that output. Simplify the equations if
desired.
Step 3 Implement For each output, create a circuit corresponding
as a gate- to the output’s equation. (Sharing gates among
based multiple outputs is OK optionally.)
circuit

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Example: Three 1s Detector

 Problem: Detect three consecutive 1s in 8-
bit input: abcdefgh
 00011101  1 10101011  0
11110000  1
• Step 1: Capture the function
 Truth table or equation?
• Truth table too big: 2^8=256 rows a
a • Equation: create terms for each possible
case of three consecutive 1s a abc
b
 y = abc + bcd + cde + def + efg + fgh c
• Step 2: Convert to equation -- already done bcd
d
• Step 3: Implement as a gate-based circuit
cde
e y
def
f
efg
g
fgh
h

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Example: Number of 1s Count

 Problem: Output in binary on
two outputs yz the number
of 1s on three inputs
010  01 101  10 000 
00
• Step 1: Capture the function
Truth table or equation?
• Truth table is straightforward
• Step 2: Convert to equation a
b
y = a’bc + ab’c + abc’ + abc a
b
c

z = a’b’c + a’bc’ + ab’c’ + abc c a

b
c
• Step 3: Implement as a gate- a
b
c
y
a
z

based circuit a
b
c
b a
b
c

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2.8

More Gates 1 1
NAND NOR XOR XNOR NAND NOR
x x x
F F x y
y y
F y
x y F x y F x y F x y F x F
0 0 1 0 0 1 0 0 0 0 0 1
0 1 1 0 1 0 0 1 1 0 1 0 x y
y
1 0 1 1 0 0 1 0 1 1 0 0
1 1 0 1 1 0 1 1 0 1 1 1 0 0

 NAND: Opposite of AND (“NOT AND”) • NAND same as AND with power &
 NOR: Opposite of OR (“NOT OR”) ground switched
 XOR: Exactly 1 input is 1, for 2-input XOR. • Why? nMOS conducts 0s well, but not
(For more inputs -- odd number of 1s) 1s (reasons beyond our scope) -- so
NAND more efficient
 XNOR: Opposite of XOR (“NOT XOR”)
• Likewise, NOR same as OR with
power/ground switched
• AND in CMOS: NAND with NOT
• OR in CMOS: NOR with NOT
• So NAND/NOR more common
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More Gates: Example Uses

 Aircraft lavatory sign Circuit

example a
b
c
S

• S = (abc)’
 Detecting all 0s 00 1 a0
0
• Use NOR b0

 Detecting equality a1
b1
A=B

• Use XNOR a2

 Detecting odd # of 1s b2

• Use XOR
• Useful for generating
“parity” bit common for
detecting errors

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Completeness of NAND
 Any Boolean function can be implemented using just NAND
gates. Why?
• Need AND, OR, and NOT
• NOT: 1-input NAND (or 2-input NAND with inputs tied together)
• AND: NAND followed by NOT
• OR: NAND preceded by NOTs
 Likewise for NOR

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Number of Possible Boolean Functions

 How many possible functions of 2 variables?
• 22 rows in truth table, 2 choices for each a b F
2
• 2(2 ) = 24 = 16 possible functions
0 0 0 or 1 2 choices
 N variables
• 2N rows
0 1 0 or 1 2 choices
•
N
2(2 ) possible functions 1 0 0 or 1 2 choices
1 1 0 or 1 2 choices

24 = 16
possible functions

a b f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15

0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
a NAND b
a XNOR b
a

1
a NOR b
0

a AND b

a OR b
a XOR b

b’

a’

0 a b 'b 'a 1
OR
X b
a AND b a a ORa bNOR b
a XNOR b a NAND b

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2.9

Decoders and Muxes

 Decoder: Popular combinational logic
building block, in addition to logic
gates d0 1 d0 0 d0 0 d0 0
• Converts input binary number to one 0 i0 d1 0 1 i0 d1 1 0 i0 d1 0 1 i0 d1 0
high output 0 i1 d2 0 0 i1 d2 0 1 i1 d2 1 1 i1 d2 0

 2-input decoder: four possible input d3 0 d3 0 d3 0 d3 1

binary numbers
• So has four outputs, one for each
possible input binary number i1’i0’ d0 d0 0
1 i0 d1 0
 Internal design
i1’i0 d1 1 i1 d2 0
• AND gate for each output to detect
input combination e d3 1
i1i0’ d2
1
 Decoder with enable e
• Outputs all 0 if e=0 i1i0 d3 d0 0
• Regular behavior if e=1 1 i0 d1 0
1 i1 d2 0
 n-input decoder: 2n outputs e d3 0
i1 i0
0

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Decoder Example
 New Year’s Eve 210 21 0 0
Happy
New Year
0 1 0 0 0 1
Countdown Display 1 0 0
i0
i1
d0
d1 0 1 0 1
0 0 0 i2 d2 1 0 0
• Microprocessor
2
0 0 0 i3 d3 0 0 0 3
cessor
a

counts from 59 r 000

o
op0 0 0
ric
i4
i5

down to 0 in binary M e
d58
d59
0 0 0
0 0 0
on 6-bit output d60
d61 58

• Want illuminate one 6x64

dcd
d62
d63
59

of 60 lights for each

binary number
• Use 6x64 decoder
4 outputs unused

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Multiplexor (Mux)
 Mux: Another popular combinational building block
• Routes one of its N data inputs to its one output, based
on binary value of select inputs
4 input mux  needs 2 select inputs to indicate which input to
route through
8 input mux  3 select inputs
N inputs  log2(N) selects
• Like a railyard switch

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Mux Internal Design

i0 i0 (1*i0=i0)
2×1 2×1 2×1 d
1 i0
i0 i0 i0 i1
d d d 0 (0+i0=i0)
i1 i1 i1
0
s0 s0 s0
a
0 1
2x1 mux 0 s0

i0
4 1
i0 i1
i1 d
d
i2 i2
i3
s1 s0 i3

4x1 mux

s1 s0

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Mux Example
 City mayor can set four switches up or down,
representing his/her vote on each of four proposals,
numbered 0, 1, 2, 3
 City manager can display any such vote on large
green/red LED (light) by setting two switches to
represent binary 0, 1,switches
Mayor’s 2, or 3
 Use 4x1 mux 1
4x1 on/off
i0
2 i1
d
i2
i3 Green/
rP 3 Red
s1 s0
LED

4
manager's
switches

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Muxes Commonly Together -- N-bit Mux

2 1
a3 i0 Simplifying
d
b3 i1 notation:
s0
4-bit 4
2 1 4 C
a2 i0 2x1
d A I0 4
b2 i1 D C is short
s0 4
B I1 for
2 1
a1 i0 s0
d
b1 i1 c3
s0
s0 c2
2 1
a0 i0
d c1
b0 i1
s0
s0 c0

 Ex: Two 4-bit inputs, A (a3 a2 a1 a0), and B (b3 b2 b1

b0)
• 4-bit 2x1 mux (just four 2x1 muxes sharing a select line)
can select between A or B

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N-bit Mux Example

 Four possible display items

• Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles
remaining (M) -- each is 8-bits wide
• Choose which to display using two inputs x and y
• Use 8-bit 4x1 mux

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2.10
Additional Considerations
Schematic Capture and Simulation
Inputs Inputs
i0 i0
i1 i1
Simulate Simulate
Outputs Outputs
d3 d3

d2 d2

d1 d1

d0 d0

 Schematic capture
• Computer tool for user to capture logic circuit graphically
 Simulator
• Computer tool to show what circuit outputs would be for given inputs
 Outputs commonly displayed as waveform

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Additional Considerations
Non-Ideal Gate Behavior -- Delay

 Real gates have some delay

• Outputs don’t change immediately after inputs change

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Chapter Summary
 Combinational circuits
• Circuit whose outputs are function of present inputs
 No “state”
 Switches: Basic component in digital circuits
 Boolean logic gates: AND, OR, NOT -- Better building block than switches
• Enables use of Boolean algebra to design circuits
 Boolean algebra: uses true/false variables/operators
 Representations of Boolean functions: Can translate among
 Combinational design process: Translate from equation (or table) to circuit through well-defined
steps
 More gates: NAND, NOR, XOR, XNOR also useful
 Muxes and decoders: Additional useful combinational building blocks

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Q&A

January 5, 2025

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