UNIT – III

ACTUATION SYSTEM and INPUT/OUTPUT SYSTEMS

Actuation systems: Introduction – type of motion – freedom and constrains. Kinematic

chain – the four – bar chain – the slider crank mechanism, mechanical aspects of motor

selection. Electrical actuation systems - Introduction – Mechanical switches – relays,

solid – state switches – diodes, thyristors and triacs, bipolar transistors, solinoids.

Interfacing: Input/output ports – Interface requirements: buffers, handshaking, poling

and interrupts, serial interfacing – introduction to PIA – serial communications interface

– example of interfacing of a seven – segment display with a decoder..

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TYPES OF MOTION

The motion of any rigid body can be considered to be a combination of translational and
rotational motions. By considering the three dimensions of space, a translation motion can be
considered to be a movement which can be resolved into components along one or more of three
axes (fig.3.1 (a)).

A rotation can be considered as a rotation which has components rotating about one or more of
the axes (fig.3.1 (b)).

Fig.3.1 TYPES OF MOTION(a) translation motions (b) rotational motion

FREEDOM AND CONSTRAINTS

A body that is free in space can move in three, independent, mutually perpendicular directions
and rotate in three ways about those directions (fig.3.1).The number of degrees of freedom is the
number of components of motion that are required in order to generate the motion. Redundant
constraints often occur and so for constraints on a single rigid body we have the basic rule.

6- Number of constraints = number of degree of freedom – number of redundancies.

PRINCIPLE OF LEAST CONSTRAIN

It states that in fixing a body or guiding it to a particular type of motion, the minimum no. of
constaints should be used.

For example: to have a shaft which only rotates about one axis with no translations motion. The
shaft has a ball bearing at one end and a roller bearing at the other end.(fig 3.2) The pair of
bearing together prevents translation motion at right angles to the shaft, the y-axis, and
rotational about the z-axis &y-axis. The ball bearing prevents translational motion along the x-
axis and along the z-axis. Thus there is total of five constrains. This leaves just one degree of
freedom, the required rotational about the x-axis. If there had been a roller bearing at each end
of the shaft then both the bearings could have prevented translational motion along the x-axis
and the z-axis and thus there would have been redundancy. Such redundancy may cause
damage. If ball bearings are used at both ends of the shafts, then in order to prevent redundancy

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one of the bearings would have its outer race not fixed in its housing so that it could slide to
some extent it an axial direction.

Fig 3.2 Shaft with no redundancies

KINEMATIC CHAINS
Each part of a mechanism which has motion relatively to some other part is termed as link. A
link need not necessarily be a rigid body but it must be a resistant body, which is capable of
transmitting the required force with negligible deformation. For this reason, it is usually taken as
being represented by a rigid body which has two (or) more points of attachments to other links,
these being termed as nodes.(Fig 3.3) Ajoint is a connection between the connected links at
their nodes and allows some motion between the connected links. A sequence of joints and links
is known as kinematic chain. For a kinematic chain to transmit motion, one link must be fixed.
Movement of one link will then produce predictable relative movements of others.

Fig 3.3 Links (a) with two nodes,(b) with three nodes,(c) with four nodes

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THE FOUR BAR CHAIN
It consists of four links connected to give four joints about which turning can occur (Fig 3.4).If
the sum of the length of the shortest link plus the length of the longest link is less than (or)
equal to the sum of the length of the other two links then at least one link will be capable of
making a full revolution with respect to fixed link.If this condition is not met then no link is
capable of a complete revolution this is known as Grashof condition.In Fig 3.4(a), link 3 is fixed
and the relative lengths of the links are such that links 1 and 4 can oscillate but not rotate. The
result is double lever mechanism.By shortening link 4 relatively to link 1, then link 4 can
rotate (Fig 3.4(b)) with link 1 oscillating. It is called lever-crank mechanism.With the link 1 and
4 the same length and both able to rotate(Fig 3.4(c)). It is called double-crank mechanism.

Fig 3.4 Examples of four bar chain

In the Fig 3.5, As link 1 rotates so the end of the link 2 locks into a sprocket of the film, pulls it
forward before releasing and moving up and back to lock into the next sprocket.

Fig 3.5 Cine film advance mechanism

Some linkages may have toggle position. Fig 3.6 illustrates such a toggle being linkages used to
control the movements of the tailgate of the truck, so that when link 2 reaches the horizontal
position no further load on link 2 will cause any further movements. There is another toggle
position for the linkage and that is when links 3 and 4 are both vertical and the tailgate is
vertical.

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 Fig 3.6 Toggle linkage

SLIDER CRANK MECHANISM

This form of mechanism consists of crank, a connecting rod and a slider and is the type of
mechanism is described in Fig 3.7.
With that configuration, link 3 is fixed. Link 1 is the crank that rotates, link 2 the connecting rod
and link 4 the slider which moves relative to the fixed link.
When the piston moves up and down, then the crank is forced to rotate. Hence the mechanism
transforms an input of up & down motion into rotational motion.

Fig. 3.7 Simple engine mechanism

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The Fig 3.8 represents the quick return mechanism. It consists of rotating crank, link AB,
which rotates round a fixed center, an oscillating lever CD, which is caused to oscillate about C,
by the sliding of the block at B along CD as AB rotates, and a link DE which causes E to move
backwards and forwards. E might be the ram of a machine and have a cutting tool attached to it.
The ram will be at the extremes of its movement when the positions of the crank are AB1 and
AB2.Thus as the crank moves anti-clockwise from B1 to B2, the ram makes a complete stroke,
the cutting stroke.When the crank continuous its movement from B2 anticlockwise to B1, then
the ram again makes a complete stroke in the opposite direction, the return stroke. With the
crank rotating at constant speed, then, because the angle of crank rotation required for the
cutting stroke is greater than the angle for the return stroke, the cutting stroke takes more times
than the return stroke.Hence the term quick-return for the mechanism.

Fig 3.8 Quick return mechanism

MECHANICAL ASPECTS OF MOTOR SELECTION:

A motor drive system is mechanically required to rotate a shaft and its

attached load. Factors that have to be considered are moments of inertia and torque.

1. MOMENTS OF INERTIA :

The torque required to give a load with moment of inertia ILan angular acceleration α
is IL .α. The torque required to accelerate the motor shaft isTM =IM .αM and that required to
accelerate the load isTL =IL .αL . The motor shaft will, in the absence of gearing, have the same
angular acceleration and same angular velocity. The power needed to accelerate the system as a
whole is TM ω + TL ω, thus

Power = (IM + IL)αω

This power is produced by the motor torque and thus the power must equal. Hence

T = (IM + IL) α

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The torque to obtain a given angular acceleration will be minimized whenIM = IL. Thus, the
optimum performance, the moment of inertia of the load should be similar to that of the motor.

2. TORQUE:

For continuous running the stall torque value should not be exceeded. This is the maximum
torque value at which overheating will not occur. For intermittent use, greater torques is possible.
As the angular speed is increased so the ability of the motor to deliver torque diminishes. Thus if
higher speeds and torques are required then given by a particular motor, a more powerful motor
needs to be selected. Fig 3.8(a) shows the operating curves for a typical motor.

Fig 3.8 a
Torque vs Speed curve

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ELECTRICAL ACTUATION SYSTEMS
Electrical actuation systems have three types. They are,
 Switching devices such as mechanical switches and solid state switches.
 Solenoid type devices
 Drive systems like D.C motors and A.C motors.

MECHANICAL SWITCHES

RELAYS
Relays are electrically operated switches in which changing a current in one electric circuit
switches a current on or off in another circuit. For the relay shown in Fig 3.9(a), when there is a
current through the solenoid of the relay , a magnetic field is produced which attracts the iron
armature moves the push rod, and so closes the normally open switch contacts and opens the
normally closed switch contacts.

Fig 3.9 (a) A relay and (b) a driver circuit

Relays are often used in control systems. The output from a controller is relatively small current
and so it is often used in conjunction with a transistor to switch on the current through the
relay solenoid and hence use the relay to switch on the much larger current needed to switch on
or off a final correction element such as an electric heater in a temperature control system or a
motor. Fig 3.9(b) shows the type of circuit that might be used. Because relays are inductances,
they can generate a back voltage when the energizing current is switched off or when their input
switches from a high to low signal.
As a result, damage can occur in the connecting circuit.

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Fig 3.10 shows how two relays might be used to control the operation of pneumatic valves which
in turn control the movement of pistons in three cylinders A, B and C.The sequence of operation
is:
 When the start switch is closed,current is applied to the A and B solenoids and results in
both A and B extending, i.e. A+ and B+.
 The limit switches a+ and b+ are then closed ; the a+ closure results in a currents flowing
through relay coil 1 which then closes its contacts and so supplies current to the C
solenoid and results in it extending, i.e. C+.
 Its extension causes limit switch c+ to close and so current to switch the A and B control
valves and hence retraction of cylinders A and B, i.e.A- and B-.
 Closing limit switch a- passes a current through relay coil 2; its contacts close and allow a
current to valve C and cylinder C to retract, i.e. C-.

Fig 3.10 Relay-controlled system

The sequence thus given by this system is A+ and B+ concurrently, then C+ followed by A- and
B- concurrently and finally C-.

SOLID STATE SWITCHES

DIODES
It only passes a current when forward biased. If an alternating current is applied across a diode,
it can be regarded as only switching on when the direction of the voltage is such as to forward-
bias it and being off in the reverse-biased direction. The result is that the current through the
diode is half-rectified to become just the current due to the positive halves of the input voltage

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 Fig 3.11(a) Diode characteristic(b) Half-wave rectification

THYRISTORS AND TRIACS

The thyristor, or silicon-controlled rectifier (SCR), can be regarded as a diode which has a
gate controlling the condition under which the diode can be switched on.
When forward biased the current is also negligible current when reverse down voltage is
exceeded. When this occurs the voltage across the diode falls to a low level, about 1 to 2V and
the current is then only limited by the external resistance in a circuit. Once switched on, the
thyristor remains on until the forward current is reduced to below a level of a few milliamps. The
voltage at which forward break down occurs is determined at the current entering gate.

Fig 3.12 (a) Thyristor characteristics (b) Thyristor circuit

The triac is similar to the thyristor and is equivalent to a pair of thyristor connected in reverse
parallel on the same chip. The triac can be turned on in either the forward (or) reverse direction.

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 Fig 3.13 Voltage control (a) Thyristor (b) Triac

In this thethyristor is operated as a switch by using the gate to switch the device on (or) off. By
using an alternating signal to the gate, the supply voltage can be chopped and an intermittent
voltage produced.

BIPOLAR TRANSISTORS

Bipolar transistors come in two forms, the npn and the pnp. For the npn transistor, the main
current flows in at the collector and out at the emitter, a controlling signal being applied to the
base.The pnp transistor has the main current flowing in at the emitter and out the collector. For
an npn transistor connected as shown in Fig 3.14(b), the so-termed common emitter circuit, the
relationship between the collector current Ic and the potential difference between the collector
and emitter VCE is described. When the base current IB is zero, the transistor is cut of; in this
state both the base-emitter and the base-collector junctions are reverse biased. When the base
current is increased, the collector current increases and VCE decreases. Thecollector current can
increase no further, even if the base current is further increased, this is termed saturation.

Fig 3.14Transistor switch

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SOLENOIDS

Solenoids can be used to provide electrically operated actuators. When a current passes through
a coil a soft iron core is pulled into the coil and in doing so, can open (or) close ports to allow the
flow of a fluid. The force exerted by the solenoid on the core is a function of the current in the
coil and the length of core that is within the coil. With On/off valves, the current in the coil is
controlled to be either on (or) off and the core consequently in one of two position. With
proportional control valves, the current in the coil is controlled to give a core movement which is
proportional to the size of the current.

Fig 3.15 Single-solenoid valve

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INTERFACE REQUIREMENTS

The following are some of the actions that are often required of an interface circuit:

1. ELECTRICAL BUFFERING / ISOLATION

This is needed when the peripheral operates at a different voltages or current to that on the
microprocessor bus system or there are different ground references. The term buffers is used for
a device that provides isolation and current or voltage amplification. For example, if the
output of a microprocessor is connected to the base of transistor , the base current required
to switch the transistor is greater than supplied by the microprocessor and so a buffer is
used to step up the current . There also has often to be isolation between the
microprocessor and the higher power system.

2. TIMING CONTROL

Timing control is needed when the data transfer rates of the peripheral and the
microprocessor are different, e.g. when interfacing a microprocessor to a slower peripheral.
This can be achieved by using special lines between microproccesor and the peripheral to
control the timing of data transfers. Such lines are referred to as handshake lines and
the process as handshaking

3. CODE CONVERSION

This is needed when the codes used by the peripherals differ from those used by
microprocessor. For example, an LED display might require a decoder to convert the bcd
output from the microprocessor into the code required to operate the seven display
elements

4. CHANGING THE NUMBER OF LINES

Microprocessors operate on a fixed word length of 4 bits, 8 bits or 16 bits. This

determines the number of lines in the microprocessor data bus. Peripheral equipment
may have a different number of lines, perhaps requiring a longer word than that of the
microprocessor.

5. SERIAL–TO–PARALLEL, AND VICE VERSA, DATA TRANSFER

Within an 8 – bit microprocessor , data is generally manipulated 8 bits at a time. To transfer

8 bits simultaneously to a peripheral thus requires eight data paths. Such a form
transfer is termed parallel data transfer. It is, however not always possible to transfer
data in this way. For example, data transfer over the public telephone system can only
involve one data path. The data has thus to be transferred sequentially 1 bit at a time.
Such a form of transfer is termed serial data transfer. Serial data transfer is a slower
method of data transfer than paralleldata transfer. Thus, if serial data into parallel data for
the microprocessor and vice versa for outputs from the microprocessor

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 6. CONVERSION FROM ANALOGUE TO DIGITAL AND VICE VERSA

The output from the sensors is generally analogue and this requires conversion to digital
signals for the microprocessor. The output from a microprocessor is digital and this might
require conversion to an analogue signal in order to operate some actuator. Many
microcontrollers have built – in analogue - to - digital converters , e.g. PIC 16C74/74A AND
MOTOROLA M68HC11 , so can handle analogue inputs. However, where required to give
analogue outputs, the microcontroller output has generally to pass through an external
digital – to – analogue converter

BUFFERS

A buffer is a device that is connected between two parts of a system to prevent unwanted
interface between two parts. An important use of a buffer is in the microprocessor input port to
isolate the input data from the microprocessor data bus until the microprocessor requests it. The
commonly used buffer is a tristate buffer. The tristate buffer is enabled by a control signal to
provide logic 0 or 1 outputs , when not enabled it has a high impendance and so effectively
disconnects circuits.Figure 3.1.1(a) and (b) shows the symbol for buffers that does not change the logic of
the input and Figure 3.1.1(c) and (d)

With PIC microcontrollers , the TRIS bit is connected to the enable input of a tristate buffer. If
the bit is 0 , the tristate buffer is enabled and simply passes its input value to its output , if it
is 1 the tristate buffers is disabled and the output becomes high impendence as in Figure 3.1.1 (b)

Figure 3.1.1

Buffers (a) no logic change, enabled by 1,(b) no logic change, enabled by 0,

(c) logic change, enabled by 1, (d) logic change, enabled by 0.

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Such tristate buffers are used when a number of peripheral devices have to share the same data
lines from the microprocessor, i.e. they are connected to the data bus, and thus there is a need
for the microprocessor to be able to enable just one of the devices at a time with the others
disabled Figure 3.1.2 shows how such buffers can be used such buffers are available as integrated
circuits, e.g. the 7412 with four non – inverting, active - low buffers and the 74126 with four non –
inverting , active - high buffers

Figure 3.1.2 Three state buffers

HANDSHAKING

Unless two devices can send and receive data at identical rates, handshaking is necessary to
exchange data. With handshaking the slower device controls the rate at which the data is
transferred. For parallel data transfer strobe – and – acknowledge isthe commonly used form of
handshaking. The peripheral sends a DATA READY signal to the input / output section. The
CPUthen determines that the DATA READY signal is active. The CPU then reads the data from
the input/ output section and sends an INPUT ACKNOWLEDGED signal to the peripheral. This
signal indicates that the transfer has been completed and thus the peripheral can send more
data. For an output, the peripheral sends an OUTPUT REQUEST or PERIPHERAL READY signal
to the input/output section. The CPU determines that the PERIPHERAL READY signal is active
and sends the data to the peripheral. The next PERIPHERAL READY signal may be used to
inform the CPU that the transfer has been completed.

With the microcontroller MC86HC11, the basic strobed input/output o)perates as follows.
The handshaking control signals use pins STRA and STRB(Fig.5.3) , port C is used for the
strobed input and port B for the strobed output. When data is ready to be sent by the
microcontroller a pulse is produced at STRA and sent to the peripheral device. When the
microcontroller receives either a rising or falling edge to a signal on STRB, then the relevant

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output port of the microcontroller sends the data to the peripheral. When data is ready to be
transmitted to the microcontroller, the peripheral sends a signal to STRA that it is ready and
then a raising or falling edge to a signal on STRB is used to indicate readiness to receive. Before
handshaking can occur, the parallel input/output register PIOC at address $1002 has to be first
configured

Figure 3.1.3 Handshaking control; strobe and acknowledge.

Full handshake input / output involves two signals being sent along STRB , the first being to
indicate ready to ready to receive data and the next one that the data has been read. This mode
of operations requires that in PIOC the HNDS bit is set to 1 and if PLS is set to 0 the full
handshake is said to be pulsed and if to 1 it is interlocked. With pulsed operation a pulsed
operation a pulse is sent as acknowledgement; with interlocked STRB there is a reset(Fig 5.4).

Figure 3.1.4 Full Handshaking (a) Pulsed (b) Interlocked

POLLING AND INTERRUPTS

Consider the situation Where all input/ output transfers of data are controlled by the program. When
peripherals need attention they signal the microprocessor by changing the voltage level of an input line.
The microprocessor can then respond by jumping to a program service routine for the device. On
completion of the routine, a return to the main program occurs. Program control of inputs/outputs is thus

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a loop to read inputs and update outputs continuously, with jumps to service routines as required. This
process of repeatedly checking each peripheral device to see if it is ready to send or accept a new byte of
data is called polling.

An alternative to program control is interrupt control. An interrupt involves a peripheral

device activating a separate interrupt request line. The reception of an interrupt results in the
microprocessor suspending execution of its main program and jumping to the service routine for the
peripheral. The interrupt must not lead to a loss of data and an interrupt handling rou-tine has to be
incorporated in the software so that the state of processor registers and the last address accessed in the
main program are stored in dedicated locations in memory. After the interrupt service routine, the
contents of the memory are restored and the microprocessor can continue executing the main program
from Where it was interrupted (Figure 3.1.5)

Figure 3.1.5 Interrupt Control

Thus, when an interrupt occurs:

1) The CPU waits until the end of the instruction it is currently executing before dealing with the interrupt.

2) All the CPU registers are pushed onto the stack and a bit set to stop further interrupts occurring during
this interruption. The stack is a special area of memory in Which program counter values can be stored
When a subroutine is to be executed. The program counter gives the address of the next program
instruction in a program and thus storing this value enables the program to be resumed at the place
Where it broke off to execute the interrupt. .

3)The CPU then determines the address of the interrupt service routine to be executed. Some
microprocessors have dedicated interrupt pins and the pin that is chosen determines which address is to
be used. Other microprocessors have only one interrupt pin and the interrupting device must then supply
data that tells the microprocessor Where the interrupt service routine is located. Some microprocessors
have both kinds of interrupt inputs. The starting address of an interrupt service routine is called an

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interrupt vector. The block of memory assigned to store the vectors is known as the vector table. Vector
addresses are fixed by the chip manufacturer.

4)The CPU branches to the interrupt service routine. .

5)After completion of this routine, the CPU registers are returned from the stack and the main program
continues from the point it left off.

SERIAL INTERFACING

With the parallel transmission of data, one line is used for each bit; serial systems, however, use a single
line to transmit data in sequential bits. There are two basic types of serial data transfer: asynchronous
and synchronous.

With asynchronous transmission, the receiver and the transmitter each use their own clock signals so it is
not possible for a receiver to know when a word starts or stops.Thus it is necessary for each transmitted
data word to carry its own start and stop bits so that it is possible for the receiver to tell Where one word
stops and another starts (Figure 3.1.6). With such a mode of transmission, the transmitter and receiver
are typically remote. With synchronous transmission, the transmitter and receiver have a common clock
signal and thus transmission and reception can be synchronised.

Figure 3.1.6 Asynchronous Transmission

PERIPHERAL INTERFACE ADAPTERS

Interfaces can be specifically designed for particular inputs/outputs; however, programmable

input/output interface devices are available which permit various different input and output options to be
selected by means of software. Such devices are known as peripheral interface adapters (PIAs).

A commonly used PIA parallel interface is the Motorola MC 6821. It is part of the MC6800 family and thus
Can be directly attached to Motorola MC6800 and MC68HC11 buses. The device can be considered to be
essentially just two parallel input/output ports, with their control logic, to link up with the host
microprocessor; Figure 3.1.7 shows the basic structure of the MC6821 PIA and the pin connections.

The PIA contains two 8-bit parallel data ports, termed A and B. Each port has:

1. A peripheral interface register.

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An output port has to operate in a different way to an input port because the data must be held for the
peripheral. Thus for output a register is used to store data temporarily. The register is said to be latched i.
e. connected, when a port is used for output and unlatched when used for input.

2. A data direction register that determines whether the input/output lines

are inputs or outputs.

3. A control register that determines the active logical connections in the peripheral.

4. Two control lines, CA1 and CA2 or CB1 and CB2.

Two microprocessor address lines connect the PIA directly through the two register select lines RS0 and
RS1. This gives the PIA four addresses for the six registers. When RS1 is low, side A is addressed and
when it is high, side B. RS0 addresses registers on a particular side, i.e. A or B. When RS0 is high, the
control register is addressed, when low the data register or the data direction register. For a particular side,
the data register and the data direction register have the same address Which of them is addressed is
determined by bit 2 of the control register (see below).

Figure 3.1.7 MC6821 PIA

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Each of the bits in the A and B control registers is concerned with some features of the operation of the
ports. Thus for the A control register we have the bits shown in Figure 3.1.8.A similar pattern is used for
the B control register.

Figure 3.1.8 Control Register

Bits 0 and 1

The first two bits control the way that CA1 or CB1 input control lines operate. Bit 0 determines whether
the interrupt output is enabled. B0 = 0 disables the IRQA(B) microprocessor interrupt, B0 = 1 enables the
interrupt. CA1 and CB1 are not set by the static level of the input but are edge triggered , i.e. set by a
changing signal. Bit 1 determines Whether bit 7 is set by a high-to-low transition (a trailing edge) or a low-
to-high transition (a leading edge). B1=0 sets a high-to-low transition, B1=1 sets a low-to-high transition.

Bit 2

Bit 2 determines whether data direction registers or peripheral data registers are addressed With B2 set to
0, data direction registers are addressed, with B2 set to 1, peripheral data registers are selected.

Bits 3, 4 and 5

These bits allow the PIA to perform a variety of functions. Bit 5 determines Whether control line 2 is an
input or an output. If bit 5 is set to 0, control line 2 is an input, if set to 1, it is an output. In input mode,
both CA2 and CB2 operate in the same way. Bits 3 and 4 determine whether the interrupt output is active
and which transitions set bit 6.

Bit 6

This is the CA2(CB2) interrupt flag, being set by transitions on CA2(CB2). With CA2(CB2) as an input (B5=
0), it is cleared by a microprocessor read of the data register A(B). With CA2(CB2) as an output (B5 = l), the
flag is 0 and is not affected by CA2(CB2) transitions.

Bit 7

This is the CA1(CBI) interrupt flag, being cleared by a microprocessor read of data register A(B).

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SERIAL COMMUNICATIONS INTERFACE

The universal asynchronous receiver/ transmitter (UART) is the essential element of a serial
communication system, the function being to change serial data to parallel for input and parallel data to
serial for output. A common programmable form of a UART is the asynchronous communications interface
adapter (ACIA) from Motorola MC6850; Figure 3.1.9 shows a block diagram of the constituent elements.

Data flow between the microprocessor and the ACIA is via eight bidirectional lines D0 to D7. The direction
of the data flow is controlled by the microprocessor through the read/write input to the ACIA. The three
chip select lines are used for addressing a particular ACIA. The register select line is used to select
particular registers Within the ACIA; if the register select line is high then the data transmit and data
receive registers are selected, if low then the control and status registers are selected. The status register
contains information on the status of serial data transfers as they occur and is used to read data carrier
detect and clear-to-send lines. The control register is initially used to reset the ACIA and subsequently to
define the serial data transfer rate and data format.

The peripheral side of the ACIA includes two serial data lines and three control lines. Data is sent by the
transmit data line and received by the receive data line. Control signals are provided by clear-to-send, data
carrier detect and request-to-send. Figure 3.1.10 shows the bit formats of the control and Figure
3.1.11.the status registers.

Asynchronous serial data transfer is generally used for communications between two computers, with or
without a modem, or a computer and a printer.

Figure 3.1.9 MC6850 ACIA

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 Figure 3.1.10 Control Register

`Figure 3.1.11 Status Register

EXAMPLES OF INTERFACING

INTERFACING A SEVEN-SEGMENT DISPLAY WITH A DECODER

Consider where the output from a microcontroller is used to drive a seven segment LED display unit. A
single LED is an on/off indicator and thus the display number indicated will depend on which LEDs are
on. Figure 3.1.12 shows how we can use a microcontroller to drive a common anode display using a
decoder driver, this being able to take in a BCD input and convert it to the appropriate code for the display.

For the 7447 decoder, pins 7, 1, 2 and 6 are the input pins of the decoder for the BCD input with pins 13,
12, 11, 10, 9, 15 and 14 being the outputs for the segments of the display. Pin 9 of the display is the
decimal point. Table 5.1 shows the input and output signals for the decoder.

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Blanking is when none of the segments are lit. This is used to prevent leading 0 occurring when we have,
say, three display units and want. to display just 10 rather than 010 and so blank out the leading 0 and
prevent it being illuminated. This is achieved by the ripple blanking input (RBI) being set low. When RBI is
low and the BCD inputs A, B, C and D are low then the output is blanked. If the input is not zero the
ripple blanking output RBO is high regardless of the RBI status. The RBO of the first digit in the display
can be connected to the RBI of the second digit and the RBO of the second connected to the RBI of the

third digit, thus allowing only the final 0 to be blanked (Figure 3.1.13).

Figure 3.1.12 Driving a Display

Table 3.1.1 The 7447 BCD decoder for a seven segment display

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 Figure 3.1.13 Ripple Blanking

With displays having many display elements, rather than use a decoder for each element, multiplexing is
used with a single decoder. Figure 3.1.14 shows the circuit for multiplexing a four-element common
cathode type of display. The BCD data is outputted from port A and the decoder presents the decoder
output to all the displays. Each display has its common cathode connected to ground through a transistor.
The display cannot light up unless the transistor is switched on by an output from port B. Thus by
switching between PBO, PB1, PB2 and PB3 the output from port A can be switched to the appropriate
display. To maintain a constant display, a display is repeatedly turned on sufficiently often for the display
to appear flicker-free.

Figure 3.1.14 Multiplexing Four Displays

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