G. Rizzoni and J.

Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Chapter 12: Digital Systems – Instructor Notes

Chapter 12 logically follows the material on combinational digital logic circuits introduced in
Chapter 11. Section 12.1 contains a discussion of sequential logic modules, starting with
latches and flip-flops and continuing in Section 12.2 with digital counters and registers; the box
Focus on Measurements: Digital Measurement of Angular Position and Velocity (pp. 712-713)
illustrates the use of a counter to measure the speed of rotation of a slotted wheel, which is a
common measurement in mechanical systems; the box Focus on Measurements: Seven-
Segment Display (p. 714) draws attention to a common logic module. Section 12.3 provides an
elementary introduction to sequential logic design and Section 12.4 introduces microcomputer
system architecture. The box Focus on Measurements: Reading Sensor Data Using Interrupts
(pp. 723-724) illustrates the utility of interrupts and how they can be implemented using a simple
flip-flop. Section 12.5 provides a broad overview of the ATmega328P microcontroller and an
introduction to the concept of mechatronic design (p. 730.) Recognizing that it is impossible to
include a serious coverage of microcontrollers in a single chapter, the treatment provides an
overview of the organization of microcontrollers. The last section, 12.6, describes the Arduino
project in brief and illustrates basic aspects of an Arduino sketch.

In recent years mechanical and industrial engineering programs have seen a significant growth
in courses related to mechatronics, or more specifically to microcontroller applications in
industrial and mechanical systems. The objective of Chapter 12 is to serve as an introduction to
such courses.

The homework problems are mostly devoted to sequential logic circuits; the last 10 problems
review simple concepts related to the architecture and functions of microcomputers.

Learning Objectives
Students will learn to…
1. Analyze the operation of flip-flops and latches. Section 12.1.
2. Analyze and apply digital counters and registers. Section 12.2.
3. Design simple sequential logic circuits using state transition diagrams. Section 12.3.
4. Describe the basic architecture of computers. Section 12.4.
5. Identify the architecture of microprocessors, microcontrollers, and the ATmega328P, in
particular. Sections 12.5.
6. Utilize the Arduino hardware and software project. Section 12.6.

12.1
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Section 12.1: Latches and Flip-Flops

Problem 12.1
The input to the circuit of Figure P12.1 is a square wave having a period of 2 s, maximum value
of 5 V, and minimum value of 0 V. Assume all flip-flops are initially in the RESET state.
a. Explain what the circuit does.
b. Sketch the timing diagram, including the input and all four outputs.

Solution:
Known quantities:
For the circuit shown in Figure P12.1, the input is a square wave having a period of 2 s,
maximum value of 5 V, and minimum value of 0 V. Assume all flip-flops are initially in the
RESET state.
Find:
a) Explain what the circuit does.
b) Sketch the timing diagram, including the input and all four outputs.
Analysis:
a) The device is called a MOD-16 ripple counter. It can count clock pulses from 0 to (24-1). The
outputs divide the frequency by 21, 22, 23, and 24 respectively. Therefore, you can use this circuit
as a divide by N counter, where N is 2, 4, 8 and 16.
b)

12.2
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.2
Suppose a circuit is constructed from three D-type flip-flops, one input I, with
D1 = Q2, D0 = Q1
( ) ( )
D2 = I ⋅ Q1 ⋅Q0 + Q1 ⋅Q0 + I ⋅ Q1 ⋅Q0 + Q 1 ⋅Q 0 = α ⊕ I
α = Q1 ⊕Q0
!

a. Draw the circuit diagram.

b. Assume the circuit starts with all flip-flops set (Q=1). Sketch a table that shows the outputs of
all three flip-flops.

Solution:
Known quantities:
Input I. Initial output state of each flip-flop is set.
Find:
The circuit diagram and state of the outputs over time.
Analysis:
a. To draw the circuit diagram simply draw lines from the outputs Q1 and Q2 to the inputs D0 and
D1, respectively. Likewise, create an exclusive OR gate with Q1 and Q0 as its inputs and a as its
output. Then create another exclusive OR gate with a and I as its inputs. The output of this
second exclusive OR gate is the input to D2. The result of this procedure is shown in the figure.

b. A table of the various outputs in response to the input I is shown here. Notice that I acts as an
enable input.

12.3
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

CLK I Q0 Q1 Q2
L L H H H
H L H H H
L H H H H
H H H H L
L H H H L
H H H L H
L H H L H
H H L H H
L H L H H
H H H H L

Problem 12.3
Suppose that you want to use a JK flip-flop for a laboratory experiment. However, you have only
D flip-flops. Assuming that you have all the logic gates available, make a JK flip-flop using a D
flip-flop and some logic gate.

Solution: J K Qn Qn+1 D
Known quantities: 0 0 0 0 0
0 0 1 1 1
The truth tables for JK and D flip-flops and various
0 1 0 0 0
logic gates.
0 1 1 0 0
Find: 1 0 0 1 1
A representation of a JK flip-flop involving only D 1 0 1 1 1
flip-flops and various logic gates. 1 1 0 1 1
1 1 1 0 0
Analysis:
The truth tables for both the JK and D flip-flops are in the table shown here. There are eight
rows because there are eight combinations of the inputs J, K, and the flip-flop output Qn. The
fourth column represents the output at the next clock trigger based upon the state of the inputs.
The fifth column represents the input to a D flip-flop necessary to produce Qn+1. For a D flip-flop
the output equals that input D; that is, D = Qn+1.

12.4
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.4
Draw a timing diagram (four complete clock cycles) for A0, A1, and A2 for the circuit of Figure
P12.4. Assume that all initial values are 0. Note that all flip-flops are negative edge–triggered.

Solution:
Known quantities:
For the circuit shown in Figure P12.4, assume that all the initial values are 0. Note that all the
flip-flops are negative edge-triggered.
Find:
Draw a timing diagram (four complete clock cycles) for A0, A1, and A2.
Analysis:

12.5
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.5
Given the sequential circuit of Figure P12.5, determine the output when input A is [1 0 1 1].
Assume all A and Q are initially zero.

Solution:
Known quantities:
The circuit shown in Figure P12.5.

Find:
The output Q for the given circuit with the input 1 0 1 1.
Analysis:

The initial state is Q = 0.

Clock Input Prior State Updated Updated

State Output
CK A Qn Qn+1 Y
0 0 0 0 1
1 1 0 1 1
2 0 1 1 0
3 1 1 0 0
4 1 0 1 1

12.6
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.6
Write the truth table for an RS flip-flop with enable (E), preset (P), and clear (C) lines.

Solution:
Find:
Write the truth table for an RS flip-flop with enable (E), preset (P), and clear (C) lines.
Analysis:
Knowing that an input to the R or S line will be effective only when the enable input is 1, and the
outputs are initially 0, the truth table for an RS flip-flop with set and preset is as follows:

S R P C Q
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 1 0 0 0
0 1 0 1 0
1 0 0 0 1
1 0 1 0 1

12.7
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.7
A JK flip-flop is wired as shown in Figure P12.7 with a given input signal. Assuming that Q is at
logic 0 initially and the trailing-edge triggering is effective,

sketch the output Q.

Solution:
Known quantities:
The JK flip-flop shown in Figure P12.8, with a given input signal.
Find:
Assuming that Q is at logic 0 initially and the trailing edge triggering is effective, sketch the
output Q.
Analysis:
Jn Kn Qn+1
1 1 Q n (toggle )

Input

Output

12.8
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.8
With reference to the JK flip-flop of Problem 12.7, assume that the output at the Q terminal is
made to serve as the input to a second JK flip-flop wired exactly as the first. Sketch the Q output
of the second flip-flop.

Solution:
Known quantities:
With reference to the JK flip-flop shown in figure P12.11, assume that the output at the Q
terminal is made to serve as the input to a second JK flip-flop wired exactly as the first.
Find:
Sketch the output Q of the second flip-flop.
Analysis:

Jn Kn Qn+1
1 1 Q n (toggle )

Input

Output

12.9
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.9
Figure P12.9 shows an RS flip-flop acting as a debouncing circuit for a single-pole, double-throw
(SPDT) switch. Fill in the table to indicate the state of Q for each of the two switch positions A and B.
What is the purpose of the two 10 K resistors?

Solution:
Known quantities:
Figure P12.9
Find:
The output 𝑸 for each position of the switch.
Analysis:
Recall that the output of a NAND gate is high unless both inputs are high.

When the switch is in position B one of the inputs to the lower NAND gate is low such that the output
of that NAND gate, 𝑄, is high. Also, the leftmost 10K resistor pulls the A input high such that both
inputs to the upper NAND gate are high and the output of that NAND gate is low.

When the switch is in position A one of the inputs to the upper NAND gate is low such that the output
of that NAND gate, 𝑄", is high. Also, the rightmost 10K resistor pulls the B input high such that both
inputs to the lower NAND gate are high and the output of that NAND gate is low.

Switch position 𝑄
A L
B H

The purpose of the two 10K resistors is to pull up inputs A and B whenever those inputs are not set
low by the switch.

12.10
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.10
Figure P12.10 shows a D flip-flop with preset and clear acting as a debouncing circuit for a single-
pole, double-throw (SPDT) switch. Fill in the table to indicate the state of Q for each of the two
switch positions A and B. What is the purpose of the two 10 K resistors?

Solution:
Known quantities:
Figure P12.10
Find:
The output 𝑸 for each position of the switch.
Analysis:
Recall that, in general, the output of the D flip-flop is 𝑄 = 𝐷 = 0 at each leading (positive) edge
transition of the clock. However, the preset and clear functions override that result whenever one of
their inputs is low. (Notice their inverted inputs.) Notice that in this diagram the present and clear
inputs are always opposite each other. That is, one of their inputs is high and one is low at all times.

When the switch is in position B the CLR (clear) function causes the output of that NAND gate, 𝑄, to
be low. Also, note that the leftmost 10K resistor pulls the A input high such that the PRE (preset)
function is disabled.

When the switch is in position A the PRE (preset) function causes the output of that NAND gate, 𝑄,
to be high. Also, note that the rightmost 10K resistor pulls the B input high such that the CLR (clear)
function is disabled.

Switch position 𝑄
A H
B L

The purpose of the two 10K resistors is to pull up inputs A and B whenever those inputs are not set
low by the switch.

12.11
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Section 12.2: Digital Counters and Registers

Problem 12.11
Assume that the slotted encoder shown in Figure P12.11 has a length of 1 m and a total of
1,000 slots (i.e., there is one slot per millimeter). If a counter is incremented by 1 each time a
slot goes past a sensor, design a digital counting system that determines the speed of the
moving encoder (in meters per second).

Solution:
Known quantities:
Assume that the slotted encoder shown in Figure
P12.7 has a length of 1 meter and a total of 1,000
slots (i.e., there is one slot per millimeter.
Find:
If a counter is incremented by 1 each time a slot goes past a sensor, design a digital counting
system that determines the speed of the moving encoder (in meters per second).
Analysis:
Assuming a maximum speed of 10 m/s and a minimum speed of 1 mm/s, we can calculate the
instantaneous speed of the slotted encoder by counting the number of clock pulses between slots
using a fixed frequency clock. This resolution should be sufficient to measure the speed of the
encoder over the range of interest. The figure depicts the arrangement: A 10 kHz clock
increments a 16-bit binary counter. The choice for a 16-bit counter is due to the maximum speed
16
requirement: 2 = 65,536, will be the maximum count between slots. At a speed of 10 m/s, the
-4
time for one slot to go by is 10 s, thus the number of counts would be 1 count; at the minimum
4
speed of 1 mm/s the number of counts would be 10 . A 14-bit counter would be sufficient, but in
practice it is easier to cascade two 8-bit counters; thus the choice of a 16-bit counter. The count
is held by a latch, and then converted to BCD for use with seven-segment displays. The details
of the seven-segment display encoders are not shown (see Focus on Measurements: Seven-
Segment Display). If a decimal point is placed to the right of the second seven-segment display
(starting from the left in the figure), the display will read the speed in m/s, up to a maximum of 10
m/s, with a resolution of 1 mm/s.

12.12
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

clock
f = 10 kHz

1 mm
16-bit
signal from binary
linear position reset counter
encoder

16-bit
CK latch

binary-to-
decimal
converter
BC D
output

7-segment
displays

12.13
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.12
A binary pulse counter can be constructed by interconnecting T -type flip-flops in an appropriate
manner. Assume it is desired to construct a counter that can count up to 10010.
a. How many flip-flops would be required?
b. Sketch the circuit needed to implement this counter.

Solution
Find:
a) How many flip-flops would be required to construct a binary pulse counter, which can count
up to 10010, by interconnecting T-type flip-flops in an appropriate manner.
b) Sketch the circuit needed to implement this counter.

Analysis:
a) 10010 = 11001002 Þ 7 flip flops required.
b)

This circuit could be modified with combinational logic if it is desired to have it reset at 10010 and
start counting again from 00000002.

12.14
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.13
Explain what the circuit of Figure P12.13 does and how it works. (Hint: This circuit is called a 2-
bit synchronous binary up-down counter.

Solution:
Find:
The operation of the circuit.
Analysis:
The basic operation of the circuit is to count up when X = 0, and to count down when X = 1.

X
clk

T1

Output #1
Output #2
counting UP counting DOWN
00 01 10 11 00 11 10 01 00 11

Clock Output #2 T1 Output #1

X
­ 0 0 0 No change
­ 1 1 0 No change
­ 0 1 1 toggle
­ 1 0 1 toggle

12.15
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.14
Figure P12.14 shows a simple divide-by-2 circuit using a leading (positive) edge-triggered J-K
flip flop. Assume the clock pulse train repeats equal length low and high intervals. Draw the
corresponding timing diagram for the output Q.

clock
Known Quantities:
Figure P12.14
Find:
Timing diagram
Assumptions:
Assume positive edge–triggered devices. The DC supply voltage is VCC.
Analysis:
With both inputs tied to VCC the JK flip-flop acts as toggle (T) flip-flops. The clock input is
positive-edge triggered.

12.16
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.15
Figure P12.15 shows a simple divide-by-3 circuit using two leading (positive) edge-triggered J-K
flip-flops. Assume the clock pulse train repeats equal length low and high intervals. Draw the
corresponding timing diagrams for the outputs A and B until they both repeat.

Solution:
Known quantities:
Figure P12.15
Find:
Timing diagram
Analysis:

Problem 12.16
12.17
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Figure P12.16 shows a simple divide-by-4 circuit using two leading (positive) edge-triggered J-
K flip-flops. Assume the clock pulse train repeats equal length low and high intervals. Draw the
corresponding timing diagrams for the outputs A and B until they both repeat.

Solution:
Known quantities:
Figure P12.16
Find:
Timing diagram
Analysis:
With both inputs tied to VCC the JK flip-flops act as toggle (T) flip-flops. The clock input is
positive-edge triggered.

Problem 12.17
12.18
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Figure P12.17 shows a Johnson counter using four leading (positive) edge-triggered D flip-flops,
each with preset and clear. Draw the timing diagrams for the outputs Q0, Q1, Q2 and Q3 until
they all repeat.

Solution:
Known quantities:
Figure P12.17
Find:
Timing diagram
Analysis:

12.19
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

12.3: Sequential Logic Design

Problem 12.18
Using necessary logic gates and D-type flip-flops, create a sequential circuit (one input–one
output) from the state table given below.

Solution:
Current state Next state D = Qn+1 Output Q
Find:
Qn I=0 I=1 I=0 I=1
A sequential circuit using A A B 0 0
only D flip-flops and logic B B A 0 1
gates to realize the state
C C B 0 0
table.
D D A 0 1
Analysis:
Notice that when I = 0 the output state does not change such that Qn+1 = Qn = 0. In other words,
I acts as an enable input. When the circuit is enabled (I = 1) the output toggles between 0 and
1. An AND gate is ideal for creating an ENABLE input. See the circuit diagram here and notice
that the inputs to the AND gate are I and the inverted output of the D flip-flop; thus, the toggling
result indicated in the table.

12.20
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

12.21
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.19
Use JK flip-flops to construct a sequential circuit with the state diagram shown in Figure P12.19

Solution:
Find:
A sequential circuit involving only JK flip-flops to realize the operation of the state diagram
shown here.
Analysis:
Notice that there is a single bit input that determines whether the states Q1 Q2 increment (in the
sense of a two-bit integer) or remain unchanged. When the input bit is low (zero) the output
state does not change such that Qn+1 = Qn = 0. In other words, the single bit input acts as an
enable input. When the single bit input is high (one) the circuit is enabled and the states Q1 Q2
increment (in the sense of a two-bit integer). An AND gate is ideal for creating an ENABLE
input. The circuit can be realized as a two bit ripple counter similar to that shown in Figure
12.13. In this problem, only two states exist so the third (right-most) JK flip-flop in Figure 12.13
is not needed. Also, the clock input should be one of two inputs to an AND gate. The other
input is the single bit enable input. The output of the AND gate would then be used to trigger
the first JK flip-flop.

12.22
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

12.23
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Section 12.4: Computer System Architecture

Problem 12.20
Explain the purpose of the ALU.

Solution:
Find:
Explain the purpose of the ALU.
Analysis:
The arithmetic and logic unit (ALU) is where all computations take place, and is capable of
performing the following operations on a binary data:
• Binary addition and subtraction
• Logical AND, OR, EX-OR
• Complement
• Rotate left or right

12.24
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.21
Name the internal registers of a microprocessor, and explain their functions.

Solution:
Find:
Name the internal registers of a microprocessor, and explain their functions.
Analysis:
The internal registers include a program counter, the instruction register, general purpose
registers and temporary registers. The sequence of instructions (often called micro instructions)
is generated by a programming language similar to a high-level language such as C. To keep
track of which instruction is to be executed next, the control unit has a dedicated register, called
the program counter (PC). The program counter holds the address of either the next instruction
to be executed or the address of a multi-word instruction. When the control unit requests the
memory to transfer the data to the microprocessor, the data will be transferred into the
microprocessor through the data bus latch and then into the instruction register. Registers inside
the microprocessor are interconnected by an internal data bus. Temporary registers are used by
the control unit to hold information until it is transferred to another register or used in a computation.
To allow greater flexibility, instructions can effect transfers between general purpose registers.
The contents of the registers are stored in a stack during subroutine calls and interrupts. The
stack consists of a group of specifically allocated read/write memory; a stack pointer is required
to address a location or register in the stack.

12.25
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.22
Name the three different systems buses, and explain their functions

Solution:
Find:
Name the three different systems buses, and explain their functions.
Analysis:
The system bus is divided into three busses each with a dedicated task.
The Address Bus, which is a unidirectional bus, holds the address of the device with which the
CPU wishes to communicate.
The Data Bus, which is a bi-directional bus transfers information to or from the device.
The Control Bus contains the information about which operation is to be performed. This bus can
be considered to act on the instruction, whereas the Address Bus controls the location of this
action, and the Data Bus contains the result of the action or the input to the action.

12.26
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.23
Suppose a microprocessor has n registers.
a. How many control lines do you need to connect each register to all other registers?
b. How many control lines do you need if a bus is used?

Solution:
Known quantities:
Suppose a microprocessor has n registers.
Find:
a) How many control lines do you need to connect each register to all other registers?
b) How many control lines do you need if a bus is used?
Analysis:
a) Since there is a line connected between every 2 registers, for every one register, there should
be (n-1) lines connected. So, for n registers, there should be (n -1)´ n lines connected.
However, considering that we double-count the lines needed between 2 registers, we actually
need
(n - 1)´ n lines.
2
b) If a bus is used, register is only required to connect to the bus and no need to connect to other
registers. So only n lines are needed.

12.27
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.24
Explain the function of the status register (flag register), and give an example.

Solution:
Find:
Explain the function of the status register (flag register), and give an example.
Analysis:
The status register ( flag register) is the one used when acting on comparison statements, such
as "If Greater Than ...", etc. The Status Register is a 16-bit register, however only 9 bits are utilized.
The register looks as follows:
xxxxODITSZxAxPxC
The 'x' represents a bit which is not used, while the letters are bits which hold the following
conditions:
O Overflow Flag
D Direction
I Interrupts Enabled
T Trap Flag
S Sign of operation
Z Zero Flag
A Auxiliary Carry
P Parity Flag
C Carry Flag
As an example, when one compares two numbers and wishes to Jump to the location called
Label in the program the operation which is in fact performed is the subtraction of the two numbers
and a Jump is executed if the Zero Flag is set (i.e. Z=1). You may compare this to a GO TO
statement in FORTRAN or Basic.

12.28
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.25
What is the distinction between volatile and nonvolatile memory?

Solution:
Find:
What is the distinction between volatile and nonvolatile memory?.
Analysis:
"Static/volatile" means that memory contents do not have to be refreshed.
"Nonvolatile" means that the information in the memory is not lost when the power is off.

12.29
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.26
A typical PC has 8 Gbytes of standard memory.
a. How many words is this?
b. How many nibbles is this?
c. How many bits is this?

Solution:
Find:
If a typical PC has 8 Gbytes of standard memory:
a) How many words is this?
b) How many nibbles is this?
c) How many bits is this?
Analysis:
8 Gbytes = 8 ´ 2 30 bytes = 2 33 bytes = 8589934592bytes
1word
a) 8589934592bytes ´ = 4294967296 words
2bytes
2nibbles
b) 8589934592bytes ´ = 17179869184nibbles
1byte
8bits
c) 8589934592bytes ´ = 68719476736bits
1byte

12.30
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.27
Suppose it is desired to implement a 4-Kbyte 16-bit memory.
a. How many bits are required for the memory address register?
b. How many bits are required for the memory data register?

Solution:
Find:
Suppose it is desired to implement a 4K 16-bit memory.
a) How many bits are required for the memory address register?
b) How many bits are required for the memory data register?
Analysis:
a) We need 2 N = 4Kbytes = 4096 bits Þ N = 12. Therefore, we need 12 bits for the memory
address register.
b) The data register must be at least as large as each word in memory. Therefore, the data
register must be 16 bits in length.

12.31
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.28
Suppose a particular magnetic tape can be formatted with eight tracks per centimeter of tape
width. The recording density is 200 bits/cm, and the transport mechanism moves the tape past
the read heads at a velocity of 25 cm/s. How many bytes per second can be read from a 2-cm-
wide tape?

Solution:
Known quantities:
Suppose that a particular magnetic tape can be formatted with 8 tracks per centimeter of tape
width. The recording density is 200 bits/cm, and the transport mechanism moves the tape past
the read heads at a velocity of 25 cm/s.
Find:
How many bytes/s can be read from a 2-cm-wide tape.
Analysis:
8tracks
´ 2cm = 16tracks
cm
bits bits
16tracks ´ 200 = 3200
cm cm
bits 1byte bytes
3200 ´ = 400
cm 8bits cm
bytes cm bytes
400 ´ 25 = 10000
cm s s

12.32
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.
G. Rizzoni and J. Kearns, Principles and Applications of Electrical Engineering, 7th Edition Solutions, Chapter 12

Problem 12.29
Draw a block diagram of a circuit that will interface two interrupts, INT0 and INT1, to the INT
input of a CPU so that INT1 has the higher priority and INT0 has the lower. In other words, a
signal on INT1 is to be able to interrupt the CPU even when the CPU is currently handling an
interrupt generated by INT0, but not vice versa.

Solution:
Find:
Draw a block diagram of a circuit that will interface two interrupts, INT0 and INT1, to the INT input
of a CPU so that INT1 has the higher priority and INT0 has the lower. In other words, a signal on
INT1 is to be able to interrupt the CPU even when the CPU is currently handling an interrupt
generated by INT0, but not vice versa.
Analysis:
There are two types of interrupts: non-maskable, and maskable. When a logic signal is applied to
a maskable interrupt input (INT1 in this case), the microprocessor is immediately interrupted.
When a logic signal is applied to a maskable input (INT0 in this case), the microprocessor is
interrupted only if that particular input is enabled. Maskable interrupts are disabled or enabled
under program control.

12.33
Copyright 2022 © McGraw Hill LLC. All rights reserved. No reproduction or distribution without the prior
written consent of McGraw Hill LLC.